logic fpga

SIMULATION OF ARITHMETIC & LOGIC UNIT AND IMPLEMENTATION USING FPGA

Submitted by Md. Hasanuzzaman

ID: ECE-080200106

Md. Mahamudur Rahaman

ID: ECE-080200107

Supervised by

Ashraful Arefin Senior Lecturer Department of Electrical and Electronic Engineering Northern University Bangladesh

May 2013 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING FACULTY OF SCIENCE AND ENGINEERING NORTHERN UNIVERSITY BANGLADESH

APPROVAL The project report on “Simulation of Arithmetic and Logic Unit and Implementation using FPGA” submitted by Md Hasanuzzaman, ID-ECE080200106 and Md. Mahamudur Rahaman, ID-ECE080200107, to the department of Electronics and Communication Engineering of Northern University Bangladesh has been accepted as satisfactory for the partial fulfillment of the requirements for the degree of Bachelor of Electronics and Communication Engineering and approval as to it’s style and contents.

 Board of Examiners

…………………………………. Ashraful Arefin Senior Lecturer Department of EEE (Supervisor)

……………………………….. Lecturer Dept. of EEE

……………………………….. Lecturer Dept. of EEE

…..……………..…………………………

Engr. Md. Badiuzzaman Head Dept. of ECE & EEE i

DECLARATION

We hereby, declare that the work presented in this project is the outcome of the investigation performed by us under the supervision of Ashraful Arefin, Sr. Lecturer, Department of Electrical & Electronic Engineering, Northern University Bangladesh. We also declare that all part of this project has been submitted by us.

Supervisor

Candidates

…………………..

….........………………………

Ashraful Arefin

Md. Hasanuzzaman

Senior Lecturer Department of EEE (Supervisor)

……………………………… Md. Mahamudur Rahaman

ii

ACKNOWLEDGEMENTS First of all we would like to thank the Almighty Allah, Today we are successful in completing our project work with such ease because Allah give us the ability, chance and co-operating supervisor. We would like to thank all of our teachers for their help which made this project and thesis successful. After that we are really thankful to our head of Department Engr. Md. Badiuzzaman and our supervisor, Ashraful Arefin. Our supervisor not only gave us time but also his proper guidance and valuable advice was always with us whenever we faced difficulties. His comments and guidance helped us a lot to prepare our thesis report. We are also thankful to our teachers who helped us a lot in a number of ways by providing various resources and moral supports, all the persons related to the laboratories and classmates and friends also who collected a lot of information to make this accomplished. Finally we are grateful to our family who always with us in every step of life.

The Authors May, 2013

iii

ABSTRACT

The Arithmetic Logic Unit (ALU) is a fundamental building block of the central processing unit (CPU) of a computer and many more digital circuits. Even the simplest microprocessors contain one for purposes such as maintaining timers. In this project our main aims are the simulations of 4-bit, 16-bit and 32-bit ALU and implement them using Field Programmable Gate Array (FPGA). The FPGA configuration is generally specified using a Hardware Description Language. We have simulated 4-bit, 16-bit and 32-bit using Quartus II software. For some limitations of Altera Cyclone 2 DE1 Board here we just implement 4-bit ALU. We have got the Netlist viewer and timing diagrams for 4-bit, 16-bit and 32-bit using Quartus II software. But for the Simulation of 64 bit it shows some error whereas the chip of the PC cannot calculate too much of bits. It is possible to implement 16-bit, 32 bit and 64 bit after recover these limitations as well. So, next we will try to implement 8-, 16-, 32- and 64-bit using FPGA to recover this sort of problem.

iv

TABLE OF CONTENTS APPROVAL

I

DECLEARATION

II

ACKNOWLEDGEMENTS

III

ABSTRACT

IV

TABLE OF CONTENTS

V

Chapter 1: Introduction

1

1.1 Arithmetic logic unit

1

1.2 Methodology

2

1.3 Overview of project work

2

Chapter 2: Operations of an ALU

3

2.1 Simple operations

3

2.2 NOT gate operation and truth table

4

2.3 AND gate operation and truth table

4

2.4 OR gate operation and truth table

5

2.5 XOR gate operation and truth table

6

2.6 Full adder circuit and logic diagram with truth table

6

2.7 Adder Subtraction block

7

2.8 4:1 MUX circuit and logic diagram with truth table

8

Chapter 3: Field Programmable Gate Array

9

3.1 What is an FPGA

9

3.2 History

10

3.3 Modern Developments

10

3.4 Application of FPGA

11

3.5 Advantage of FPGA

11

3.6 Altera DE1 FPGA board

13 v

Chapter 4: Verilog Hardware Description Language

14

4.1 Hardware Description Language

14

4.2 Why verilog HDL

15

4.3 Structural Verilog Code

15

4.4 Register Transfer Level (RTL) Verilog Code

15

4.5 Comparison between Structural and RTL Verilog Code

16

Chapter 5: Implementation Using FPGA

17

5.1 Netlist view

17

5.2 Netlist RTL Viewer of 4 bit ALU

18

5.3 Timing diagram for 4 bit ALU

19

5.4 Netlist RTL viewer for 32 bit ALU

20

5.5 Timing diagram for 32 bit ALU

21

Chapter 6: Discussion

22

6.1 Limitations

22

6.2 Future work

22

6.3 Conclusion

23

Appendix Appendix A

24

Appendix B

27

Appendix C

28

References

29

vi

CHAPTER 1

Introduction

1.1 Arithmetic Logic Unit (ALU): In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. Mathematician John von Neumann proposed the ALU concept in 1945, when he wrote a report on the foundations for a new computer called the EDVAC. Research into ALU remains an important part of computer science, falling under arithmetic and logic structures in the ACM computing classification system.

1

1.2 Methodology An Arithmetic logic unit system has been developed by sequence of operations and implemented usinf FPGA. To achieve a successful ALU design we use following methodologies:  Studying literature on different types of bit and their implementation.  Studying the existing method for ALU arithmetic and logic operation.  Analyzing and designing for the proposed system  Creating the layer diagram using Verilog® code.  Implementation of the Arithmetic and Logic Unit.  Implementation of 4 bit ALU using FPGA.  Analyzing and Designing of the Netlist Viewer and Timing Diagram of 4 bit and 32 bit ALU using the Quartus II software.

1.3 Overview of project work The steps involved in the design of the logic section. 

Design the arithmetic section independent of the logic section in chapter 2.



Description about Field Programmable Gate Array and Hardware Description Language in chapter 3 & 4.



Simulation of 4-bit, 32-bit ALU and Imlementation using FPGA in chapter 5 & 6.

2

CHAPTER 2

Operations of an ALU

2.1 Simple operations Most ALU can perform the following operations: 

Bitwise logic operations (NOT, AND, OR, XOR)



Integer arithmetic operations (addition, subtraction, and sometimes multiplication and division, though this is more expensive)



Bit-shifting operations (shifting or rotating a word by a specified number of bits to the left or right, with or without sign extension). Shifts can be seen as multiplications and divisions by a power of two.

3

2.2 NOT Gate: (1) Instruction Format:

NOT Operand A

(2) Function: Operand A is an input. This operator performs the bitwise NOT operation on Operand A. The truth table defines the behavior of each bit operation shown in figure 1.1

INPUT

OUTPUT

0

1

1

0

NOT gate truth table

Fig-2.2.1: NOT gagggagate

2.3 AND Gate: (1) Instruction Format: AND Operand A Operand B (2) Function: Operand A and Operand B are two inputs. This operator performs the bitwise AND operation, and put the result in Y = A. B The circuit symbol and truth table defines the behavior of each bit operation shown in figure.

4

INPUT

OUTPUT

A

B

A*B

0

0

0

0

1

0

1

0

0

1

1

1

Fig-2.3.1: AND Gate AND gate truth table

2.4 OR Gate: (1) Instruction Format: OR Operand A Operand B (2) Function: Operand A and Operand B are two 16_bits register inputs. This operator performs the bitwise OR operation, and put the result in Y = A +B. The truth table defines the behavior of each bit operation shown in figure 3.3

INPUT

OUTPUT

A

B

A+B

0

0

0

0

1

1

1

0

1

1

1

1

Fig-2.3.1: OR gate OR gate truth table

5

2.5 XOR Gate: (1) Instruction Format: XOR Operand A Operand B (2) Function: Operand A and Operand B are two 16_bits register inputs. This operator performs the bitwise XOR operation, and put the result in

Y=A

B

The truth table defines the behavior of each bit operation shown in figure 3-(a). The circuit symbol is shown in figure 3-(b).

INPUT

OUTPUT

A

B

A XOR B

0

0

0

0

1

1

1

0

1

1

1

0

Fig-2.5.1: XOR Gate XOR gate truth table

2.6 Full adder circuit and logic diagram with Truth table:

Full Adder: A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from the next less significant stage. The full-adder is usually a component in a cascade of adders. The circuit produces a two-bit output sum typically represented by the signals Cout and S. 6

Full adder circuit diagram and Truth table:

Fig-2.6.1: Full adder circuit diagram

2.7 Adder Subtraction block: The addition and subtraction operations can be combined into one circuit with one common binary adder. This is done by including an exclusive –OR gate with each full adder. A 4 bit full adder-subtractor circuit is shown below this figure. The mode input S controls the operation. When S = 0, the circuit is an adder, and when S = 1, the circuit becomes a subtractor. Each exclusive –OR gate receives input S and one of the inputs of B. When S = 0, we have B ⨁ 0 =B. The full adders receive the value of B, the input

carry is 0, and the circuit performs A plus B. When S = 1, we have B ⨁ 1 =B and C0 =1. The B inputs are all complemented and a 1 is added through the input carry. The circuit performs the operation A plus the 2’s complement of B.

7

Fig2.7: Adder Subtraction diagram.

2.8 4×1 MUX circuit and logic diagram with Truth table: MUX: In communication transmission and computer networking systems a mux is a device that sends multiple signals on a carrier channel.

4×1 MUX circuit diagram and Truth table:

Fig-2.8.1: 4×1 MUX circuit diagram 8

CHAPTER 3

Field Programmable Gate Array

3.1What is an FPGA: A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing—hence "field programmable ". The FPGA configuration is generally specified using a hardware description language (HDL). An FPGA is similar to a PLD (Programming Logic Design) but whereas PLDs are generally limited to hundred of gates, FPGA supports thousands of gate.

Also an FPGA contains a matrix of reconfigurable gate array logic circuitry that, when configured, is connected in a way that creates a hardware implementation of software application.

9

3.2 History: In the late 1980s the Naval Surface Warfare Department funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.

3.3 Modern Developments: Three major vendors provide FPGA hardware. (1) Xilinx inc (2) Altera corp (3) Laltice semiconductor corp

Xilinx : Xilinx is basically the one who invented the FPGA and is currently the biggest name of the FPGA world.

ALTERA : Altera tools have more intuitive feel at the GUI. For most users, navigating through the menu and searching for bits of code is more user friendly. Another thing that is easier to do with altera, is viewing the timing analysis results.

ALTERA DE1 board : The Altera DE1 board is useful for learning about digital logic, computer organization and FPGA.It is suitable for wide range of exercise and the board designed for university and college laboratory use.

Cyclone 2 : Cyclone 2 FPGAs provide a wide range of density, memory, embedded multiplier.FPGA feature set optimized for low cost applications.Supports a wide range of common external memory interfaces.I/P protocols common in low cost applications, plus intellectual property (IP) cores make using cyclone 2 FPGA interfaces and protocols easy. 10

3.4 Application of FPGA :  Video and Image Processing.  Digital Signal Processing.  Medical Imaging.  Computer Vision.  Speech Recognition.  Comuter Hardware Emulation.  Radio Astronomy.  Aerospace and Defense.  Broadcast.  Consumers Electronics.  Distributed Monetary System.  High Performance Computing.  Security.  Wired Communications.  Wireless Communications.

3.5 Advantage of FPGA :  Flexible Development: Many FPGA devices provide dedicated funtional blocks such as DSPs. This means that the funtional blocks of a system can be readily moved between software, compiled hardware and DSP inside the FPGA devolopment.

 Reduced devopment time and risk: It is possible to reduce development time and risk still further with the increasing number of commercial off-the-shelf

11

(COTS) FPGA hardware development kits. If a suitable hardware platform can be found your product can be produced with no hardware development.

 Maintainig a markeet in your supply chain: Once a product is implemented in an FPGA based design the specific FPGA used can be changed for an equivalent part with minimal re-development time. This has made the FPGA market extremely competitive.

 Simplification of logistics: Another advantage of the FPGA approach is that the PCB, although not simple, contains common interface blocks.

 IP blocks: There has always been an active market for IP blocks. These are usually provided as VHDL or linked netlists that can be implemented into an ASIC, Structured ASIC or FPGA. This market has until recently been focused on chip manufacturers. With the increasing use of FPGAs in embedded systems this market has expanded and many companies produce IP for sale or free distribution.

12

3.6 Altera DE1 FPGA Board : Family: Cyclone 2 Name: EP2C20F484C7

Fig 3.6.1 Altera DE1 FPGA board.

13

CHAPTER 4

Verilog Hardware Description Language

4.1 Hardware Description Language: HDL based design technique has been emerged as the most efficient solution for any complex design. It offers the following advantages over convention design approaches: It is technology dependent. If a particular IC fabrication process becomes outdated, it is possible to synthesize a new design by only changing the technology file but using the same HDL code. HDL shortens the design cycle of a chip by efficiently describing and simulating the behavior of the chip. A complex circuit can be designed using a few lines of HDL code. It lowers the cost of design of an IC. It improves design quality of a chip. Area and timing of the chip can be optimized and analyzed in different stages of design of a chip.

14

4.2 Why Verilog HDL: There are different types of HDL available in the market. Some of it is vendor dependent where the HDL code is only usable under the software provided by the specific vendor. For example, AHDL from Altera Company, Lola from European silicon structure company etc. However, Verilog HDL and VHDL (Very high Speed IC Hardware Description Language) are now widely accepted industry for digital system design. VHDL is popular in European countries and Verilog HDL is widely used in Asia and America.

4.3 Structural Verilog Code: It describe the components and interconnections present in a design. Design Automation (EDA) tool compiles and synthesizes the RTL code of a design and produces the netlist of the design in the form of structural code. Verilog® of 4 bit ALU structural Code is shown in Appendix A

4.4 Register Transfer Level (RTL) Verilog code: Digital circuit can be represent in different ways such as gate level representation, transistor level representation etc. RTL acronym Register transfer level is also another type of representation style for digital circuit. Any complex digital system can be partitioned into different modules where each module is basically consists of registers and gates. Information is stored in the registers and specific operation is performed using the information and then it is transferred among the registers. Hence the said representation style is known as RTL. Verilog® of 4-bit ALU RTL Code is shown in Appendix B Verilog® of 32-bit ALU RTL Code is shown in Appendix C

15

4.5 Comparison between Structural and RTL Verilog Code:

RTL Verilog Code

Structural Verilog Code Structural design is the oldest digital logic

This is the method currently used for the

design method.

design of complex logic circuits such as microprocessors.

The Designers Selects the low level

It Determines the numbers and sizes of

components and decides exactly how they

registers needed to hold the data used by

are to be connected.

the device.

A Structural design can be represented as a

It determines the logic and arithmetic

parts list and a list of the connections

operations that needed to be performed on

between the pins and the components. This

these register contents.

representation of a circuit is called a Netlist. It supports in any types of circuit

Editing and simulations are much easier.

16

CHAPTER 5

Implementation using FPGA

5.1 Netlist Viewer There are two netlist viewers, the RTL Viewer and the Technology Viewer. Each viewer opens a different netlist file type, but many of the viewer functions are the same. The information supplied in the RTL Viewer and Technology Viewer help pages applies to both viewers, unless otherwise specified. RTL Viewer The RTL Viewer enables you to view a Register Transfer Level (RTL) netlist as a schematic when you use Xilinx® or Quartus II as your synthesis environment. This representation is in terms of generic symbols, such as AND and OR gates, and is generated after the parsing and elaboration phase of the synthesis process. Viewing this schematic enables you to see a gate-level representation of your HDL.

17

5.2 Netlist RTL Viewer of 4 bit ALU (code shown in Appendix B)

Fig5.2.1: 4 bit ALU Netlist RTL Viewer for the Appendix B.

18

5.3 Output Timing Diagram for 4 bit ALU (code shown in Appendix B):

Fig5.3.1: Output Timing Diagram of 4 bit ALU.

19

Fig5.4.1: Netlist RTL Viewer 32 bit ALU for the Verilog® code Appendix C. 20

5.5 Output Timing Diagram for 32 bit ALU (code shown in Appendix C):

Fig5.5.1: Output Timing Diagram of 32 bit ALU.

21

CHAPTER 6

Discussion

7.1 Limitation: 

There are only ten input switches that are why Altera DE1 board showing only 4 bit ALU.



The propagation delay was not a matter of concern during our design.

7.2 Future work: 

In the future we will try to add extra bit and showing over 4 bit ALU.



As well as we will try to minimize the propagation delay.



In

future

we

will

try

to

increase

22

the

number

of

operations.

7.3 Conclusion: It is reasonably straightforward to modify the adder circuit to perform either addition or subtraction (depending on a control input). This forms a simple ALU. Practical ALU are capable of a wide variety of arithmetic and logical operations. The operation is selected by a control input selection word, S. Despite their complexity, they are only logic. The main message of this paper is this experimental assumptions, tools and techniques can have a significant impact on the conclusion of FPGA architectural experiments and need to be considered carefully when conclusion to be presented.

23

Appendix A module alu( A3,B3,A2,B2,A1,B1,A0,B0, S1,S0,out5,out4,out3,out2,out1); input A3,B3,A2,B2,A1,B1,A0,B0; input S1,S0; output out5,out4,out3,out2,out1; wirew39,w40,w41,w42,w43,w44,w45,w46; wire w47,w48,w49,w50,w51,w52,w53,w54; wire w55,w56,w57,w58,w59,w60,w61,w62; wire w63,w64,w65,w66,w67,w68,w69,w70; wire w71,w72,w73,w74,w75,w76,w77,w78; wire w79,w80,w81,w82; xor xor xor xor

xor(w2,B3,w16); xor(w7,B2,w16); xor(w11,B1,w16); xor(w15,B0,w16);

and and(w16,w37,S0) not

inv(w37,S1);

and and and and

and(w25,B3,A3); and(w28,B2,A2); and(w31,B1,A1); and(w34,B0,A0);

or or or or

or(w29,A2,B2); or(w32,A1,B1); or(w35,A0,B0); or(w26,A3,B3);

and and(out5,w38,w37,w5); not

inv(w38,S0);

xor xor

sub_1(w39,A3,w2); sub_2(w4,w39,w3);

and sub_3(w40,w3,w39); 24

and sub_4(w41,w2,A3); or xor xor

sub_5(w5,w40,w41); sub_6(w42,A2,w7); sub_7(w9,w42,w8);

and sub_8(w43,w8,w42); and sub_9(w44,w7,A2); or sub_10(w3,w43,w44); xor sub_11(w45,A1,w11); xor sub_12(w13,w45,w12); and sub_13(w46,w12,w45); and sub_14(w47,w11,A1); or xor xor

sub_15(w8,w46,w47); sub_16(w48,A0,w15); sub_17(w17,w48,w16);

and sub_18(w49,w16,w48); and sub_19(w50,w15,A0); or not not and and and and not not and and and and not not

sub_20(w12,w49,w50); sub_21(w51,S1); sub_22(w52,S0); sub_23(w53,S1,S0,w26); sub_24(w54,w51,w52,w4); sub_25(w55,w51,S0,w4); sub_26(w56,S1,w52,w25); sub_30(w59,S1); sub_31(w60,S0); sub_32(w61,S1,S0,w29); sub_33(w62,w59,w60,w9); sub_34(w63,w59,S0,w9); sub_35(w64,S1,w60,w28); sub_39(w67,S1); sub_40(w68,S0);

and sub_41(w69,S1,S0,w32); 25

and sub_42(w70,w67,w68,w13); and sub_43(w71,w67,S0,w13); and sub_44(w72,S1,w68,w31); not not

sub_48(w75,S1); sub_49(w76,S0);

and and and and

sub_50(w77,S1,S0,w35); sub_51(w78,w75,w76,w17); sub_52(w79,w75,S0,w17); sub_53(w80,S1,w76,w34);

endmodule

26

Appendix B module alu (A, B, S, OUT); input [3:0] A, B; input [1:0] S; output [4:0] OUT ; reg [4:0] OUT ; always @* begin case (S) 0: OUT 1: OUT 2: OUT 3: OUT endcase end endmodule

27

= = = =

A+B; A-B; A&B; A|B;

Appendix C module alu (A, B, S, OUT); input [31:0] A, B; input [1:0] S; output [32:0] OUT ; reg [32:0] OUT ; always @* begin case (S) 0: OUT 1: OUT 2: OUT 3: OUT endcase end endmodule

28

= = = =

A+B; A-B; A&B; A|B;

References 1. Digital logic and circuit design by Morris Mano 2. Digital logic design by principles wiley 3. Altera DE1 development board – user manual 4. http://en.wikipedia.org/wiki/Field-programmable_gate_array 5. http://www.altera.com/devices/fpga/cyclone2/features/cy2-

features.html 6. http://www.altera.com/education/univ/materials/boards/de1/unv-de1-

board.html 7. http://www.altera.com/products/fpga.html 8. http://ece353.ecs.umass.edu/verilog/verilog_examples.html 9. http://www.dilloneng.com/documents/howto/coding_style.v/view 10. http://www.altera.com/products/software/sfw-index.js 11. http://www.mouser.com/new/altera/altera-quartus/ 12. http://www.experiencefestival.com/arithmetic_logic_unit_-_history 13. http://search.edaboard.com/4-bit-alu-vhdl-code.html 14. http://www.edaboard.com/thread202709.html 15. http://web-ext.u-aizu.ac.jp/~yliu/teaching/comparch/lab1.html 16. http://stackoverflow.com/questions/16661670/design-a-32-bit-

arithmetic-logic-unit-alu-in-verilog-using-active-hdl 17. http://quartushelp.altera.com/12.0/mergedProjects/verify/rtl/rtl_view.h

tm 18. http://www.edaboard.com/thread20771.html 19. http://www.af-inventions.de/en/our-services/fpga-design/fpga-advantages/

29