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A new design methodology is presented for outputting digital infor- mation from asynchronous analogue circuits, which allows signed frequency encoded signal ...
Low-power pulse-width-modulated neuromorphic spiking circuit allowing signed double byte data transfer along a single channel D.J. Banks, P. Degenaar and C. Toumazou A new design methodology is presented for outputting digital information from asynchronous analogue circuits, which allows signed frequency encoded signal transfer along a single channel. The circuit outputs data as a series of rate and pulse-width encoded spikes: pulsewidth modulation is used to represent vector and pulse frequency modulation is used to represent magnitude symbiotically. This technique can be used to increase the bandwidth of multiplexed neural signals, such as for address event registration, or by using a time-tofirst-spike system, to multiplex signals on a single channel. Additionally, feedback has been used to improve the switching speed of current starved inverters, reducing their power consumption by over an order of magnitude.

Introduction: To communicate with digital logic, low-power, asynchronous, analogue circuits need to output information that can be read by digital systems. To do this, many systems utilise frequency encoded outputs, which may be directly represented by a series of digital pulses [1]. Originally developed by Carver Mead, this technique has been mimicked from the information communication processes of the human nervous system [2]. Biological neurons use 100 mV pulses (often referred to as spikes) as a means of communicating information between neurons. This form of communication can negate signal losses in noisy environments, by using analogue lowpass filtering at the synaptic connections to remove highfrequency noise, allowing each communication pulse to effectively traverse around the body [3]. Spike information content is generally thought to be contained in the frequency of pulses arriving at a node from specific locations, and we have adopted this coding system. Neuromorphic circuits and devices are artificial systems designed to function in a similar way to the sensory and neural structures and signal processing architectures of neurobiology [4, 5]. Many acquire data from a natural stimulus, and as such they need to process information with over 120 dB of dynamic range [6, 7]. Effective adaptations of real-time neural systems require highly parallel computing architectures [8]. Within the human nervous system an individual sensory neuron may have over 1000 direct interactions between other neurons [3]: this level of connectivity between parallel processing units is not possible to replicate within CMOS at the present time, so other techniques for increasing bandwidth and interconnectivity are necessary. CMOS architectures are constrained by the limit of electrical interconnects and output buses. However, in direct comparison to neurobiology, individual lines in CMOS have a higher bandwidth than neuronal axons, allowing multiplexing of signals [3]. In a step towards increasing interconnectivity between analogue parallel processing circuits and digital systems, we have developed a methodology allowing signed data transfer along a single channel with frequency-modulated spike trains [9, 10]. Our scheme significantly improves the output bandwidth, and allows multiplexed data on a single channel. Additionally, our methodology reduces power consumption of the input stage by over an order of magnitude by using a feedback system to increase the switching speed of current-starved inverters.

Circuit design: The pulse-width-modulated spiking circuit is a variation of the capacitive neuron developed by Carver Mead [1, 2]. This circuit was simulated using the Spectre simulator within the Cadence integrated circuit design environment with foundry administered models for a standard 0.35 mm process. For these simulations all the transistor sizes are 2  2 mm with Monte Carlo mismatch indicating a 4% maximum variation in output. Fig. 1 shows a system level schematic of the circuit, and a cartoon of the pulse output. Charge accumulates on the gate capacitance, reset source and feedback drain, at the input of the circuit, which over time increases the voltage at that node. As charge builds up, the node voltage reaches the input inverter threshold voltage. This switch outputs a pulse of controlled width and resets the input node to ground after a specific delay, after which the charging process begins again. The delay blocks are a

series of p-MOS current-starved inverters biased by a controlled voltage. By varying the current through the delay blocks the output pulse width and reset delay time can be accurately controlled between 100s of nanoseconds and tens of milliseconds. Fig. 2 shows the frequency response of the simulated circuit. As the threshold is reached, positive feedback opens the input node to Vdd, speeding the switch time and reducing power consumption. This switch then sets two delay blocks into operation: one to control the spike width; and the other to control reset delay. A bias within the delay circuit directly controls the spike width of the output signal, and the reset time. A reset delay is necessary to separate reset time from spike width; in this way multiple circuits can be connected to the same channel and output information of different pulse width and the same reset delay.

Fig. 1 System level diagram showing pulse-width-modulated spiking circuit with positive feedback Pulse width and delay are controlled by voltage bias on current starved inverters. Positive feedback is used to improve timing and switching speed, and reduce power consumption

Fig. 2 Power consumption of current-starved inverters with and without positive feedback in a 0.35 mm process As positive feedback speeds switching process, spike of charge precedes switching of improved current-starved inverter

Multiple neurons can share the same channel by using the time-tofirst-spike technique, which is used by nature and engineers as a useful means of data reduction in frequency-encoded systems [11, 12]. If a channel is sampled at 50 MHz then up to 100 neurons can be connected synchronously, where a shift register is used to cycle between the neurons. Taking into account the maximum variations through mismatch and process calculated with Monte Carlo analysis to introduce a guard time, each neuron can have 10-bit dynamic range. Feedback: This circuit employs positive feedback to reduce power consumption and speed the switching time of the inverters. Using this technique the inverters are only current starved until the switching threshold is reached. At this point positive feedback opens the input gate voltage to Vdd and the inverter is quickly switched, as can be seen in Fig. 3. The power consumption of these inverters is reduced by over an order of magnitude.

ELECTRONICS LETTERS 21st June 2007 Vol. 43 No. 13

References

Fig. 3 Frequency response with bias voltage of low-power pulse-widthmodulated neuromorphic spiking circuit Varying voltage over 600 mV changes pulse frequency between 100s of nanoseconds and tens of milliseconds

Conclusions: Our system resolves a significant problem with neuromorphic spiking systems, that of signed data, and bridges the gap between signed data within digital systems and neuromorphic processing systems. The human body deals with this through increased connectivity; however, in an artificial silicon environment this is not preferential, so techniques such as ours, which increase the bandwidth of neuromorphic communication systems, are necessary. We have also used positive feedback to improve the use of current-starved inverters in delay systems and reduce power consumption in neuromorphic spiking circuits.

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# The Institution of Engineering and Technology 2007 17 May 2007 Electronics Letters online no: 20071440 doi: 10.1049/el:20071440 D.J. Banks, P. Degenaar and C. Toumazou (Institute of Biomedical Engineering, Imperial College London, South Kensington Campus, London SW7 2BT, United Kingdom)

ELECTRONICS LETTERS 21st June 2007 Vol. 43 No. 13