Low Power Sigma-Delta Modulator with Dynamic Biasing ... - CiteSeerX

Low Power Sigma-Delta Modulator with Dynamic Biasing for Speech CODECs Fun Ye, Jen-Shiun Chiang, and Chun-Cheng Wu Department of Electrical Engineering, Tamkang University, Tamsui, Taipei, Taiwan

Abstract In this paper the design of a low power sigma-delta modulator with dynamic biasing is presented. This design uses simple analog and digital components to achieve the low power purpose. In order to get a 12-bit resolution over the 4-kHz signal bandwidth for voice band applications such as PCM CODECs, an optimum choice is the second order modulator with an oversampling ratio of 128 and sampling frequency of 1.024MHz. To achieve low power, the dynamic biasing technique is used in our design. To implement the SDM, the modulator has been designed with fully differential switched capacitor integrator by the TSMC 0.35-um 2P4M CMOS process. The sigma-delta modulator achieves a 80-dB dynamic range, and the power consumption is only 1.4mW by a single 3.3-V supply.

I. Introduction Sigma-delta ADCs fulfill an important role in today’s mostly digital mixed-mode systems as interface circuits between the analog word and the powerful digital processing environment. Oversampling and noise shaping are the two key techniques employed in these ADCs. Sigma-delta converters and modulators are always used to pass analog signal into digital signal processing units for most audio applications. The advantages of these converters include relaxed requirements for anti-aliasing filters and component matching, high resolution, and compatibility with digital VLSI technology [1]. In addition, there is a great interest in low power and low voltage ADCs, which strengthens the importance of low power oversampled A/D converters [2]. Opamps are the most power consuming components in sigma-delta ADCs. To decrease the power dissipation of the

converters, new architectures with fewer opamps [3],[4],[5] and opamps with dynamic biasing [6] were proposed. In this paper, a modified clocked bias scheme is used to implement the sigma-delta modulators (SDM) with dynamic biasing. The low pass filters of the second order modulator in the first stage and second stage are implemented by non-inverting switched capacitor integrators and inverting switched capacitor integrators respectively. The clock of the SDM has different requirements for four-phase switches, comparator, low-level current bias circuit, and high power bias circuit. They are implemented by the modified clock generator.

II. SDM Design The block diagram of a second order sigma-delta modulator is shown in Fig. 1. X(z)

Y(z) H1(z)

H2(z)

z−1 DAC

Fig. 1 Block diagram of a second order sigma-delta modulator. The difference between the proposed architecture and the traditional SDM architecture is in the part of the second stage. In the proposed second order SDM, the transfer functions of the two stages are different and the transfer functions of H 1 (z) and H 2 (z) are as follows:

H 1 (z) =

z −1 1 − z −1

(1)

H 2 (z) =

1 1 − z −1

(2)

We add a unit delay block to the feedback path of the second stage to satisfy the SDM architecture. In the circuit level, a non-inverting switched capacitor integrator is used to implement the first stage low pass filter H 1 (z) . On the other hand an inverting switched capacitor integrator is used to implement H 2 (z) . Fig. 2 shows the circuit configuration of the whole second order SDM with the input and reference sampling circuit. Vref+ VrefVcm

Vcm Cint1

φ 2 d φ1 Vin+

φ1d Cin1 φ 2

+ -

Vin-

Cin1

φ1d

- + Op1

φ2 φ 2 d φ1

Cint2

φ1d

φ 2d Cin2 φ 2 Cin2 φ2 φ 2d φ1d φ1

Cint1 Vcm

φ1 + -

+ -

- +

- +

Op2

Vo+ Vo-

where g m is the transconductance of the amplifier’s input device and C l is the output load of the amplifier. To satisfy low power requirements and maintain the desired error voltage, it needs to reduce the transconductance required and increase the time available for settling. Practically it can be achieved by increasing the current level during the portion of the slewing duration. The power consumption during slewing is not dependent on the slew current value [6]. The slewing can be completed in a very short period with a higher current, and it has the same average power per clock cycle compared with the use of a lower current during the whole clock cycle. However, a net power saving can be achieved because of a lower g m . For the characteristic of a MOS device in strong inversion, the equation of the relation between the transconductance and the bias current is shown as follows:

Comparator

gm =

Cint2 Vcm

2K' (L/W)I bias ,

(4)

VrefVref+

Fig. 2 Circuit configuration of the proposed second order SDM

III. Dynamic Biasing The amplifier of the switched-capacitor integrator can be divided into three distinct operation tasks: slewing, settling, and holding an output value. The operations of slewing and settling are during phase 2 ( φ 2 ), and holding an output value is during phase 1 ( φ1 ). For the SDM design, the bias-level of the operation amplifier is decided by the slewing and settling requirements. However, the bias of each task is different, power savings can be achieved by considering the bias required level during each of these tasks. The tasks during each phase are described as follows:

where g m is proportional to the square root of the bias current, and thus the power saving can be significant. If the slewing is forced to be less than 3/8 of the clock phase, it can achieve the desired power saving. In our design, in order to have more time available for settling, we choose 1/5 of the clock phase for slewing. The bias level during the 1/5 of the clock phase is increased by a factor of four compared with the bias level during the settling phase, and the profile is shown in Fig. 3. Although there is a power saving during this phase by this arrangement, it is limited. We only have a small gain in the settling time at the expense of a very large bias change. φ2

(slewing and settling)

φ1

(holding) 4I

3.1 Phase 2: Slewing and Settling

Ibias

The error voltage, Ve (t) , after settling a disturbance Vi is V e (t)

=

V ie

− t ⋅ g m /C l

(3)

I I/4 0 1/5

1

2

t, us

Fig. 3 Bias current profile during each phase.

3.2 Phase 1: Holding Considering the amplifier requirements during phase φ1 , we can find another power saving approach. The output of the amplifier during φ1 only operates in the mode of holding an output value, and it will not be sampled by the following integrator. Therefore during this phase, the bias level can just be chosen to assure that the adequate time is made available to settle the amplifier chopping artifacts. The bias current can be reduced to one-fourth of the level during settling. By this arrangement, the idle current can be saved and it can accomplish the power savings. Fig. 3 shows the current profile in the amplifier during different working tasks.

IV. Circuit Design In the circuit design, the SDM needs extra circuits to implement the dynamic biasing. Furthermore, the current mirrors in the amplifier of the SDM are needed to rearrange. The SDM consists of the amplifier with rearranged current mirrors, high–level current bias, modified low-level current bias, and modified clock generator. The modified clock generator is for the four-phase switches, comparator, and high-level current bias control. They are respectively described as follows:

4.1 Amplifier The folded-cascode opamp is used to implement our proposed SDM. The inputs of the PMOS differential pair are chosen to minimize the noise and enhance the non-dominant pole. To implement the current increase from the nominal value for slewing, a parallel set of clocked current sources is used. Fig. 4 is a simplified schematic of the amplifier. The high-level current sources are designed as Ih or 2Ih. These sources are turned on only during the portion of phase φ 2 , and for another duration they must be turned off well. The low-level current sources are designed as Il and 2Il. They are always turned on during the clock cycle. These sources have higher current during phase φ 2 . During phase φ1 , the current is switched to lower current state. It does not affect the performance at the end of the settling phase to use the parallel

arrangement since the sources are off. M3 and M4 are used to improve the PSRR.

4.2 Low-level current bias circuit The complete low level current bias circuit is shown in Fig. 5. This circuit is a modification of the wide-swing constanttransconductance bias circuit [7] which has wide-swing current mirrors and a start-up circuit. The main difference of the circuit from the wide-swing constanttransconductance bias circuit is the switching current mirror. The switching current mirror has a switch at the device drain controlled by pulse p to steer the appropriate current value.

4.3 High-level current bias circuit Fig. 6 shows a simplified schematic of the high-level current bias circuit [6]. Device M4 is the output device, and in the on-state it mirrors device M1. In the on-state, current Ih mirrors current Id3, and current Id3 matches current Id2. In the off-state, Id2 is changed by a factor of a large value, and it is used to assure the shutdown of the circuit. The control pulse p steers the appropriate current value to turn on or turn off the output current.

4.4 The modified clock generator In order to get synchronous clocks for the four-phase switches, comparator, and high-level current bias circuit, the modified clock generator is used and is shown in Fig. 7. It is a modification circuit of the four-phase clock generator proposed by Greets et al. [8]. The original circuit generates the clocks with properties of non-overlaping and delay. Adjusting the sizes of the loop inverters, the time of non-overlaping and delay can be controlled. The clock can reduce the signal-dependent charge injection effectively. The different part from the original circuit is that two extra paths are added. An inverter and a nand-gate are included in path 1. Adjusting the size of the inverter, the desired pulse width can be achieved to control the switch of the high-level current bias circuit in the on-state. The comparator is triggered during phase φ1 . In order to avoid triggering in the bias current changing state of the amplifier, the comparator cannot be triggered on the

edge of φ1 ; it has to be triggered after a delay time. Path 2 adds a buffer from node1, and the desired delay time can be controlled by adjusting the buffer size. Ih

Il

Il

Ih

Ih

Ih

CMFB

vbp in-

in+

M3

vbp

out-

out+

vbn

M4

vbn

2Ih

2Il 2Il

2Ih

Fig. 4 Folded cascode amplifier with a parallel set of clocked current source

V. Circuit Simulation Results The proposed SDM is designed by TSMC 2P4M 0.35um process. The input signal is with 2kHz bandwidth. After the HSPICE simulation, we use FFT of MATLAB to find the power spectrum density of SNDR and dynamic range. The dynamic range is 80dB over 4kHz bandwidth. The SNDR is 77dB, which can achieve a 12-bit resolution and the oversampling ratio is 128. The reference voltage is ±0.5V. Fig. 8 shows the simulated output spectrum of the SDM. Table I summarizes the simulated performance. The SDM power dissipation of 1.4mW is substantially lower than that of the prior works with similar performance [9], [10].

vbp1

0

vbp2

Am plitude [dB]

− 20

vbn2

vbn1

Ir

Io

p

− 40 − 60 − 80

R

Cascode bias

Bias loop

Switching current mirror

SNDR = 77dB

− 100

Start-up circuit

− 120

Fig. 5 Low-level current bias circuit with switching current mirror

10 2

103

10 4

105

Frequency [Hz]

Fig. 8 Output spectrum Table I. Modulator specification Id2 Ir Pb

Pb

P

M2

M1 10x

10x

Signal bandwidth

4 kHz

Ih

Sampling Frequency

1.024 MHz

M4

Dynamic Range

80 dB

SNDR

77 dB

Supply Voltage

3.3 V

Power Consumption

1.4 mW

Technology

0.35

M3

1x Id3

Fig. 6 Clocked high-level current bias circuit φ2

φ 2b

φ2d

φ 2 db

Path2

VI. Conclusion

φc Buf

φ1d

φ1db

φ1

φ1b φ

Path1

Fig. 7 The modified clock generator

2P4M

CMOS

node1

CLK

um

h

In this paper, a low power SDM is designed for pulse-coded modulation (PCM) CODECs in voice band application. A dynamic biasing technique is used to implement the SDM; it can achieve lower power consumption. Simulated results show

that the resolutions can achieve about 12 bits, and it can fit the required resolution for PCM CODECs. The technique offers significant power savings with expected performance.

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[6] D. B. Kasha, W. L. Lee, and A. Thomsen, “A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing,” IEEE Journal of Solid-State Circuits, vol. 34, no. 7, pp. 921-926, July 1999. [7] D. A. Johns and K. Martin, Analog CMOS Integrated Circuits, Wiley, 1997 [8] Y. Greets, M. Marques, M. S. J. Steyaert, and W. Sansen, “A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1MHz for ADSL applications,” IEEE Journal of Solid-State Circuits, vol. 34, no. 7, pp. 927-936, July 1999. [9] O. Bajdechi and J. H. Huijsing, “A 1.8V ∑ ∆ modulator interface for electric microphone with on-chip reference,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 279-285, March 2001. [10] M. Keskin, Un-Ku Moon, and G. C. Temes, “A 1-V 10-MHz clock-rate 13-bit CMOS ∑ ∆ modulator using IEEE unity-gain-reset opamps,” Journal of Solid-State Circuits, vol. 37, no. 7, pp. 817-824, July 2002.