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Low Voltage Power Efficient Tunable Shaper Circuit With Rail-To-Rail Output Range for the HYDE Detector at FAIR J. Galán, R. López-Ahumada, T. Sánchez-Rodríguez, A. Torralba, Senior Member, IEEE, R. G. Carvajal, Senior Member, IEEE, and I. Martel
Abstract—This paper presents a low voltage, low power readout front-end system implemented in 130 nm CMOS technology. A conventional architecture that consists of charge sensitive amplifier, pole/zero cancellation and shaper has been used. The work focuses on the design of novel circuit topologies in low voltage environment minimizing the power consumption in modern deep submicron CMOS technologies. An operational amplifier with rail-to-rail output swing that uses a gain boosting technique and class-AB output stage without extra power consumption has been used for the shaper. The circuit combines excellent performances with simplicity of design and suitability for low voltage operation. The system is intended to work with silicon detectors for nuclear physics applications and is optimized to match an input capacitance of 10 pF. The system features a peaking time of 500 ns, a power dissipation of 1.57 mW/channel and an equivalent noise charge of . Index Terms—Current efficiency, deep submicron CMOS technology, front-end electronics, gain boosting techniques, silicon detectors.
I. INTRODUCTION
T
HE nuclei near the drip lines are very different from that of stable nuclei, and radioactive beam facilities (RBF) provide a unique workbench to investigate nuclear structure and dynamics by exploiting the isospin degree of freedom [1]–[3]. There is a number of new RBFs foreseen to be operative in the next two decades, like SPIRAL2 at GANIL (Grand Accélérateur National d’Ions Lourds in Caen, France), FAIR at GSI (Gesellschaft für Schwerionenforschung in Darmstadt,
Manuscript received May 13, 2013; revised August 09, 2013; accepted January 18, 2014. Date of publication March 04, 2014; date of current version April 10, 2014. This work was supported by the Spanish Ministry of Science and Innovation, FEDER funds under grant FPA2010-22131-C02-01/02, and by the Andalussian Innovation, Science and Enterprise Council under grant P10-TIC6311 and FQM-2010-4964. J. Galán, R. López-Ahumada, and T. Sánchez-Rodríguez are with the Department of Electronic Engineering, Computer Systems and Automatics, University of Huelva, E-21071 Huelva, Spain (e-mail:
[email protected];
[email protected];
[email protected]). A. Torralba and R. G. Carvajal are with the Department of Electronic Engineering, University of Sevilla, E-41092 Sevilla, Spain (e-mail: carvajal@gte. esi.us.es;
[email protected]). I. Martel is with the Department of Applied Physics, University of Huelva, E-21071 Huelva, Spain (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNS.2014.2302008
Germany), SPES at LNL (Laboratori Nazionali di Legnaro in Legnaro, Italy) and EURISOL (location to be decided), which will accelerate radioactive nuclear beams with intensities several orders of magnitude higher than today’s ones, allowing the study of very rare and short-lived nuclei not presently available. Therefore the development of a new generation of particle detectors becomes critical. Such development should focus on R&D on silicon, front-end electronics and control systems. Particle identification techniques based on digital pulse shape analysis should be investigated and developed in the case of these highly segmented silicon detectors. The energy range provided at the Low-Energy Branch (LEB) at FAIR facility [4] (Darmstadt, Germany) will make it possible to investigate the effect of Coulomb and nuclear fields at time scales relevant for the structure of exotic nuclei. The HYbrid DEtector array (HYDE) [5] is a highly segmented charged particle silicon-detector designed to study direct nuclear reactions, elastic and inelastic scattering, break-up, and transfer reactions of exotic nuclei. Such studies will provide complementary information for values, quadrupole deformations, spectroscopic values, collective phenomena and nucleon-nucleon correlations for very exotic nuclei with half lives down to the microsecond. In this paper we present recent developments in low power CMOS technologies for the design of the Front End Electronics of the HYDE detector. Typical HYDE silicon-detector cell will contain double-sided silicon strip detectors (DSSSDs) with a total of 512 spectroscopic channels in atypical capacitance range between 5-50 pF, depending on wafer thickness. Front End Electronics must have good properties for performing nuclear spectroscopy with heavy ions: energy resolution below 30 keV, wide dynamic range up to 50 MeV, and a bandwidth above 100 MHz allowing for digital pulse-shape identification of ions. Although some multichannel ASICs have been developed in the past [6]–[8] they do not fulfill the required channel density or the spectroscopic specifications for DSSSDs. Present work is a first step towards the development of such dedicated ASICs in the low energy region (up to 5 MeV). These studies shall be also of common interest for the new nuclear physics silicon arrays TRACE being built for the SPES facility at LNL (Legnaro, Italy) [9], FAZIA and GASPARD array for the SPIRAL2 facility (Caen, France) [10].
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II. LOW VOLTAGE LOW POWER READOUT SYSTEM: PRELIMINARY CONSIDERATIONS The downscaling of CMOS technologies reduces the supply voltage, while the trend to integrate a large number of readout channels forces the minimization of the power consumption per channel. Digital circuits benefit from downscaling due to a minimization of the area, and a reduction in the power consumption thanks to the reduction of the supply voltage. But this is not the case for analog circuits as, with the size reduction, minimum length transistors increase noise and reduce the output resistance, and with the supply voltage reduction, the signal swing decreases [11]. Under these adverse conditions, to preserve or even increase circuit performances in modern technologies, efforts are required both, in the architectural and circuit levels. The design of an operational amplifier (opamp) is a good example (an opamp is considered here to be a differential amplifier whose voltage gain is large enough to take advantage of feedback). The operational amplifier is the main building block in the analog front-end of the readout electronics system; it is used as the active element in charge sensitive amplifiers (CSA) and shapers [12]–[16]. Basic properties of operational amplifiers in these applications are low-noise, high dc gain and large gain bandwidth (GBW) product. Nevertheless, in modern deep submicron technologies, the reduction of the output resistance of transistors, which operate in saturation region, limits the open loop gain of amplifiers, and the increasing transistor threshold to supply voltage ratio precludes the application of cascode stages with several stacked transistors. The development of novel amplifier topologies and operation modes is required, since the simple scaling of the supply voltage using existing design approaches drastically reduces the circuit performances. This paper addresses these issues and proposes compact topologies that provide high current efficiency. A shaping circuit with optimized low power consumption and high dynamic range has been designed. The proposed circuit uses, as a building block, a single-stage current mirror amplifier with a gain boosting technique in the active load of the input differential pair (which provides the largest part of the overall gain), while a class-AB rail-to-rail output stage ensures good driving capability. The power consumption is low, as these properties are achieved without extra power consumption, and the amplifier does not require a compensation capacitor. In addition, a folded-cascode preamplifier with optimized noise performance has been designed. It uses a novel class-AB output buffer to drive the load with low quiescent current. The preamplifier-shaper channel has been developed for charged particle detection using silicon detectors, and optimized for a detector capacitance from 1 to 10 pF. III. SHAPER CIRCUIT DESCRIPTION The shaper is responsible for amplification, signal to noise ratio (SNR) improvement and signal shaping. Operational amplifiers based on conventional class-A topologies are not appropriate for low power operation, since their biasing currents are constant and limit the maximum output current. On the other hand, class-AB amplifiers have well-controlled quiescent currents, which can be made low to reduce
Fig. 1. (a) Two-stage topology. (b) One-stage current mirror topology.
power consumption, while their maximum output currents can be much larger than their quiescent values. A two-stage operational amplifier is a topology suitable to obtain a compact design for low supply voltage, as shown in Fig. 1(a). It achieves an open loop gain of about without cascode transistors ( and are the small signal transconductance, and the output resistance of transistor , respectively). Nevertheless, a Miller compensation capacitor may be necessary to guarantee the stability, reducing the GBW and increasing the tail current of the differential pair. Fig. 1(b) shows a current mirror amplifier with a current ratio of , where is the gain of the n-channel current mirrors. The amplifier consists of a p-channel input stage , , and two n-channel current mirrors , , which copy the input current to the rail-to-rail output branch. The current mirror amplifier is the only single-stage topology that can provide rail-to-rail output swing [11]. As every single-stage topology, it is load compensated ( ). It is well-known that, for a given GBW and , . Considering that , then . As the output current is , the total static current is
(1) The same analysis can be made for the two-stage topology. Considering that the non-dominant pole created by the load ca, that is, pacitance should be placed beyond three times
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Fig. 2. Gain enhancement technique.
Fig. 3. (a) Class-AB output conventional. (b) Class-AB output based on QFG transistors.
in the best case, the total (best case) quiescent current is . Therefore, the current mirror amplifier is the topology preferred to reduce the power consumption for a given GBW. The main disadvantage of the current mirror amplifier is the low open-loop voltage gain, which is only in the order of . In deep submicron technologies this value can be around 20-30 dB, since the output resistance is quite low. Note that the overall voltage gain is the same as that of a single transistor. Although the transconductance is times increased by the current mirror gain, the output resistance is reduced in the same factor ( , where is the channel-length modulation factor of transistor ) due to the amplification of the biasing current. Thus the open-loop voltage gain is approximately given by
(2) According to behavioral simulations, the active shaper implemented here requires an amplifier with more than 35 dB of open-loop gain. If a current mirror topology were selected, some kind of gain enhancement technique should be used. Finally, concerning noise, the current mirror amplifier suffers from larger thermal noise when compared to a folded-cascode amplifier because its input transistors are biased with a lower proportion of the total bias current and therefore have a smaller transconductance. Thus, for the design of charge sensitive amplifiers, a folded-cascode topology is often preferred since noise is of primary concern for these amplifiers. A. Gain Enhancement Amplifier As mentioned before, in the current mirror amplifier it is difficult to obtain, at the same time, high transconductance and high output resistance. The circuit gain can be enhanced if the biasing current of the output branch is reduced, but maintaining the ac current gain. To this end an additional current source can be placed in parallel with the diode-connected transistors to sink part of their dc current, increasing the ratio [17], [18], as shown in Fig. 2.
If the new current source carries times ( ) the quiescent current of , the biasing current of the output transistor is . Substituting in (2) yields,
(3) appears in the dc gain of the An increasing factor of current mirror amplifier compared to the conventional topology. Note that the gain enhancement is achieved without extra power consumption. B. Class AB Output Stage Class-AB output stages make an efficient use of the biasing current and provide rail-to-rail signal swing, but care must be taken to avoid an excessive contribution of the class-AB control circuitry to the amplifier noise, power consumption, and silicon area. A conventional approach for class-AB operation of the complementary output stage in Fig. 3(a) is to drive the PMOS transistor by a floating voltage source . This level-shifter transfers the signal swing from node to the gate of transistor , boosting the dynamic load current. The proposed compact class-AB output stage is shown in Fig. 3(b). It consists of two common-source connected output transistors, a diode connected transistor and a capacitor . The transistor operates in the cutoff region acting as a very large resistive element. The capacitor acts as a floating battery as it cannot quickly charge/discharge through . For the frequencies of interest changes in the voltage at node X will be immediately transferred to node Y; only in steady state condition the capacitor will slowly discharge through the large resistance of transistor , and the voltage at node Y will tend to . The value of can be very small and still the time constant associated to will be in the order of milliseconds. Under quiescent conditions, and given that no dc current flows through , the voltage at the gate of is the same as at the gate of ( ). Thus, the biasing of the output transistors is controlled by the voltage , providing a well-defined quiescent current. is called a quasi-floating gate (QFG) transistor, as reported by some of the authors in [19]. Note that the QFG biasing does not modify the noise performance of the
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Fig. 5. Scheme of the implemented readout front-end electronics.
Fig. 4. Proposed current mirror operational amplifier for the shaper circuit.
the circuit: the noise contribution of the MOS-based resistance to the output SNR is negligible since it is not the channel resistance of an active transistor but the leakage resistance of a transistor operating in the cutoff region. C. Proposed Amplifier for the Shaper Circuit The proposed operational amplifier for the shaper circuit is shown in Fig. 4, which is a current mirror amplifier with gain enhancement and class-AB output branch. Note that both, gain boosting and class-AB operation, are achieved without sacrificing static power consumption and with only a few modifications in the conventional current mirror amplifier. In nominal conditions the biasing current of the operational amplifier has been set to A. The current through transistor is adjusted at and the size of is ten times larger than that of . The minimum supply voltage of the output stage is , where is the minimum for operation in saturation (about 0.1 V). Therefore the circuit is suitable for low voltage operation. If necessary, a second stage could be added to this design, like a buffer composed by a common-drain stage to provide a low output resistance and increase the of the amplifier, at the cost of higher power consumption. IV. APPLICATION TO FRONT-END ELECTRONICS Fig. 5 shows the scheme of the designed readout front-end detection system. The charge generated by the detector is integrated by a preamplifier or charge sensitive amplifier (CSA) and converted into voltage pulses with an amplitude equal to . These pulses are fed to a band-pass filter which shapes them according to timing requirements, and filters noise to maximize the signal to noise ratio. Parameters in the frequency domain, such as bandwidth, cutoff frequency, and filter order determine the shaper time domain behavior, i.e., the peaking time of the output pulse, which is directly related to noise performances. The semi-Gaussian pulse shaper consists of one differentiator followed by two active second-order Sallen-Key (SK) sections with complex poles. An amplifier in non-inverting configuration ( ) has been also included to set the gain of the overall shaper section.
Fig. 6. Topology of the preamplifier.
A shunt resistor in parallel with capacitor is adjusted to cancel the undershoot at the shaper’s output due to the preamplifier feedback pole. To achieve proper pole/zero cancellation should be selected to be equal to , where and are the feedback components of the preamplifier. The analog front-end is designed in a standard 130 nm CMOS technology with 1.2 V supply voltage. A. Preamplifier Although the noise of the readout front-end depends on its building blocks, in practice, it is dominated by the preamplifier noise. Noise matching is concerned with optimal choice of the parameters at the input stage of the preamplifier, including transistor dimensions and bias conditions. The noise also depends on some parameters, such as the input capacitance (including sensor capacitance, and parasitic capacitors connected to the input node), the peaking time, and the maximum power allocated to the input MOS transistor of the preamplifier [20]. As noise is the main specification, a folded-cascode topology has been used for the preamplifier, as shown in Fig. 6. Although this architecture is basically a (load compensated) single gain stage, its gain is quite reasonable, as it is given by the product of the input transconductance and the output impedance at the drain of . The transconductance is determined by the size and biasing current of the input transistor ( ), and cascode techniques are used to increase the output impedance. The active load formed by transistors and is a cascode current mirror. The circuit includes a transistor in cascode configuration with the input transistor to boost the gain. The drain current of is determined by and the ratio of to and .
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The open-loop gain is given by (4) (apThe first non-dominant pole is placed at the source of proximately in , where is the total capacitance at the source of transistor ). Stability of the preamplifier can be enforced by proper sizing of transistors to ensure a high value of and a low value of . An output buffer has been included to drive the load. Usually this stage needs a high current to fulfill the bandwidth requirement of the preamplifier. Transistors and the bias current form the output buffer in Fig. 6. This is a class-AB approach, where the transistor is biased by drain terminal instead of by source terminal, as in a classic class-A buffer (source follower). In the conventional source follower stage, the maximum output current is limited by the biasing current. In Fig. 6 voltage is set by and the size of , and is held constant independently of the output current. The current delivered to the load is provided by transistor and it is not limited by the biasing current source . To quickly charge the feedback capacitor the class-AB output buffer automatically boosts dynamic currents, yielding maximum current levels well above the quiescent current . Unlike the conventional voltage follower, the sinking capability is limited by the biasing current source. Nevertheless, this issue does not degrade the performances of the circuit, as the voltage pulse slowly discharges by the feedback resistance connected in parallel to . This class-AB buffer can operate at a low supply voltage with low power-consumption. Concerning the preamplifier reset mechanism, a PMOS transistor biased in the triode region has been used instead of a polysilicon resistor, that otherwise would have increased the area, parasitic capacitance, speed and noise [22]. By changing the bias gate voltage of the PMOS-based feedback resistor, the decay time of the voltage step can be adjusted to fulfill speed constraints. B. Shaper Topology The shaping filter provides a voltage pulse whose amplitude is proportional to the energy of the detected particle. The bandpass frequency response improves the signal to noise ratio by filtering the noise out of the bandwidth of interest. In addition, the shaper provides additional voltage gain and shortens the output signal. Front-end readout electronics usually employs continuous time filters with active topologies [23]; they achieve high linearity and high signal to noise ratio (SNR), at the expense of low bandwidth due to the closed-loop operation. Recently transconductance-C ( ) filters have also been proposed for these applications [21]. filters are power efficient because the amplifier unity gain frequency is comparable to the filter pole. Nevertheless, the use of an excessive number of transconductors necessary to build a biquadratic section contributes to reduce their power efficiency. In addition, the most stable and controlled pulse shapes are obtained using
Fig. 7. Fourth-order low-pass filter with SK topology.
active filters with passive linear elements in the feedback loop, as the filter poles depend on the passive components as long as the open-loop gain of the amplifier is large enough. In this work we use a fourth order active filter where the amplifier power consumption is reduced with respect to other closed-loop filters thanks to the proposed current mirror amplifier previously described. Fig. 7 shows the scheme of the shaping filter [24]. A conventional Sallen-Key topology [25] has been used, which is attractive for low power and low noise since it only requires one single amplifier per biquadratic section. The second-order low-pass filter transfer function is given by (5) The procedure used to design the Gaussian filter follows the method proposed in [26]. The simple differentiator (highpass section) in Fig. 5 realizes a real pole ( ), which determines the time constant. The two complex conjugated poles obtained by the 4th order SK topology are in the positions:
(6) The relation between the time constant of the differentiator and the real pole is given by , where , and is the time constant of a filter. For ns, has been set to 5 pF yielding k . The complex pole pairs are , where and are the real and imaginary parts, respectively. From (6), . In order to simplify the design, all resistances are set to the same value , yielding . Applying the same procedure for the imaginary part, yields . The coefficients , and are provided in [26] for each second-order stage of the filter. In our case, the nominal values included in the SK filter for ns, are the following: k , pF, pF, pF, pF. For ns the peaking time of the Gaussian filter is about ns. V. NOISE ANALYSIS Noise optimization is of primary concern in readout front-end systems. In fact, low noise and power consumption are the main features of the proposed shaper. These advantages are achieved by using a single amplifier per biquad. Moreover, the class-AB behavior and the gain boosting scheme included into the current mirror amplifier do not contribute to power consumption and noise.
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Fig. 8. Chip microphotograph.
In a well-designed readout CMOS front-end channel, the total system noise is determined by the preamplification stage, and thus a careful design according to low noise criteria should be performed [23], [27], [28]. The dominant noise sources of a CMOS transistor are thermal and flicker noise. The latter has become more important in modern technologies. Regarding noise optimization for the preamplifier, the input noise is given by the detector capacitor, the input MOS transistor type, dimensions and biasing current, and by the peaking time. The peaking time specification defines the bandwidth of the shaper, and hence, determines the dominance of thermal or flicker noise. For a 500 ns peaking time, the white noise may not dominate over the noise. In fact, simulation results confirm that the noise is not negligible in the region of frequency around 1 MHz for the selected 130 nm CMOS process. A p-channel MOS input transistor has been chosen for the preamplifier in order to reduce the noise contribution. Transistors , and are the main contributors of noise in the preamplifier of Fig. 6. Usually the transconductance of is enlarged to focus on the noise optimization on this transistor. A large value of transconductance means that the input transistor should have a large ratio and a large quiescent drain current. Thus a noise-power consumption tradeoff must be made. Other parameters, such as peaking time and shaper order are also involved in the noise performances. The peaking time (500 ns), the filter order ( ) and the total detector capacitance (10 pF) are fixed specifications in this work. From [28], , where is a constant that includes other parameters directly related to thermal noise. , in turn, is directly related to power consumption. This design is focused on achieving a good compromise between noise and power consumption. A transconductance of 15 mA/V has been selected here and the calculated thermal noise contribution from the input transistor is about 146 electrons. Including the flicker noise contribution, the total ENC noise is 201 electrons. VI. EXPERIMENTAL RESULTS The readout channel has been designed and fabricated in a 130 nm CMOS process, operating with a single 1.2 V supply voltage. Fig. 8 shows a microphotograph of the circuit. The active area of the chip is m m mm . The design parameters for the different blocks are given as follows: for the preamplifier stage, the feedback capacitor has a value of 1 pF to meet the required sensitivity
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(45 mV/MeV) and the reset device was fixed to behave as a nominal resistor of M to satisfy the decay time constraints. The high value of the active feedback resistance ensures a good trade-off between noise and count rate. A transconductance of 15 mA/V matches a detector capacitance of 10 pF to optimize noise. A well-known method for noise optimization has been followed to design the preamplifier [20], [23], [29]. An aspect ratio ( ) of m m for the PMOS input transistor was chosen according to the theoretical calculations described in a previous section. The folded-cascode preamplifier was biased with 1.1 mA. The ratio of the bias current of the input transistor to the current of the cascode branch was set to 4. Hence, the current consumption of the input branch was about 0.9 mA, and for the cascode branch was A. The power consumption of the preamplifier is about 1.4 mW including the bias current for the class-AB output buffer with A. The circuit has been designed in such a way that the input transistor contributes more than 75% to the total preamplifier noise. The gain-bandwidth product ( ) for the preamplifier was 230 MHz ensuring a fast response and an open-loop gain of 51 dB. Fig. 9 shows the measured preamplifier output signal for a detector capacitance of 10 pF and an input energy of 1 MeV. The gain of 1 V/pC ( ) provides a signal amplitude of about 45 mV. The rise time (10% to 90% of the amplitude) is 40 ns and the preamplifier discharge time is s. Note that the decay time can be tuned by changing the gate bias voltage of the reset device, to allow fulfilling different speed specifications. Regarding the shaper section, the main parameters must be set according to the peaking time and the dynamic range. Table I shows the nominal shaper performance characteristics. The gain enhancement technique applied to the proposed current mirror amplifier (Fig. 4) used in the Sallen-Key filter, increases the open-loop gain from 28 to 41 dB using a value of in (3). This value is higher than the minimum gain requirement of 35 dB determined by simulations for the implemented active filter, as it was discussed in Section II. The biasing current of the proposed current mirror amplifier is A. The current through transistor is adjusted at and transistor is ten times wider than . Thus the total supply current is A( W). The unity-gain frequency of this amplifier is 57 MHz. Since the low-pass Sallen-Key section exhibits unity passband gain (0 dB), a non-inverting stage sets the gain of the overall section shaper to . The same topology of the current mirror amplifier in Fig. 4 has been used for this non-inverting stage. The total quiescent current dissipation of the shaper is only A( W). This low power consumption confirms the suitability of the proposed current mirror operational amplifier. The full readout front-end system consumes 1.57 mW, 89% of it allocated to the preamplifier. For nominal values of all components of the readout front-end system, the peaking time is 500 ns. In order to keep the flexibility of the system, the peaking time can be tuned to implement three values: 250 ns, 500 ns and s. Fig. 10 shows the shaper output signal and the peaking time programmability for an input energy pulse of 3.5 MeV and a detector capacitor of 10 pF. The amplitude is about 400 mV, close to the maximum
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Fig. 10. Measured peaking time programmability.
Fig. 11. Measured energy response and dynamic range.
Fig. 9. Measured preamplifier output signal for an input energy of 1 MeV. (a) Zoom of the rise time. (b) Tunability of the feedback active resistance.
TABLE I DESIGN PARAMETERS FOR THE SHAPER
linear range. The tunability of the system is accomplished by switching all the polysilicon passive resistors of the Sallen-Key shaping circuit and the resistance of the differentiator. A small secondary overshoot in the transient response can be observed, which lasts about 500 ns and is well below 5% of the peak value. It is due to a mismatch between resistances and . Although the measured overshoot amplitude is small, the amplitude resolution could be degraded limiting the maximum input charge rates. Some techniques could be applied to solve this problem [23], [30], and [31]. The circuit solution proposed for the shaper using an operational amplifier with gain enhancement and rail-to-rail output swing allows the system to increase the input energy range due
to the lack of cascode output transistors. Nevertheless, the use of a PMOS input transistor in the preamplifier imposes a low common-mode voltage that could limit the output swing, so that the mentioned benefits of not using cascode transistors in the shaper might be diminished. A control voltage shown in Fig. 5, has been included to set the common-mode voltage of the shaper to 400 mV. This value allows a wide energy range of the front-end system. The linearity of the system was measured using a calibrated pulse generator; the corresponding energy response and dynamic range are shown in Fig. 11. The output peak amplitude should be linear for a given input range of charge. Note that the linearity is maintained better than 1% up to 4 MeV. The system provides an input charge-voltage output conversion of 2.5 mV/fC. The ENC is for a detector of 10 pF and the noise performance increases with a slope of pF. VII. CONCLUSIONS A low voltage, low power readout front-end system has been presented for use of silicon detectors in the construction of the HYDE detector for FAIR. This work proposes new techniques and circuit architectures to achieve high gain and current efficiency in deep submicron CMOS technologies within the constraint of low voltage operation. By proper topology selection, the shaper section enables the usage of single-stage amplifiers with rail-to-rail output swing. A gain enhancement technique has been adopted in a current mirror amplifier to overcome its low gain. This technique avoids the use of cascode transistors, increasing the output swing range. In addition, a class-AB output stage has been used for high current
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efficiency. The gain boosting and the class-AB approaches are achieved without extra power consumption. The flexibility of the design allows adjusting the decay time, and the peaking time. Experimental results have been provided with a prototype fabricated in a 130 nm CMOS technology.
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