(MI)/sup 2/L: multiinput-multioutput integrated injection ... - IEEE Xplore

IEEE JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL. SC-14, NO. 5, OCTOBER

807

1979

(MI)2L: Multiinput-Multioutput Injection Logic WONCHAN

KIM, PETER K. SEEGEBRECHT,

Abstract–The (MI)2 L structure wilf be discussed, which is a combination of CHL/CHIL and 12L, taking advantage of ion implantation. It provides improved speed-power product and functional density compared to conventional 12L schemes. The gate consists of a lateraf n-p-n transistor with intermediate collectors and a Schottky inverter. The device fabrication is fully compatible with standard bipolar processes for analog circuits. The approach is applied to a standard bipolar process of 6 ym epi thickness and 35 V breakdown voltage. The results obtained are a minimum power-delay product of 0.07 pJ and a minimum deIay of 17 ns at 0.38 pJ. The improved device parameters, packing density, and design flexibility are discussed with the experimental results of test circuits, including a D-type frequency divider and MS fhp-flop.

AND

it is a digital

circuit

concept, not a new technology,

diffusion profiles are optimized for the n-p-n transistors and the resistivity and thickness of the epitaxial layer are constrained taxial

by the required

breakdown

layer and the poor upward

transistors limit lay time

voltages of the analog

The large storage of minority the gate propagation

of 12L gates with

carriers in the epi-

current delay.

with

the

technological

analog circuitry yet still digital circuit part. II. The form

GATE

of the

are basically

used in the

AND

circuits

upside-down

operation

with will

analog

be

the n-p-n

mode.

circuits,

carried

out

1) To increase Gummel

the upward number

and

current

One attractive

tacts for the inverter

is

of 20 V and 100 ns

12L structure

the compatibility

by the CHL/CHIL

a modification

of the

that

the

following

by a

emitter-to-collector

2)

To

decrease

ume of the lightly

the

minority

doped

carrier

storage

by a small

vol-

epit axial layer.

A. Basic Gate Structure The (MI)2 L gate consists of a lateral n-p-n transistor intermediate

collectors integrated

and a Schottky

inverter,

with

which

as shown in Fig, 1. Principally

are

modified form of CHIL, where the collector-base junctions of the inverter are replaced by Schottky collectors. The injector

de-

technology

optimization with analog

approach is the use of Schottky

injection-coupled

are

to main-

The minimum

in place of base-collector

which is provided

It offers additional

original

transistors

functionally

junctions

concept [6],

it is a

current can be switched on and off by the intermediate lectors for logic implementation, while the multicollector current

flows

colin-

mainly

the lightly doped p-region due to the large Gummel across the p+-wall. If the collector IN1 is floating,

con-

i.e., not connected

[4] .

charged up and reinject the electrons to the next collector IN2. If the collector IN2 also floats, the Schottky inverter turns on since INZ acts simultaneously as its base. If, on the other hand, one of the collectors is not floating, it will hog all the injector current; hence, the Schottky inverter turns off.

This scheme combines the p-n-m inverter with a lateral n-p-n injection and leads to 10 ns with a technology adapted to 12L only and using ion implantation for n-Schottky contacts on a p-type epitaxial layer [5]. Another way of improving the effective gate delay time for a given logic function is to take advantage of the input flexibility,

in the

gain of the inverter

an optimum

through number

devices.

by

of the

In order

such

However,

only, not necessarily retaining

imposed

are met.

verter offers the normal 12L functions. In the given structure, the injected

are for

The

FABRICATION

12 L/CHIL

due to the fact that

compatibility

small

DESIGN

shortcomings

constraints

enables design optimization

To improve gate performance, much research has been carried out with innovative processes and device technologies. most of them

collectors.

gain of the n-p-n

linear compatible

about 50 ns for a process with breakdowns for a 30 V process [3].

with intermediate

area ratio.

12L circuits realized with conventional bipolar processes show limitations in speed-power performance. This is because the

circuitry.

structure

The target of this work was to find a new process which is compatible

requirements

NTEGRATED injection logic (12L) has been introduced as a low-power high-density bipolar logic [1] , [2] . Although

L. ENGL

problem is the increased charge storage.

12 L technology

I. INTRODUCTION

basically

WALTER

expanded injector

tain

I

Integrated

[7].

AND and OR gates by an

Manuscript received April 4, 1979; revised June 18, 1979. The authors are with the Institut fur Theoretische Elektrotechnik de~ Rheinisch-Westfalischen Technischen Hochschule Aachen, Aachen, Wesl Germany.

to an inverter

in the ON state, it will be

In contrast to the layout with the original 12L gates where logical combinations are made by dotting collector outputs of separate devices, this implementing three-output

gate offers

rent does NOT flow through OR C, current

flows

through

Q= A”B+C.

001 8-9200/79/1000-0807$00.75

a straightforward

way of

logic function. h example of a three-input, logic gate is given in Fig. 2. If the injected cur-

Q 1979 IEEE

the control the Schottky

collectors A AND B collectors:

IEEE JOURNAL

808

1NJ

I N2

IN,

OF SOLID-STATE

CIRCUITS,

VOL. SC-14, NO. 5, OCTOBER

1979

OUT1 0UT2

Ill

II

SCHOTTKY

COLLECTORS

(a)

Fig. 3. Cross section of (MI)2 L and analog n-p-n device structure.

=%r IN1

1N2

OUT,

TABLE I PROCESSFLOW

0UT2

(b)

1.

As buried

2.

B turied

3.

n epi ta xia[ layer

layer layer

de ..6

Fig. 1. (MI)2 L gate, (a) Schematic cross section. (b) Equivalent circuit.

dqwsi

W,

L.

B“ implan r ation

5.

BN deposition

t ion

p.20cm

no= 10’3 cm”2 , E=150 keV

~.2@3 6.

POC$

7.

contact

8.

Al deposition

and

drive-in

w.

diffusion ps= 8 w. holes 10 ~

and

dell n~tion

detail

(a)

feature, in addition

E!?YDEAB+’

to the convenient

logic configuration,

multiinput-multioutput

offers a high degree of flexibility

to the

circuit designer and leads to a good wireability. Finally,

(b) Fig. 2. (MI)2 L elements.

The same result is obtained

(a) Layout.

modifications

mentioned

before,

two

are made to the standard bipolar

process, and the result is shown in Fig. 3. The isolation

dif-

fusion process is divided into two steps, before and after the deposition of the epitaxial layer. The up-diffused p-type buried layer forms the emitter of the Schottky inverter and the base of the later-al n-p-n transist ors, It reduces the volume of the lightly doped epi layer, and hence the minority carrier boron implantation

is employed

for the

base region of the lateral n-p-n transistor. To avoid an additional oxidation step, photoresist is used as a mask during the ion implantation. The processing sequence is given in Table I. It requires seven masking steps for digital and analog devices. This analog-compatible lowing advantages.

digital

technology

provides the fol-

any double

EXPERIMENTAL

RESULTS

A. DC Characteristics

the size of the output

are characterized

transistor is substantially

duced to the minimum metal width by replacing collector diffusion by Schottky collectors.

re-

the multi-

Thirdly, the low sheet resistivity of the n’-diffusion allows the metal interconnection lines to cross the injector rail, This

digital technology

as follows:

Minimal

contact window:

Minimal

metal width:

8X8pm2

Base width of the lateral transistors:

12#m 8 Mm.

For the analog n-p-n transistors, the lateral p-n-p, and vertical p-n-m transistors, typical device parameters are given in Table II. An essential property Schottky

inverter.

of (MI)2 L is the operation

The dependence

of the

of the gate currents

on

input voltage is shown in Fig. 4. For the measurement, the injector is grounded to account for the reinfection from the inverter to the adjacent injector. It enables the determination the effective upward current gain of the inverter peff

The impurity profiles can be optimally adjusted for digital circuits without influencing the device parameters of analog circuits. Secondly,

III.

The design rules for the analog-compatible

In order to meet the requirements

Furthermore,

point of view, the gate struc-

in terms of voltage if defined in

B. Device Fabrication

storage.

a technological

diffused inverter structure. This makes scaling down feasible, and hence promises the possibility of low-power bipolar largescale integration.

(b) Logic circuit.

positive logic. This layout is used as a basic gate for the MS flip-flop, which will be discussed in the following section,

technological

from

ture consists basically of two layers only, without

.

k IB

of

(1) J“inj=f)

which ranges in this work from 50 to 100 under normal operating conditions. This current gain is relatively high compared to a normal

12L gate and is due to the increased inverter

rent and the decreased injector Considering diffusion

the effective

cur-

current for a given voltage,

epi thickness of 2 ~m after the up-

of the p-type buried layer and the epi concentration

KIM et al.: MULTINPUT-MULTIOUTPUT

INTEGRATED

INJECTION

LOGIC

809

TABLE II TYPICAL DEVICE PARAMETERSOF ANALOG AND DIGITAL TRANSISTORS npn

analog

7.2

‘VEBO ‘“C

I

lateral

V

npn

7.2

vertical

pnm

V

7.2

V

7,2 V

11.0

v

Ii’ 7L.O V

BO

350v

I

‘“CEO

I

70v

I

50v

I

165 -

1F Ic

167

/“

~ 5P ~ 7p

/

v+p lB

“

I 500

600 m

‘B%

800

Fig. 5. Zc and Zb versus VEB for the lateral n-p-n transistor with the base width as parameter. The injecting emitter length is 84 pm.

lateral n-p-n transistor is given by

r~

I

500

400

600

700

~ mV

Fig. 4. Ic and lb versus V~

for the Schottky inverter. the diagram of the test assembly.

Also shown is

QB, P-n-m

has the

~P-n-rn .—

. =w

(J%#-m/~T)

An-p-n

ew

(~&$’-n/~T)

(3) “

Because the n-p-n base is realized by overcompensating the epi laYer, which forms the p-n-m base, QB, n.~.n is larger than QB,P.n-m;

of 2.5 X 101s cm-3, the base of the p-n-m transistor equivalent

= QB,.-P-.

Ic, n-p-n

moreover,

~P-n-rn

>~n-p-n

and

~%n”m

>

~gip-n.

Accordingly, 1=,p-n-m is always larger than 1., n.p.n, which is not the case with normal 12L gates. The dependence of lC and lB on VB~ of the lateral n-p-r? transistor and the test structure used are shown in Fig. 5. The

dose

n ‘depiXN~pi=

5 X 1011 cm-2

base current is independent of the base width variation the recombination is concentrated near the p-n junction.

which is much lower than the dose

since The

collector current, on the other hand, follows (2), whereby n =3

X 1012 cm-2

normally

used for analog transistors.

Accordingly,

for a given

VBE the smaller Gummel number enables larger collector

cur-

rents. At the same time the base current is reduced due to the decreased recombination in the emitter region. This is in contrast to the normal 12L where a large hole recombination can be caused in the large region of the low concentrated epi emitter [8] . For the gate current gain, as defined in (l), towards the injector

results in a larger contribution

current than the above-mentioned Employing the relation Ic

the reinfection to the base

recombination

current.

A . exp (VBE/VT)

(2)

a

the collector

current

of a transistor,

tive

emitter

area and QB is the Gummel

the

current

ratio

for

the

vertical

where

p-n-m

A is the effec-

number

of the base,

transistor

and

the

a

WB

(4)

m

WB eff stands for the actual base width. The transfer characteristics of an (MI)2 L gate are shown in Fig. 6.

While the off state shows the same characteristics

as

conventional gates, the output voltage saturates in the ON state to the forward Schott& voltage of about 300 mV. B. Current Hogging of the Schottky In case of saturation collectors they

QB for

QB

work

Collectors

of the p-n-m inverter,

show a unique behavior.

the Schottky

For the non floating

as an SBD clamped transistor,

thus reducing

case, the

propagation delay. If, on the other hand, the collectors are floating, the holes injected into the base of the inverter will have to recombine

with the electrons from the injector.

For a

multicollector transistor, the increased recombination due to the floating collectors results in a drop of the current gain of the nonfloating ones. The processing of the (MI)2 L structure, however, always enables a high current gain, as was’ demon-

IEEE JOURNAL

810

OF SOLID-STATE

CIRCUITS,

VOL. SC-14, NO. 5, OCTOBER

1979

-7001

—x—

. . \

-600

‘1 1

-500

1 -Loo

Ji \ L

-300

-200

“OOL————— 0

-100

-200

-300

-Loo

-500

-600

-700

v, ~

.lpd

10ns loonw

1OnW

1(LW

mV

Fig. 6. Transfer characteristics of the (MI)2 L gate.

lpJ

.2pJ

I loofLw

loflw

PoWER

Fig. 8. Power-delay characteristics of the unmodified 12L and (MI)2L. This is using a 6 #m epi and a technology for 35 V breakdowns.

lo~ -

/-” /

(a)

‘CE=VBE -

(b)

/

/

,03

/ / ,./

,.2

4: 10~A

10Q~A

lmA

Ic

./

(c) Fig. 7. Worst case measurements of gate current gain. (a) Test circuit. (b) Test structure. Each collector area is 24 X 24 Km*. (c) peff as a function of Zc with the number of floating collectors as a parameter. (For the nonfloating case, see Fig. 4.)

10’

,01

,00

102

&

103

pw

strated in (3), which helps to overcome the current-hogging problem. This is proven by a worst case measurement carried out on a gate with an FO = 4. In this investigation, the ~eff, as defined in (l), was measured for several combinations of floating and nonfloating collectors. The test structure as well as the experimental

results are shown in Fig. 7. &.f f is still larger

than 1.5, even if three of four collectors are floating. C

Gate Performance

Fig. 9. Plot of toggle frequency versus power consumed by a D-type divide-by-two circuit. The circuit for two-state frequency divider is also shown.

These improvements

also apply to more complex logic func-

tions, e.g., D-t ype and MS-type flip-flops, Fig. 9 shows the photomicrograph of a ~-type FF and the toggle frequency as a function of the power consumed by a divide-by-two circuit.

The average propagation delay versus power per gate for both the conventional and modified 12L is shown in Fig. 8.

The frequency divider requires six gate delays per clock cycle, and therefore the maximum toggle frequency of 10 MHz implies a gate delay of 17 ns. ‘‘ ~~

The data were taken on the 9- and 15-stage ring oscillators with FO = 2, whereby the unused collector is floating. The reduction in charge storage and increase in current gain are evident. The (MI)* L gates show an improvement in the

An MS-type frequency divider was also built to demonstrate the design flexibility y resul~~ng from multiinput gates, the basic gate of which is discussed iri*Section II. Fig. 10 shows the photomicrograph and the logic circuits.

power-delay over conventional 12L. It ranges from 0.07 pJ at low currents to 0.4 pJ for minimum gate delay of 17 ns, which is competitive

with

other LSI processes.

same design rules, it needs only two thirds conventional

12L circuits.

Besides, using the of the area with

The photograph

of the output

and the two non~verlapping

input signals are shown too. This divider operates up to 4 MHz. The simple design process by arranging the intermediate collect ors according to a given logic function only desi~

time, but also simplifies

saves not

restoring the logic from

KIM et al.: MULTINPUT-MULTIOUTPUT

INTEGRATED

INJECTION

LOGIC

811

REFERENCES

[1]H. H, Berger and S. K. Wiedmann, “Merged-transistor

[2]

[3]

(a)

[4]

[5] [6]

[7]

[8] (b)

logic (MTL)– A low-cost bipolar logic concept,” IEEE J. Solid-State Circuits, vol. SC-7, pp. 340-346, Oct. 1972. K. Hart and A. ,Slob, “Integrated injection logic: ~ new approach to LSI,” IEEE J. Solid-State Circuits, vol. SC-7, pp. 346-351, Ott. 1972. J. L. Saltich; W. L. George, and J. G. Soderberg, “Processing technology and AC/DC characteristics of linear compatible 12L,” IEEE J. Solid+tare C%cuits, vol. SC-I 1, pp. 478-485, Aug. 1976.

H. H. Berger and S.K. Wiedmann, “Advanced merged transistor vol. 7, pp. logic by using Schottky junctions,” Microelectron., 35-42,1976, S. C. Blackstone arid R. P. Mertens, ‘~chottky collector I* L,” IEEE J. Solid-state Circuits, VOL SC-12, pp. 270-275, June 1977. H. Lehning, “Current hogging logic (CHL)–A new bipolar logic for LSI,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 228-233, Oct. 1974. R. Miillei, ,“Current hogging injection logic (CHIL)–A new logic with liigh functional density ,“ IEEE J. Solid-State Circuits, VOL SC-10, pp. 348-352, Oct. 1975. H. E. J. Wulms,, “Base current of 12L transistors,” in ZSSC6 Dig. — Tech. I’apers, 1976, pp. 92-93.

(c) Fig. 10. (a) Photomiciograph of a master-slave flip-flop connected as a divide-by-t wo. (b) Equivalent gate circuit. (c) Waveforms of the nonoverlapping input signals (IN1, IN2) and the output signal (OUT I ). Horizontal: 0.5 ps/div; vertical: 1 V/div for the inputs and 500 mV/ div for the output.

;, the layout, Another important: hdva~tage is obviously the flexibility of metal interconnection. As can be seen in the figure,

the injector

is coritacted

at one place and the rail is

crossed ove~ by the interconnection tion without flip-flop

with

double

layer

lines for logic implementa-

any severe voltage drop. normal

12L gates would

metallization

or

The design of this MS have needed either

a immber

of

a

crossunder

diffusions. IV.

SUMMARY

A new version of 12L, the (MI)2 L, has been described, which can be fabricated with a linear-compatible technology. The improved performance, packing density, and design flexibility y are discusied with different circuit examples. Using a 6 urn thick down, a speed-power

epi and a technology product

for 35 V break-

of 0.07 pJ and minimum

gate

delays of 17 ns have been measured, A D-type frequency divider with a maximum toggle frequency of 10 MHz has been built. ACKNOWLEDGMENT The support

authors

would

and P. Zdebel,

discussions.

like

Peter K. Seegebrecht was born in Rathenow, Gelmany, on January 11, 1942. He received the Ing. grad, degree from the Ingenieurschule, Hamburg, Germany, in 1967, and the Dipl.Ing. degree in electrical engineering from the Technische Hochschule Aachen, Aachen, Germany, in 1972. Since “1972 he has been With the Institut fur Theoretische Elektrotechnik, Technische Hochschule Aachen. His research interests are in device physics, fabrication technology, and circuit design.

to thank

P. Rieger,

R. Korfer and H. Flocke

for

processing for

valuable

Walter L. Engl was born in Regensburg, Germany, on Ap~i.1 8, 1926. From-1946 t: 1949 he studied physics at the Technische HochHe received the schule, Munich, Germany. Dr. rer. nat. degree from the Technische Hochschule in 1953. From 1950 to 1963 he worked for the Wernerwerk fiir Met3technik at Siemens and Haiske AG; his last position there was as Head of the Research Laboratory. From 1961 to 1963 he lectured on Theoretische Elektrotechnik und MeS3technik at the Karlsruhe Institute of Technology. Since 1963 he has been a full Professor at the RWTH, Aachen. From 1968 to 1969 he was the Dean of the Faculty for Elektrotechnik of the RWTH. In 1967, 1970, and 1972, respectively, he was a Visiting Professdr at the University of Arizona, Tucson, at Stanford University, Stanford, CA, and at the University of Tokyo, Tokyo, Japan. His main research fields are theory and application of integrated electronics, theory of electromagnetic fields and networks, and electrical measuring techniques.