Modeling Feedback Bridging Faults With Non-Zero ... - Semantic Scholar

Modeling Feedback Bridging Faults With Non-Zero Resistance Ilia Polian1

Piet Engelke1 Michel Renovell2 Bernd Becker1 2 1 Albert-Ludwigs-University LIRMM – UMII Georges-K¨ohler-Allee 51 161 Rue Ada 79110 Freiburg im Breisgau, Germany 34392 Montpellier, France

Abstract We study the behavior of feedback bridging faults with nonzero bridge resistance. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Even loops going through a gate with controlling values on its side inputs (which we call disabled loops) expose non-trivial behavior. We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depending on the bridge resistance, making such a fault very hard to resolve. We conclude that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.

1 Introduction It is not true that only a few short defects have negligible resistance [1]. However, the attention paid to these two defect types by the testing community definitely suggests the opposite. The number of various methods for simulating nonresistive bridging faults is far too high to give an overview even close to completeness, see e. g. [2, 3, 4, 5, 6, 7]. On the other hand, there are only few publications and even less available tools dealing with resistive shorts, starting in the early 90s with [8]. The main reason for this under-representation is that, unlike for the non-resistive case, there is an unknown value to be taken into account, the resistance. This is because it can not be known in advance which particle will cause the short defect corresponding to the bridge. A bridging fault may be detected by a test vector for one resistance value, and the bridge between the same nodes may not be detected by the same vector for another resistance. This fundamentally changes the meaning of standard testing concepts, like redundancy, coverage, and so forth. In order to handle this ambiguity, Renovell et al. [9, 10, 11] introduced the concept of Analogue Detectability Interval (ADI). An ADI [R 1 ; R2 ] is defined for a given fault and a given test set. The short having the resistance R sh is detected by the test set if and only if R sh is within this interval: R1  Rsh  R2 . This concept is applicable both to bridging faults between two logic nodes and to stuck-at faults understood as shorts with power supply or ground. Sar-Dessai and Walker [12, 13] proposed a prototype

simulator and ATPG for this fault model (they used the term ‘Detectable Resistance Interval’ instead of ADI). Lee and Walker [14] presented a simulator with some speed-up techniques. Maeda and Kinoshita [15] advocate pseudoexhaustive test application at the bridge site. None of them dealt with feedback bridging faults or with sequential circuits. Mei mentions feedback bridging faults as early as 1974 [16]. Xu and Su [17] provide further theoretical insights on the testability of these faults using wired models. Abramovici and Menon [18] overcome some restrictions of earlier research and report on a gate-level simulation. Dahlgren [19] describes a switch-level simulation method. Malaiya et al. [20] study on the electrical level implications of propagation delay on feedback loop behavior. They briefly mention the possible problems caused by non-zero bridge resistance in context of non-feedback faults. Millman and Garvey [5] apply the voting model to feedback bridging faults. Chess and Larrabee [21] perform ATPG using the generalized concept of ‘primitive bridge function’. Taken together, there are several papers on resistive bridging faults as well as some literature on feedback loops, but, to the best of our knowledge, no publication considering the combination of these two concepts. The conventional wisdom for zero-resistance feedback bridges says that it is crucial whether the loop induced by the bridge is inverting (has an odd number of inverting gates) or not. In the former case, the fault will either lead to oscillation if properly sensitized (if not, no fault effect will be visible); in the latter case, there may be a fault effect or not, depending on the circuit and used fault model. In this work, we report our findings on simulating resistive feedback bridging faults. We demonstrate that all three options: detection, non-detection, and oscillation, can occur for different bridge resistance ranges for the same loop. It turns out that under certain circumstances a circuit line can oscillate, however not between V DD and ground (corresponding to logic values 0 and 1) but between some intermediate voltages. This phenomenonm (which we call the multiple strengths problem) can lead to non-trivial circuit behavior. We propose a simplified technique which allows simulation of such a circuit with reasonable computational complexity. We also suggest an indicator for accuracy lost due to the simplifications. Experimental results are reported for ISCAS benchmarks. The remainder of the paper is organized as follows. In Section 2 we introduce the fault model. We demonstrate the faulty behavior for combinational circuits in Section 3. Implications for fault simulation are discussed in Section 4. Experimental results are given in Section 5. Section 6 concludes the paper.

2 Non-Feedback Resistive Bridges An example circuit can be seen in Figure 1. The lines a and b are bridged, with a being the output of a NAND2 and b of a NOR2 gate. Let us first assume that logic 0 is applied to both inputs of the NAND gate and logic 1 is applied to both inputs of the NOR gate. In CMOS, two p transistors from the pull-up network of the gate A (connected in parallel) drive the node a, and two n transistors (also in parallel) from the pull-down network of the gate B drive the node b. Thus, in absence of the bridge there will be a 1 on a and a 0 on b. The voltages on a and b in presence of the bridge, V a and Vb respectively, depend on the bridge resistance R sh . For Rsh = 0 , there will be some intermediate voltage identical for both lines. For R sh = 1, Va will equal VDD and Vb will equal 0V, as if the bridge were not present. A possible voltage characteristic for intermediate values of R sh (those between 0 and 1) is depicted by solid curves in Figure 2. The abscissa corresponds to different values of R sh , the ordinate shows which voltages are assumed on the lines a and b if the bridge has such a resistance. With increasing Rsh , Va and Vb diverge, with V a approaching V DD and Vb approaching 0V. The question of interest in simulation is how the succeeding gates will interpret these voltages. In our example circuit, gates C and D are successors of a and gate E is successor of b. Neither the gate types of C, D and E are important in this example, nor whether they have additional inputs. Rather, it is relevant whether they interpret the voltage on their input as a logic 1 or a logic 0. In accordance to previous works [10, 12], we assume an exact-defined threshold voltage T h, which however may be different for different gate types. Note that there may be many different gate types with the same functionality, e. g. different NOR2 gates having a different threshold. Also, different inputs of the same gate may have different thresholds. Thus, we rule out that some voltage is not recognized as a logic value; any voltage above T h is interpreted as a logic 1, and any below as logic 0. Moreover, we also neglect that for different manufactured ICs, the threshold of the same gate may vary. In Figure 2, the thresholds for the gates C, D, E are shown as horizontal lines labeled by T h C , T hD and T hE , respectively. Consider the gate C. Given a resistance R sh , this gate will either interpret the value on a as 1 or as 0. Being more exact, there is a critical resistance, denoted as R C in the picture, so that for R sh < RC the value on a is interpreted as 0 and for Rsh > RC it is interpreted as 1. The intuition behind this is that for a bridge with low resistance, the value 0 on the line b has larger impact on the voltage on a than for a highlyresistive bridge. Hence, if we want to detect the bridge by propagating the faulty value through the gate C to some observable point, we may be able to do this only for the bridge C

0 A

a Rsh

B

b

Va

ThC ThD ThE

Vb R’D R C R’E R’C R E Figure 2: Rsh -V -diagram

Rsh

resistance Rsh < RC , because otherwise no fault effect will be visible on C’s input. Since for the critical resistance R C Va (RC ) = T hC holds, RC can be determined in Figure 2 by finding the intersection of the curve V a with T hC . For the gate D, the threshold T h D is below the curve. This means that for any R sh the gate D will recognize the voltage on a as logic 1 and there is no critical resistance; no fault effect can be propagated. For the gate E, the solid curve Vb is relevant, and there is a critical resistance R E . E interprets the voltage on b as faulty logic value 1 only for Rsh < RE . Now imagine that there is a logic 1 on the second input of the NAND gate. Then, only one p transistor will pull up the voltage on the line a to the power supply. This results in logic 1 being driven with less strength on a. With 0 driven on b with the same strength as before (two parallel n transistors), the voltage characteristic for V a and Vb in the Rsh -V -diagram will be described by curves situated underneath the original ones (one possibility is shown by the 0 dashed curves). This results in new critical resistances R C 0 and RE . Furthermore, there is now a critical resistance for D, 0 RD (no intersection between the V a curve and T h D existed before). The shown shift of the curves plays an important role in the multiple strengths problem discussed later on. As we have stated above, the gate C interprets the voltage on a as logic value 0 for R sh < RC and as 1 for R sh > RC . We denote this situation by the Analogue Detectability Interval (ADI) [10] [R C ; 1]1=0, which means that 1 is assumed for the values of R sh within the interval and 0 for all other values. We could also have written [0; R C ]0=1 to describe the same situation. Note that this interval is only valid for the values (0, 0, 1, 1) applied to the NAND and NOR gates; 0 for (0, 1, 1, 1), the interval would have been [R C ; 1]1=0. This interval can be propagated through the gate C and the following gates to the primary outputs or other observable points using rules described, e. g., in [14]. We are interested in propagating the (faulty) effect from the bridge location, so our point of interest is whether the succeeding gates like C, D, E will recognize the faulty value as such or not. In the remainder of the paper, we concentrate on feedback bridging faults, i. e. ones which induce a (structural) loop in the circuit.

3 Analysis of Feedback Bridges

0 (1) 1

V

D E

1

Figure 1: Example circuit

According to Mei [16], “A feedback bridging fault is a bridging fault such that both involved leads lie on the same path in the circuit”. The bridged line with lower topological ordering is sometimes called back line [18], while the other line involved in the bridge is called front line. Beyond this

R sh

c_in 0

C 1

c

b_in

0 a

A

B

Y

b

1

D

0 d

To primary outputs

X

0

Figure 3: Inverting feedback fault RD (1)

R sh

a d

(1)

b 1st excitation a d b 2nd excitation a d b 3rd excitation simulation progress

a

11111 00000 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 11111 00000 11111 00000 00000 11111 00000 11111 11111 00000 11111 00000 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 11111 00000 00000 11111 00000 11111 11111 00000

faulty value

(1)

(1)

corresponds to 1st excitation

1 0 0oscillation 1

# of active

(n) transistors

Figure 4: Oscillation (c in = b in = 1) structural definition, some authors distinguish whether the loop is sensitized or not. Dahlgren [19] calls sensitized loops with an odd number of inversions such that a faulty effect is introduced at the back wire active feedbacks. Favalli and Dalpasso [22] refer to sensitized loops as logically closed loops and to their non-sensitized counterparts as logically opened loops. To emphasize the specifics of non-sensitized loops caused by resistive short defects, we call them disabled loops.

3.1 Oscillation In Figure 3, the resistive bridge induces an inverting loop. We consider the case c in = 1 first, so the OR gate C has a controlling 1 at one of its inputs. Further good simulation values are shown at the corresponding lines. Figure 4 shows the situation for the non-controlling value 1 on b in, i. e. we have a sensitized loop via gates D and B. The diagram depicts the development for all R sh values simultaneously, with R sh shown on the abscissa. The simulation is done in topological order of the gates, starting with the back line a. The simulation progress is shown from top

to bottom. Since there is now a cycle in the circuit, some lines are visited more than once. Note that this diagram (and the following one) looks confusingly similar to waveform diagrams featuring the simulation time on the abscissa. It is crucial to understand that R sh is on abscissa, instead, and for an actual circuit with a fixed R sh , the voltages on the lines are obtained by reading the diagram from top to bottom at a fixed abscissa value for R sh . As noted above b in and c in have logic 1 value. The first simulation pass results in a = 0, c = 1, d = 0 and b = 1, where only one p transistor actually connects b to the power supply (while two n transistors in gate A pull line a to ground). The number of active transistors in gate B is given in parentheses below the curve. With a = 0 and b = 1, the bridge is excited; the line a assumes some voltage V a (Rsh ) larger than its voltage in absence of the bridge, 0V. Note that V a (Rsh ) is larger for smaller values of R sh . The row of the diagram just below the mark “1st excitation” shows one possibility for the voltage Va (Rsh ) on the line a. Note the similarity to the bottom curve in Figure 2. Also similarly, the gate D will interpret this voltage Va (Rsh ) as 1 or 0, depending on R sh . We denote the critical resistance of the gate D as R D (1), where 1 indicates that one transistor drives the 1 on the line b (see above). Consider Rsh > RD (1). Then, Va (Rsh ) is less than D’s input threshold. Consequently, D will interpret the value as logic 0, so there will be a logic 0 on the line d and a logic 1 on b. Again, the bridge is excited, and the gate D interprets the voltage on the line a as 0 (because R sh > RD (1) holds). Hence, the signal assignment is stable for R sh > RD (1). Now, regard R sh < RD (1), so that Va (Rsh ) exceeds D’s threshold. The line d will then assume logic 1, and there will be a logic 0 on b. Thus, the bridge is not excited anymore, the voltage on a returns to 0, d becomes 0, b becomes 1, and the bridge is excited again. Since R sh < RD (1), the voltage on a is interpreted as logic 1 by the gate D, again, and the whole process repeats. Thus, both lines d and b oscillate between 1 and 0, and the line a oscillates between 0V and some intermediate voltage V a (Rsh ). The oscillation typically takes place at a frequency much higher than the IC’s clock frequency; the lines will have multiple values on them during the same clock cycle. The oscillation may be propagated to an observable point. However, whether the test equipment will detect the fault or not is random since it depends on the exact strobe time of the tester. It is an interesting question if and how the oscillation contributes to the fault coverage; in this paper we just note that oscillation is a kind of effect which is different both from a faulty and a good value on a line. Thus, we are interested both in resistance ranges for which the fault is detected and ranges for which oscillation takes place. For the considered situation, we conclude that for R sh < RD (1), there is oscillation, and for R sh > RD (1), no fault effect is visible. This matches with conventional wisdom about (non-resistive) inverting loops: there is oscillation, unless Rsh is too high for a fault effect to be observable. It is possible to use an interval notation also for oscillation, like [0; RD (1)]OSC . In the diagram, we mark the R sh ranges for the lines on which oscillation takes place by a dashed pattern.

RD (1)

RD (2)

R sh a d b

(2)

1st excitation a d b 2nd excitation a d b 3rd excitation a d b 4th excitation

simulation progress

a

111 000 000 111 000 111 (1) (1) 000 111 000 111 000 111 000 111 111 000 111 000 000 111 000 111 000 111 000 111 (2) (1) 000 111 00 11 000 111 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 (1) (1) 11 00 11 00 11 00 11 00 11 00 11

(2)

(2)

(2)

corresponds to 2nd excitation

Figure 5: Multiple Strengths Problem (c in = 1, b in = 0)

3.2 Multiple Strengths Problem Now, let us assume the (controlling) value 0 is at b in (while c in remains at 1). Hence, we have a disabled loop as defined in the beginning of this section. With 1 at c and 0 at d, there is the logic value 1 at b, driven by two p transistors. The further development can be seen in Figure 5. In addition to the number in parentheses, solid curves indicate lines driven by one transistor and dashed curves are used for lines driven by two transistors. The bridge is activated, and the voltage V a1 (Rsh ) on line a forms a curve (1 in V a1 indicates first excitation). With RD (1) (RD (2)) denoting the critical resistance of the input of the gate D when b is driven by one (two) transistors, there are three cases to be distinguished: Case 1: Rsh < RD (1). After the first excitation, the line d has logic value 1. Hence, b in is the sole input of the gate B having logical value of 0. So, only one p transistor connects the output b of gate B to V DD (indicated by “(1)”). Therefore, the second excitation of the bridge differs from

the initial one: two n transistors (in gate A) still connect line a to ground, but now one single p transistor pulls line b to VDD . Thus, the resulting voltage on line a is below the one recorded at the first excitation. We denote this characteristic as Va2 (Rsh ). The line d assumes logic 1, so the third excitation is identical to the second one. This means that there is a stable faulty value on line d (which can be propagated to an observable point via gate X). There is no oscillation in this range. Case 2: RD (1) < Rsh < RD (2). Up to the second excitation, the simulation progress is identical to Case 1. In particular, line b is still driven by one p transistor. However, since Rsh is now larger than R D (1), gate D will interpret the voltage on its input a as logic 0. Hence, line d is pulled to logic 0 and two inputs of gate B assume the logical value of 0. Consequently, logic 1 at b is driven by two transistors, again. Therefore, the third excitation is equal to the first one. This process is iterated endlessly. V a1 corresponds to Va3 , Va5 , and so on, while V a2 is the same as Va4 , Va6 et cetera. Thus, there is an oscillation on line a between some intermediate voltages. According to our assumptions, line d oscillates between logic 0 and logic 1. In particular, we assumed that there is a unique threshold such that all voltages above (below) this value are interpreted as logic 1 (0). In reality, this means that the gain of gate D’s input is sufficiently high to result in clear logic values at line d. Case 3: RD (2) < Rsh . Here, no fault effect of any kind emerges. In summary, depending on R sh , a faulty effect or oscillation may occur on d (and thus be potentially propagated via X), although, if only Boolean logic values are considered, the loop is disabled.

4 Implications for Fault Simulation There is no doubt that it is possible to build a simulator which can accurately resolve the multiple strengths problem, deal with intervals originating from the memory elements and even treat the combination of both problems. To do so, it could just reiterate what we are doing in our diagrams. Simulating the loop over and over again, sooner or later one of the earlier value assignments would repeat 1 . Then, all the intervals can be checked for whether opposite values are assumed (then, there is oscillation) or, if not, whether the value is good or faulty. On the other hand, the computational complexity of such an approach would be tremendous. We demonstrated that even for small examples it may be necessary to simulate the loop many times before an accurate decision can be made. Note that in realistic circuits, loops may consist of a considerable number of gates. In sequential circuits, additionally, many different critical resistances would accumulate with simulation progress, making the simulation of late time frames even more time consuming. One possible solution for the performance problem is to adopt the following, simplified approach: given a bridging fault, determine the critical resistance of any gate under any 1 This is because there are finitely many critical resistances in the circuit, and thus finitely many intervals, in each of which one of three values (good, faulty or oscillating) can be assumed.

possible circumstances. Of all these critical resistances, select the minimal and the maximal one, R min and Rmax . Now, consider three intervals: [0; R min], [Rmin ; Rmax ] and [Rmax ; 1]. The behavior in the third interval corresponds to the good simulation; no faulty values are interpreted as such by any gates. In the first interval, the circuit behaves as if the bridge resistance were 0 ; it is not too hard to determine its behavior. The simulation has been accurate so far. In order to reduce the computational complexity, we assume that in interval [Rmin ; Rmax ] oscillation takes place. This suggests that the fault effect, if propagated to an observable point, may be visible or not. By doing so, maximally two intervals have to be dealt with: the interval [0; R min] in which faulty value may be assumed or oscillation may take place, and [Rmin ; Rmax ] (the last interval, [Rmax ; 1], is guaranteed to expose no faulty behavior). Note that these values are independent of the propagation path, thus the technique can handle multiple loops induced by a single fault. The concept of fault coverage has been adapted to resistive bridging faults in [10, 14] as the detection probability of a fault by a given test set. Let [R 1 ; R2 ] be the ADI for a resistive bridging fault f . According to [14], the fault coverage for this fault is given as

F C (f ) = 100%


Z R2 R1

! Z Rmax

(r)dr =

0

!

(r)dr ;

(1)

where (r) is the probability density function of the short resistance r. For more than one fault, average F C is taken as fault coverage. A feedback bridging fault may result in oscillation visible at the circuit’s output(s). It depends on the used automatic test equipment (ATE) whether or not this faulty effect is recognized as such. In order to account for this, let [R 3 ; R4 ] be the bridge resistance interval, in which either a faulty value or oscillation occurs. We denote as F C OSC the fault coverage with respect to such an interval (it is defined in the same way as in Eq. (1), except that R 3 and R4 replace R1 and R2 ). Note that [R1 ; R2 ] is contained in [R3 ; R4 ]. F COSC is equal to F C if no oscillation occurs and is larger than F C otherwise. The “real” fault coverage lies somewhere between F C and F COSC , depending on how good the test equipment recognizes oscillation. For instance, if the ATE is known to recognize oscillation in k % of the cases, the “real” fault coverage can be defined as (1 k=100)
F C +(k=100)
F C OSC . The larger the difference between F C and F C OSC is, the more important it is to understand the ATE behavior exactly. In order to assess the impact of the proposed simplification on the accuracy of simulation results, we introduce an indicator called Accuracy Loss Ratio (ALR), defined as:

ALR =

Z Rmax 0

!

(r) dr =

Z Rmin 0

(r) dr

!

(2)

(averaged over all considered faults). ALR indicates the contribution of the interval [R min ; Rmax ] (in which our simplified technique assumes oscillation) to the fault coverage (Eq. (1)). By taking  into account, the number ALR is an indicator for the relevance of the interval [R min ; Rmax ]. ALR = 1:0 means that our approach produces accurate results. With increasing ALR, the exactness of the proposed method deteriorates.

Circ #F c0095 16 c0432 5909 c0499 4912 c0880 9094 c1355 10000 c1908 10000 c2670 10000 c3540 10000 c5315 10000 c6288 10000 c7552 10000 s00027 25 s00208 663 s00298 558 s00349 1824 s00382 1251 s00386 1442 s00400 1310 s00420 2575 s00444 1691 s00510 1850 s00526 1198 s00641 10000 s00713 10000 s00820 1586 s00832 1592 s00838 9999 s00953 6764 s01238 10000 s01423 10000 s01488 8998 s01494 8968 s05378 10000 s09234 10000 s1196 9932 s1269 10000 s13207 10000 s1512 10000 s15850 10000 s3271 10000 s3330 10000 s3384 10000 s344 1809 s35932 10000 s38417 10000 s38584 10000 s4863 10000 s499 2662 s635 10000 s6669 10000 s938 9999 Average

ALR

1.66 1.34 1.22 1.34 1.20 1.22 1.08 1.17 1.12 1.24 1.13 1.37 1.26 1.34 1.27 1.29 1.00 1.31 1.25 1.35 1.51 1.30 1.01 1.05 1.33 1.33 1.24 1.43 1.25 1.20 1.00 1.00 1.22 1.08 1.23 1.23 1.05 1.21 1.07 1.28 1.01 1.01 1.27 1.13 1.18 1.09 1.00 1.50 1.21 1.00 1.24

FC

91.71 97.25 98.12 94.25 96.27 97.46 89.47 94.16 97.27 91.40 95.83 78.24 78.28 67.75 87.74 13.18 82.14 13.27 53.08 15.03 79.02 18.50 92.84 91.53 73.83 73.57 40.16 88.20 88.56 46.98 83.79 83.45 70.16 37.02 88.13 95.21 43.32 60.52 62.16 93.16 79.86 93.29 87.85 61.71 12.60 65.19 96.98 84.37 0.00 99.51 40.22 71.84

FCOSC

100.00 98.98 99.94 98.42 99.19 99.35 95.39 99.17 99.57 98.01 98.24 100.00 96.66 86.63 97.25 19.26 87.43 19.43 62.12 22.93 99.57 29.57 94.27 93.30 84.88 84.95 44.99 96.44 91.90 49.75 89.69 89.54 76.63 40.28 91.60 99.20 47.06 67.40 66.77 97.05 82.09 94.66 97.22 76.69 14.14 70.28 98.52 98.00 0.05 99.92 45.04 78.22

ratio 1.09 1.02 1.02 1.04 1.03 1.02 1.07 1.05 1.02 1.07 1.03 1.28 1.23 1.28 1.11 1.46 1.06 1.46 1.17 1.53 1.26 1.60 1.02 1.02 1.15 1.15 1.12 1.09 1.04 1.06 1.07 1.07 1.09 1.09 1.04 1.04 1.09 1.11 1.07 1.04 1.03 1.01 1.11 1.24 1.12 1.08 1.02 1.16 – 1.00 1.12

time [s] 0.68 202.48 454.55 791.67 754.42 804.62 842.42 779.23 958.94 2658.29 1554.24 1.22 108.17 46.26 309.35 160.14 296.43 167.26 562.18 239.67 3412.41 122.90 736.55 1253.66 753.22 668.50 2293.44 7703.29 665.89 1029.01 3230.85 3249.51 1389.25 3586.12 313.26 5534.53 6787.58 1359.82 3796.18 2938.13 1291.48 2864.23 352.96 2162.16 8289.10 58566.26 3348.22 3641.79 501.44 3093.41 1326.51

Table 1: Experimental results

5 Experimental Results In order to evaluate the approximate simulation model from Section 4, we implemented it in an event-driven resistive bridging fault simulator. 2 The results of simulating ISCAS 85 and 89 benchmark circuits with 1,000 random test patterns can be found in Table 1. The circuit name is followed 2 Further results (not reported here) based on different fault coverage definitions are available for non-feedback faults.

by the number of simulated faults #F. We did not consider faults with primary ports involved as well as ones where the input and the output of the same gate were shorted. If there were more than 10,000 of such faults, we selected 10,000 randomly 3. In the third column, the value of ALR is given. The next columns contain the fault coverage without considering oscillation as detection (F C ), its counterpart including oscillation F COSC and the ratio of these numbers. We used the definition of (r) from [14] (which is based on results from [1]) for determining ALR and the fault coverages. The run time of the simulator in CPU seconds concludes the table. We performed all experiments on a 2GHz Linux machine with 1 GB RAM. The value of ALR assumes values between 1.00 and 1.66. For circuits like s00386, s01488, s01494 and s6669, the simplified simulation technique is able to produce exact results. There are also circuits like c0095, for which a more exact method may be considered. If the ATE is capable of recognizing oscillation as a faulty effect, it is adequate to use F C OSC as the quality measure for a test set. In case the ATE never identifies oscillation, F C should be utilized for this purpose. While this ratio is somewhat related to ALR, they focus on different aspects: ALR helps to decide whether it is appropriate to employ the proposed simplification (no assumption on ATE is done). F COSC =F C describes the influence of oscillation on the results. It is defined for the simplified approach as well as for the exact method. In summary, ALR corresponds to the exactness of our method, while the ratio F C OSC =F C describes the uncertainty of recognizing oscillation by the ATE. The ratio F COSC =F C (given in the sixth column of Table 1) ranges from 1.00 to 1.60. Note that low (high) values of this ratio tend to coincide with low (high) values of ALR. However, there is no stringent correspondence between these two measures. The reason for this is that oscillation may also occur in the lowest bridge resistance range [0; R min ]. This range is simulated exactly in our simplified approach and is hence not accounted for when calculating ALR.

6 Conclusions Resistive bridging faults reflect realistic defect behavior much better than their zero-resistance counterparts do. Unfortunately, the complexity of simulating them is tremendous, mainly due to the presence of a parameter not known ex ante, the resistance. In this work, we considered resistive feedback faults, a fault class on which no existing literature is known to us. Logic values on the circuit’s lines were studied depending on the bridge resistance, R sh . We found that good or faulty values are assumed or oscillation takes place in different R sh ranges. Further analysis (which could not be included in this paper) reveals that these ranges can even be non-contiguous. We furthermore demonstrated that disabled loops, normally not regarded as something worth detailed consideration, may expose non-trivial behavior under the resistive bridging fault model leading to situations hard to resolve, compared to the zero-resistance case. 3 In an industrial setting, the fault list might be generated using layout information, e. g. by means of Inductive Fault Analysis [3].

Our conclusion was that these faults can undoubtedly be accurately simulated, but the computational complexity would probably be prohibitive. Hence, we suggested a simplified technique giving up accuracy for speed and presented experimental results for ISCAS benchmarks. We introduced the Accuracy Loss Ratio as an indicator for influence of the simplification on the exactness of simulation results. It turned out that for some circuits, the accuracy loss is reasonable. For those few circuits with overly high values of ALR, exact simulation methods should be employed, which will be a focus of future research.

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