Multi-bit Sigma-Delta TDC Architecture for Digital Signal Timing ...

Multi-bit Sigma-Delta TDC Architecture for Digital Signal Timing Measurement Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi† , Tatsuji Matsuura, Kiichi Niitsu, Fumitaka Abe, Daiki Hirabayashi ∗

Dept. of Electronic Engineering, Gunma University, Kiryu Gunma 376-8515 Japan, email: k [email protected] † Semiconductor Technology Academic Research Center (STARC), Yokohama 222-0033 Japan

Abstract— This paper describes the architecture (circuit design) and principles of operation of sigma-delta (ΣΔ) time-todigital converters (TDC) for high-speed I/O interface circuit test applications; they offer good accuracy with short test times. In particular, we describe multi-bit ΣΔ TDC architectures for fast testing. However, mismatches among delay cells in delay lines degrade the linearity there. Then we propose two methods to improve the overall TDC linearity: a data-weighted averaging algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our MATLAB and Spectre simulation results demonstrate the effectiveness of these approaches. Keywords: Time-to-Digital Converter, Time Measurement, Sigma-Delta Modulation, Multi-bit, High-Speed I/O Interface Circuit Testing

I. I NTRODUCTION High-speed I/O interfacing circuits such as for double-datarate (DDR) memory interfaces are very important, and lowcost, high-quality testing of such circuits is challenging [1]. This paper describes simple test circuitry for measuring digital signal timing with high resolution and good accuracy. We focus on Time-to-Digital Converter (TDC) applications of sigma-delta modulators (for fine-timing-resolution, digital output, and simple circuitry) and with multi-bit architecture (for short testing time). Multi-bit ΣΔ TDC can suffer from delay mismatches among delay cells, but we propose two techniques to solve this problem and maintain good accuracy: data-weighted-averaging (DWA) and self-calibration. We describe the principles of ΣΔ TDC in Section II, and report the architecture for mismatch delay cell of DWA and calibration in multi-bit ΣΔ TDCs in Section III, and IV. We present simple circuit designs in Section V, and conclusion in Section VI. II. S IGMA -D ELTA TDC A. Flash TDC and Sigma-Delta TDC TDC can be used to measure digital signal timing. The architecture of a basic flash-type TDC is shown in Fig.1 [2]. It consists of a delay-line using delay cells in the signal path and an array of flip-flops. The input Start signal passes along the delay cells, which are connected in series. And then each signal is connected to a D input terminal in the D flip-flop

array. Start signal is delayed only by an integral multiple of the buffer delay τ . The state of each D flip-flop is latched by the rising edge of the Stop signal. This circuit converts the time delay between the signals to a certain number of steps of buffer delay. That is, the output from the D flipflop is obtained as a thermometer code (unary code) output showing the time delay between Start signal and Stop signal, and this time delay is obtained as a digital output Dout using a thermometer-code-to-binary encoder. The flash-type TDC has the advantage of being able to measure a single-event input, however its disadvantages are that the time resolution is determined by the delay value τ , and its circuitry is large. We consider here how to measure the time delay between two repetitive digital signals (or clocks), and we use a ΣΔ TDC for the measurement. Although arbitrary digital timing signals cannot be measured with the ΣΔ TDC, it can measure the timing of two clocks where time resolution is inversely proportional to measurement time. The longer the measurement time, the finer the time resolution. We consider here the use of a multi-bit architecture for short testing time, and the use of DWA or self-calibration of the delay cell elements for good accuracy. Note that the ΣΔ TDCs have been studied recently [3], [4], [5], [6] mainly for all-digital PLL circuits. In this research, we consider to use them for digital signal timing measurement and testing. B. Single-bit Sigma-Delta TDC Fig.2 shows a single-bit ΣΔ TDC architecture for our Matlab simulation. It consists of a delay element, three multiplexers, an analog integrator, and a comparator. Its inputs are two clock signals CLK1 and CLK2 with the same frequency, and it measures the time difference T of their clock timing edges. In this design, the TDC output as the time difference is positive when the CLK1 rising edge is earlier than CLK2 and it is negative when the CLK1 edge is later. The number of 1’s of the comparator output for a given time is proportional to the time difference between CLK1 and CLK2 when CLK1 is earlier. Similarly the number of 0’s is proportional to their time difference when CLK2 is earlier. Its operation is as follows:

1) When the comparator output is “1”, CLK1 is delayed by τ while CLK2 is not delayed. When the comparator output is “0”, CLK1 is not delayed, while CLK2 is delayed by τ . 2) The clock signals acquired as the result are defined as CLK1a and CLK2a, respectively. 3) Mask signal (generated in ”Timing Generator”) is the same as CLK1a when CLK1a comes earlier than CLK2a; otherwise it is the same as CLK2a. 4) CLK1a is logical AND of Mask signal and CLK1b, while CLK2a is logical AND of Mask signal and CLK2b. 5) We produce the time delay signal CLKin between CLK1b and CLK2b and convert it to the voltage signal by feeding it to the integrator whose output is IN Tout . 6) The comparator examines whether the integrator output IN Tout is larger than ”0” or not. Its output Dout is that of the ΣΔ TDC and feedback to the multiplexers. Fig.3 shows timing diagram of the signals. C. Multi-bit Sigma-Delta TDC Next we describe the multi-bit ΣΔ TDC, and Fig.4 shows its architecture. In the case of the multi-bit ΣΔ TDC, a flashtype A/D converter (precisely, an array of comparators) is used instead of a single comparator, and its digital output is in a thermometer code (unary code) format. The same number of delay elements as that of the comparators are used: in case of an N-bit ΣΔ TDC, 2N − 1 comparators and delay elements are used. Since the integrator output IN Tout is digitized with an array of comparators (a flash ADC without an encoder), its output Dout is in a thermometer code format. Then the digital output in a thermometer code is fed into select signals of an array of multiplexers. Note that the integrator output IN Tout is digitized with fine voltage resolution with an array of comparators, and hence the multi-bit ΣΔ TDC can obtain fine time resolution compared to the single-bit one for a given measurement time. (Fig.5 shows the simulation results which support this statement.) In other words, the multi-bit ΣΔ TDC takes shorter measurement time for a given time resolution than the single-bit one, which means lower testing cost. However, the multi-bit ΣΔ TDC may suffer from mismatches among delay units, which degrades the TDC linearity (which is similar to the multi-bit ΣΔ ADC [7]). III. M ULTI - BIT S IGMA -D ELTA TDC

WITH

DWA

This section shows our proposal of applying the DWA algorithm to the multi-bit ΣΔ TDC for its linearity improvement. The boxed area in Fig.4 shows a digital-to-time converter (DTC) in a ΣΔ TDC, and the comparators outputs are feedback and select the corresponding delay cells in the DTC. There is delay value variation among delay cells in actual circuits, and it causes the nonlinearity error of the overall TDC. Then, we propose to apply the DWA algorithm to the multibit ΣΔ TDC. Fig.6 shows a block diagram and operation of

the DWA logic. It performs the right rotation shift of the ΣΔ TDC comparators outputs in a thermometer code as follows: 1) The first input starts at S1 . 2) Next input starts at the position of S2 shifted by 1 (the previous input) from the previous position S1 . 3) Next input starts at S5 that shifted by 3 (the previous input) from the previous position S2 . This is the ΣΔ operation, and suppresses errors (caused by the delay cell mismatches) in DC component and pushes it in the high frequency side. (Fig.7). Fig.8 shows a block diagram of the multi-bit ΣΔ TDC with DWA logic. The outputs of the comparator array are fed into DWA logic and their outputs are given to the multiplexers as select signals in the DTC. We have performed Matlab simulation for a 3-bit ΣΔ TDC with DWA logic. Simulation conditions are given in Table I. The time difference between input clocks used for the simulation is from -0.9ns to 0.9ns. Figs.9 (a) and (b) show the difference between an ideal line and the simulated result (i.e., the integral non-linearity: INL). Fig.9 (a) is the result in case that the number of comparison times (number of samplings) is 99, and Fig.9 (b) is when it is 599. We see that the INL is large without DWA, however when DWA is employed, it is small and the TDC linearity is improved. IV. M ULTI - BIT S IGMA -D ELTA TDC S ELF -C ALIBRATION

WITH

We describe here a self-calibration technique to improve the linearity of the multi-bit ΣΔ TDC, utilizing the fact that the input signals are ”time” instead of ”voltage”. Our calibration consists of two steps: 1) Self-measurement of delay values of each delay cell is carried out with a ring oscillator configuration (Fig.10). 2) We improve the TDC linearity using the measured delay values output calculation (Fig.11). In Fig.11, the vertical axis Aout indicates the rising timing edge difference between the input clocks, and the horizontal axis Dout shows a digital output of the ΣΔ TDC, and the error from the ideal value is caused by mismatches of the delay cells. We propose here to adjust the Dout values (based on the measured cell delays) using fraction as well as integer with the following DSP so that Dout and Aout are linear. The following is the measuring method of the cell delays: 1) We add an inverter to have a ring oscillator configuration with each delay cell (Fig.10). 2) We also add a binary counter whose clock is the ring oscillator output and which is in the “enable” state when the reference clock CLKref is high. Each cell delay value can be measured digitally using the ring oscillator, the counter and the reference clock. We assume here that the time duration is Tref when the reference clock is high, and the number of the ring oscillator output pulses during Tref k is Mk . Then the ring oscillator frequency fosc is approximated

by k fosc

Mk ≈ . Tref

(1)

k is larger, this approximation becomes more acAs Tref fosc curate. Let τ  is the delay time of the added inverter plus the multiplexers, and τ1 is the measured delay of cell 1. Then we have the following: 1 fosc =

1 . 2(τ  + τ1 )

(2)

Similarly we have the following for cell k: k = fosc

1 2(τ  + τk )

for k = 1, 2, .., 2N − 1.

(3)

We also measure the ring oscillator frequency with the inverter and multiplexers and without the cell delay. 1 . (4) 2τ  Then we can obtain the delay value τk of each cell based on the above equations: 0 fosc =

τk =

1 1 1 Tref 1 1 − ). ( − )≈ ( 2 fk f0 2 Mk M0

(5)

These measurements/calculations are performed in digital domain, and the measured delay values τk are stored in memory. During measurement of the time difference between clocks with the multi-bit ΣΔ TDC, we carry out digital postcalculation from the TDC output. When Dout (n) = m, then correct we use the following corrected output Dout (n) for the post processing: correct Dout (n)

m  1 1 = (2 − 1) ( − )/A. Mk M0 N

(6)

k=1

Here A=

N 2 −1

k=1

(

1 1 − ). Mk M0

(7)

correct (n) is a Note that Dout (n)(= m) is an integer, but Dout real number (integer + fraction). With the P comparison times (sampling times), we have the following time measurement output:

Tmeasure =

P Tref · A  correct correct (n)). (D (n) − Dout 2P (2N − 1) n=1 out (8)

Here correct (n) Dout

N

= (2 − 1)

N 2 −1

(

k=m+1

1 1 − )/A. Mk M0

(9)

Fig.12 shows the whole TDC circuit with the proposed selfcalibration scheme. Next we show the simulation results of the 3-bit ΣΔ TDC with self-calibration method. We assume that each delay value is known by self-measurement, and the post-calculation is performed. Simulation conditions are given in Table I.

Figs.13 (a) and (b) show the INL with and without the selfcalibration. Fig.13 (a) shows the result in case that the number of comparison times is 99, while Fig.13 (b) is the case that it is 599. We see that our self-calibration improves the linearity. We close this section by remarking that the similar selfcalibration technique is used in ΣΔ ADC [8], [9], where the nonlinearity measurement of the multi-bit DAC inside the ΣΔ ADC modulator is difficult. However, in case of TDC, the nonlinearity self-measurement of the multi-bit DTC is relatively easy using the ring oscillation configuration. This is because the input signal of TDC is ”time” while that of ADC is ”voltage”. V. C IRCUIT D ESIGN We have designed our ΣΔ TDCs with TSMC 180nm CMOS process parameters. Fig.14 shows the circuit design of a single-bit sigma-delta TDC, which is composed of a delay selection circuit, a phasefrequency detector (PFD), a charge pump, and a comparator. • The delay selection circuit consists of a multiplexer, and two delay cells τ with cascaded inverters. • The PFD consists of two D flip-flops with reset and NAND circuit. If the reset signal is 0, then it forces the DFF outputs to be 0. This circuit outputs the phase difference between CLK1a and CLK2a. There are two outputs V up and V down. V up is 1 when CLK1a is 1 and CLK2a is 0, while V down is 1 when CLK1a is 0 and CLK2a is 1. • We have designed a charge pump using op amps for stable operation. V up and V down control appropriate switches. We use a pseudo-differential structure and the outputs are V out+ and V out−. • The comparator examines which is bigger, V out+ or V out− at the clock rising edge timing. Output of the comparator is connected to the multiplexer in the delay selection circuit. Fig.15 shows the circuit design of a multi-bit ΣΔ TDC. We use an array of comparators (a flash ADC without an encoder) whose outputs are connected to the selection signals of the multiplexers. Fig.16 shows a block diagram of DWA logic. The encoder converts the comparator outputs in a thermometer code into 3-bit binary signal (B2, B1, B0). We have two registers: one is to hold the 3-bit signals and delay them by 1 clock, and its outputs are (Da2, Da1, Da0). The other is for the output of 3-bit adder, and its outputs are (Db2, Db1, Db0). The output of 3-bit adder adds the output of two registers and its outputs are (Ds2, Ds1, Ds0). We have checked the operation of this circuit and verified that the DWA logic works correctly. We have combined all the circuits and checked that the overall circuit works correctly with Spectre simulation. VI. C ONCLUSIONS We have described multi-bit ΣΔ TDC architectures for fast and high accuracy testing of the timing between two clocks. We have proposed two techniques to reduce the effects of

delay mismatches among delay cells: one is a DWA algorithm, and the other is self-calibration for the delay cells. Our selfcalibration can be done easily since the signal is “time” rather than “voltage”. We have performed system design, circuit design as well as Matlab and Spectre simulation, which validate the effectiveness of our proposed approach. Our simulation results show that the correction techniques of DWA and selfcalibration can improve linearity to near the ideal state. Our proposed circuits are simple but enable fast and accurate testing, and hence we expect to use them as DFT, BIST or BOST for clock timing measurement and testing.

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ACKNOWLEDGMENT

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We acknowledge Y. Yano, T. Gake, N. Takai, T. J. Yamaguchi, K. Wilkinson and STARC.

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R EFERENCES

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[1] J. Moreira, H. Werkmann, An Engineer’s Guide to Automated Testing of High-Speed Interfaces, Artech House (2010). [2] S. Ito, S. Nishimura, H. Kobayashi, S. Uemori, Y. Tan, N. Takai, T. J. Yamaguchi, K. Niitsu, “Stochastic TDC Architecture with SelfCalibration”, IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia (Dec. 2010). [3] D.-W. Jee, Y.-H. Seo, H.-J. Park, J.-Y. Sim, “A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC”, IEEE VLSI Circuit Symp., Kyoto (June 2011). [4] B. Young, K. Sunwoo, A. Elshazly, P. K. Hanumolu, “A 2.4ps Resolution 2.1mW Second-Order Noise-Shaped Time-to-Digital Converter with 3.2ns Range in 1MHz Bandwidth”, IEEE Custom Integrated Circuits, San Jose (Sept. 2010). [5] Y. Cao, P. Leroux, W. D. Cock, M. Steyaert, “A 1.7mW 11b 1-1-1 MASH ΔΣ Time-to-Digital Converter”, IEEE ISSCC, San Francisco (Feb. 2011). [6] W. Yin, R. Inti, P. K. Hanumolu, “A 1.6mW 1.6ps-rms-Jitter 2.5GHz Digital PLL with 0.7-to-3.5GHz Frequency Range in 90nm CMOS”, IEEE Custom Integrated Circuits Conference, San Jose (Sept. 2010). [7] R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters, IEEE Press (2005). [8] J. Silva, X. Wang, P.Kiss, U. Moon, G. C. Temes, “Digital Techniques for Improved ΔΣ Data Conversion”, IEEE Custom Integrated Circuits Conference, San Jose (Sept. 2002). [9] J. G. Kauffman, P. Witte, J. Becker, M. Ortmanns, “An 8mW 50MS/s CT ΔΣ Modulator with 81dB SFDR and Digital Background DAC Linearization”, IEEE ISSCC, San Francisco (Feb. 2011).

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PARAMETERS OF DELAY VALUES FOR SIMULATION

Delay values(Ideal) Delay values(Actual) Delay values(Ideal) Delay values(Actual)

τ1 0.145 0.140 τ5 0.145 0.145

τ2 0.145 0.149 τ6 0.145 0.148

τ3 0.145 0.148 τ7 0.145 0.146

τ4 0.145 0.143 Total of τ 1.015 1.019

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4

Fig. 11.

5

D

㺦

INT

out

Flash ADC

D D D D

…

bit out(2 -1)

out4 out3

3

out2 out1

3.13

4

5

3.95

5.02

out

Proposed error correction scheme.

CLKref

External circuit

Ǽ

’

Ǽ

+ǍǼ1

Ǽ

M U X

M U X

Counter M U X

+ǍǼ2

M U X

࡮࡮࡮ M U X

࡮࡮࡮

Ǽ

ь

PD

+ǍǼ7

Flash ADC

DSP

M U X

CLK1

τ

CLK2

τ

7

3-bit ǍǛ TDC

Fig. 12.

Memory

M U X

M U X

τ τ

M U X

M U X

τ τ

M U X

TDC circuit with self-calibration.

7 R

R

䏛䎃䎔䎓䎐䎔䎕

B

2

R

With Self-Calibration

4䎗

6

R

Without Self-Calibration

6䎙

Vout-

Dout

7

IC

8䎛

M U X

(a) Vout+ From Integrator

]s p[ en lil ae di m or f ec ne re ffi D

Vout+

M U X

Flash ADC

M U X

M U X

PD + Integrator

M U X

2䎕

R

R

1

Do7

MUX7

Do6

MUX6

Do2

MUX2

Do1

MUX1

0䎓

IC From VoutIntegrator

-2䎐䎕 -4䎐䎗

(b)

-6䎐䎙 -8䎐䎛䎐䎔 -1

䎐䎓䎑䎛 -0.8

䎐䎓䎑䎙 -0.6

䎐䎓䎑䎗 -0.4

䎐䎓䎑䎕 -0.2

䎓 0.0

T[s]

䎓䎑䎕 0.2

䎓䎑䎗 0.4

䎓䎑䎙 0.6

䎓䎑䎛 䎔 0.8 䏛䎃䎔䎓䎐䎜1

Fig. 15. Circuit design of a multi-bit ΣΔ TDC. (a) The whole circuit. (b) Flash ADC part.

(a) In case 99 times.

]s [p en il la ed i m or f ec ne re fif D

8䎛

䏛䎃䎔䎓䎐䎔䎕

B

Without Self-Calibration

6䎙

With Self-Calibration

4䎗 2䎕 0䎓

-2䎐䎕 -4䎐䎗 -6䎐䎙 -8䎐䎛䎐䎔 -1

䎐䎓䎑䎛 -0.8

䎐䎓䎑䎙 -0.6

䎐䎓䎑䎗 -0.4

䎐䎓䎑䎕 -0.2

䎓 0.0

T[s]

䎓䎑䎕 0.2

䎓䎑䎗 0.4

䎓䎑䎙 0.6

䎓䎑䎛 䎔 0.8 䏛䎃䎔䎓䎐䎜1

(b) In case 599 times. Fig. 13.

INL with and without self-calibration (simulation results).

CLK

register Db2,Db1 3 Db0 CLK1 CLK2 PD + Integrator

To delay circuit

ΣΔTDC

7

encoder

Do7~ Do1

3

register

B2,B1 B0

3

3bit adder

3

Da2,Da1 Da0 3 Ds2,Ds1,Ds0

CLK1

τ

CLK2

τ

M U X

D Q R

+

7 Dout

Vout+

barrel shifter

7 R

M U X

clk

+

Fig. 14.

D7~D1

D Q

Fig. 16. Vout-

Circuit design of a single-bit ΣΔ TDC.

DWA

Block diagram of DWA logic.