Multi-Inverter Architectures for High Efficiency Power

Matilde D’Arpino

Università degli Studi di Cassino e del Lazio Meridionale

2012-2013

Matilde D’Arpino was born in Cassino, Italy, on July 6, 1986. She received the B.E. degree and the M.E. degree with honours in Electrical Engineering from the University of Cassino and Southern Lazio, in 2008 and 2010, respectively. In 2011, she joined the same University as PhD Student. Her research interests include power electronics, electrical drives, simulations and new control strategies for power converters.

Matilde D’Arpino

Università degli Studi di Cassino e del Lazio Meridionale

Author:

Multi-Inverter Architectures for High Efficiency Power Conversion

Doctoral Thesis for the degree of Philosophiae Doctor

The dissertation deals with power electronic converters and their application in the field of renewable energy and urban mobility. It focuses on the advantages of using the standard three-phase Voltage Source Inverter (VSI) as base unit to design high performance power conversion systems. In fact, VSI is still one of the most adopted topology of power converter. However, this solution shows disadvantages and limitations mainly due to dead-time effect and real characteristics of the semiconductor devices. An optimization technique is proposed to compensate the nonlinearity behaviour of VSI. For high performance and high power rate, multi-inverter VSI-based architecture is proposed for photovoltaic application. It is based on parallel VSIs system and it allows obtaining high efficiency with respect to a single VSI-based topology by means of a both optimal power sharing algorithm and interleaving modulation. Modular VSI-based power converter is also proposed for electric vehicle application. Two tandem converters are adopted to connect the hybrid energy storage system to two open-winding motors. Thanks to a supercapacitor auxiliary storage unit and to a suitable control algorithm, the proposed structure allows optimizing the vehicle performances in terms of traction control and power flows.


Abstract:

Scuola di Dottorato in Ingegneria Ciclo XXVI

SSD ING-IND/32

Dottorato di Ricerca in Sistemi, Tecnologie e Dispositivi per il Movimento e la Salute

` DEGLI STUDI DI CASSINO E DEL LAZIO UNIVERSITA MERIDIONALE SCUOLA DI DOTTORATO IN INGEGNERIA DIPARTIMENTO DI SCIENZE UMANE, SOCIALI E DELLA SALUTE

Multi-Inverter Architectures for High Efficiency Power Conversion Matilde D’Arpino [email protected]

In Partial Fulfillment of the Requirements for the Degree of PHILOSOPHIAE DOCTOR in Systems, Technologies and Devices for Movement and Health January 2014

TUTOR Prof. Giuseppe Tomasso

COORDINATOR Prof. Angelo Rodio

` DEGLI STUDI DI CASSINO E DEL UNIVERSITA LAZIO MERIDIONALE SCUOLA DI DOTTORATO IN INGEGNERIA

Date: January 2014 Author:

Matilde D’Arpino

Title:


Department:

DIPARTIMENTO DI SCIENZE UMANE, SOCIALI E DELLA

Degree:

SALUTE

PHILOSOPHIAE DOCTOR

Permission is herewith granted to university to circulate and to have copied for non-commercial purposes, at its discretion, the above title upon the request of individuals or institutions.

Signature of Author

THE AUTHOR RESERVES OTHER PUBLICATION RIGHTS, AND NEITHER THE THESIS NOR EXTENSIVE EXTRACTS FROM IT MAY BE PRINTED OR OTHERWISE REPRODUCED WITHOUT THE AUTHOR’S WRITTEN PERMISSION. THE AUTHOR ATTESTS THAT PERMISSION HAS BEEN OBTAINED FOR THE USE OF ANY COPYRIGHTED MATERIAL APPEARING IN THIS THESIS (OTHER THAN BRIEF EXCERPTS REQUIRING ONLY PROPER ACKNOWLEDGEMENT IN SCHOLARLY WRITING) AND THAT ALL SUCH USE IS CLEARLY ACKNOWLEDGED.

Nullius boni sine socio iucunda possessio est. No good thing is pleasing without friends to share it. Seneca, Epistulae morales ad Lucilium

My gratitude to the team of the Laboratory of Industrial Automation of University of Cassino and South Lazio. A particular mention to Prof. Giuseppe Tomasso, he has represented a precious guide for academic field, but not only, during these years. Moreover, many thanks to Eng. Mauro Di Monaco for the help and the support he gave me. I would like to thank Prof. Andreas Steimel and Prof. Volker Staudt to gave me the possibility to study in the Ruhr University of Bochum. At the end of this challenging, but full of satisfaction, route I have to say “Thank you!” to all those who have walked and are walking with me, my family and my friends.

vi

Contents Acknowledgements

6

Introduction

11

Power converters: configurations and modulations

1

I

Power Electronic Converters

1

I.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

I.2

Power semiconductor devices . . . . . . . . . . . . . . . . . . . . .

2

I.2.1

Ideal and real characteristics . . . . . . . . . . . . . . . . .

2

I.2.2

Power losses . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

I.2.3

Thermal characteristic . . . . . . . . . . . . . . . . . . . . .

8

I.2.4

Safe Operating Area . . . . . . . . . . . . . . . . . . . . . .

9

I.3

Power electronic converters classification . . . . . . . . . . . . . . .

9

I.4

Harmonics content . . . . . . . . . . . . . . . . . . . . . . . . . . .

11

I.4.1

Fourier analysis . . . . . . . . . . . . . . . . . . . . . . . . .

11

I.4.2

Power analysis . . . . . . . . . . . . . . . . . . . . . . . . .

13

II Voltage Source Inverter

15

II.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

II.2 Voltage Source Inverter basic concept . . . . . . . . . . . . . . . .

16

II.2.1 Real behavior . . . . . . . . . . . . . . . . . . . . . . . . . .

17

II.3 Three-phase Voltage Source Inverter mathematical model . . . . .

18

II.3.1 Averaged mathematical model for Voltage Source Inverter .

22

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CONTENTS

II.4 Modulation techniques . . . . . . . . . . . . . . . . . . . . . . . . .

23

II.4.1 Square-wave modulation technique . . . . . . . . . . . . . .

24

II.4.2 Carried-based Pulse Width Modulation . . . . . . . . . . .

25

II.4.3 Space Vector Modulation . . . . . . . . . . . . . . . . . . .

27

II.4.3.1

Switching sequences . . . . . . . . . . . . . . . . .

30

II.4.3.2

Comparison . . . . . . . . . . . . . . . . . . . . . .

32

II.4.4 Hysteresis control . . . . . . . . . . . . . . . . . . . . . . . .

32

II.4.5 Sub-oscillation current control

. . . . . . . . . . . . . . . .

34

II.4.6 Predictive current control . . . . . . . . . . . . . . . . . . .

35

II.5 Total Harmonics Distortion evaluation . . . . . . . . . . . . . . . .

37

III High efficiency DC/AC power converters

39

III.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39

III.2 Historical background . . . . . . . . . . . . . . . . . . . . . . . . .

40

III.3 DC/AC power converters topologies . . . . . . . . . . . . . . . . .

41

III.4 Multilevel converters . . . . . . . . . . . . . . . . . . . . . . . . . .

42

III.4.1 Multilevel basic concept . . . . . . . . . . . . . . . . . . . .

42

III.4.2 Multilevel converter mathematical model . . . . . . . . . .

43

III.4.3 Multilevel converter redundant states . . . . . . . . . . . .

44

III.4.4 Diode-Clamped multilevel converter . . . . . . . . . . . . .

45

III.4.5 Capacitor-Clamped multilevel converter . . . . . . . . . . .

48

III.4.6 Cascaded H-bridge . . . . . . . . . . . . . . . . . . . . . . .

49

III.4.7 Multilevel converter modulation techniques . . . . . . . . .

51

III.4.7.1 Space Vector Control . . . . . . . . . . . . . . . .

51

III.4.7.2 Selective Harmonic Elimination modulation . . . .

52

III.4.7.3 Hybrid PWM modulation . . . . . . . . . . . . . .

52

III.4.7.4 Space Vector Modulation . . . . . . . . . . . . . .

54

III.4.7.5 Phase-shifted modulation . . . . . . . . . . . . . .

54

III.4.7.6 Level-shifted modulation . . . . . . . . . . . . . .

54

III.5 Tandem converter

. . . . . . . . . . . . . . . . . . . . . . . . . . .

55

III.5.1 Tandem converter mathematical model . . . . . . . . . . .

55

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CONTENTS

III.5.2 Tandem converter redundant states . . . . . . . . . . . . . .

58

III.5.3 Tandem converter Modulation techniques . . . . . . . . . .

60

III.6 Parallel VSIs converter . . . . . . . . . . . . . . . . . . . . . . . . .

63

III.6.1 Parallel VSIs converter with isolation techniques . . . . . .

64

III.6.2 Parallel VSIs converter with current-sharing reactors . . . .

66

III.6.3 Parallel VSIs converter with circulating current control . .

67

III.6.3.1 Zero-sequence circulating current model . . . . . .

68

III.6.4 Parallel VSIs converter modulation techniques . . . . . . .

70

III.7 Optimization techniques for two-level VSI . . . . . . . . . . . . . .

71

III.7.1 Output filter for VSI . . . . . . . . . . . . . . . . . . . . . .

73

III.7.2 Parallel-resonant dc-link VSI . . . . . . . . . . . . . . . . .

76

III.7.3 Hybrid modulation techniques . . . . . . . . . . . . . . . .

77

III.7.4 Non-linearity compensation techniques for VSI . . . . . . .

78

III.7.4.1 State of arts . . . . . . . . . . . . . . . . . . . . .

79

III.7.4.2 Recursive dead-time compensation techniques . .

80

III.7.4.3 Simulation results . . . . . . . . . . . . . . . . . .

83

III.7.4.4 Experimental results . . . . . . . . . . . . . . . . .

83

Application

89

IV Power conversion systems for photovoltaic applications

89

IV.1 Overview of PV power conversion systems . . . . . . . . . . . . . .

89

IV.1.1 Power conversion system topologies . . . . . . . . . . . . . .

93

IV.1.2 Filters topologies . . . . . . . . . . . . . . . . . . . . . . . .

94

IV.1.3 System sizing . . . . . . . . . . . . . . . . . . . . . . . . . .

95

IV.2 Multi-inverters power conversion system . . . . . . . . . . . . . . .

95

IV.2.1 Modelling and Control Strategy of Power Converter . . . .

96

IV.2.2 Interleaving Modulation . . . . . . . . . . . . . . . . . . . .

98

IV.2.3 Power losses calculation . . . . . . . . . . . . . . . . . . . .

99

IV.2.4 Total harmonics distortion calculation . . . . . . . . . . . . 100 IV.3 Optimal power sharing algorithm . . . . . . . . . . . . . . . . . . . 100 ix

CONTENTS

IV.4 Numerical results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 IV.4.1 High power test-bench . . . . . . . . . . . . . . . . . . . . . 106 IV.4.2 Low power test-bench . . . . . . . . . . . . . . . . . . . . . 109 IV.5 Experimental analysis . . . . . . . . . . . . . . . . . . . . . . . . . 112 IV.5.1 Experimental set-up . . . . . . . . . . . . . . . . . . . . . . 112 IV.5.2 Experimental results . . . . . . . . . . . . . . . . . . . . . . 113 V Power converters for urban mobility V.1 Overwiew of electric vehicles

117

. . . . . . . . . . . . . . . . . . . . . 117

V.1.1 Hybrid electric vehicles . . . . . . . . . . . . . . . . . . . . 119 V.1.2 Fully-electric vehicles . . . . . . . . . . . . . . . . . . . . . . 121 V.1.3 Powertrain sizing . . . . . . . . . . . . . . . . . . . . . . . . 122 V.1.3.1

Urban test cycles

. . . . . . . . . . . . . . . . . . 124

V.1.4 Energy storage systems . . . . . . . . . . . . . . . . . . . . 125 V.1.4.1

Batteries . . . . . . . . . . . . . . . . . . . . . . . 128

V.1.4.2

Ultracapacitors . . . . . . . . . . . . . . . . . . . . 130

V.1.4.3

Fuel cells . . . . . . . . . . . . . . . . . . . . . . . 131

V.1.4.4

Flywheels . . . . . . . . . . . . . . . . . . . . . . . 132

V.1.4.5

Hybrid energy storage systems . . . . . . . . . . . 132

V.1.5 Electric propulsion systems . . . . . . . . . . . . . . . . . . 133 V.1.5.1

Electrical machine for EVs . . . . . . . . . . . . . 135

V.1.5.2

Power conversion system for EVs . . . . . . . . . . 137

V.1.5.2.1

Tandem converter for EV application . . 139

V.2 Multi-inverter electrical drive for double motor electric vehicles . . 142 V.2.1 Double-cascaded converter mathematical model . . . . . . . 143 V.2.2 Kinematic model of differential . . . . . . . . . . . . . . . . 145 V.2.3 Induction machine mathematical model and control strategy 146 V.2.4 Power flows management algorithm . . . . . . . . . . . . . . 149 V.2.4.1

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . 150

V.2.4.2

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . 151

V.2.4.3

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . 152 x

CONTENTS

V.2.4.4

Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . 152

V.2.4.5

Mode 5 . . . . . . . . . . . . . . . . . . . . . . . . 154

V.2.4.6

Flowchart of the algorithm . . . . . . . . . . . . . 155

V.2.5 Simulation results . . . . . . . . . . . . . . . . . . . . . . . 155 V.2.6 Experimental results . . . . . . . . . . . . . . . . . . . . . . 158 Conclusions

161

A Space vector

167

A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 A.1.1 Space vector representation . . . . . . . . . . . . . . . . . . 167 A.1.2 Clarke transform . . . . . . . . . . . . . . . . . . . . . . . . 167 A.1.3 Park transform . . . . . . . . . . . . . . . . . . . . . . . . . 169 Bibliography

171

xi

CONTENTS

xii

Introduction The research described in this dissertation concerns about power electronic converters for mobility and industrial applications. The presented technologies and devices find application in the field of renewable energy and urban mobility. Moreover, the proposed power converter system can be adopted in biomedical fields. The research focuses on multi-converter systems based on Voltage Source Inverter (VSI) with the aim to obtain high efficient and high reliable systems.

Motivation The commitment of the global authority to mitigate the climate change has been demonstrated by setting to 2050 the deadline for a 50% of reduction of gas emissions. Energy efficiency, renewable energies, electric vehicles are expected to reduce the environment pollution. Moreover, the global energy consumption is growing day by day, then energy efficiency improvement makes an essential goal. Since 1973, the global energy demand has enhanced with a rate of only 1.7% a year thanks to the energy efficiency improvements [1]. Figure 1 shows the energy efficiency improvement. In particular, the long term energy use would have been 63% higher in 2006 than the real one, according to the study of the International Energy Agency (IEA). Energy power generation and transportation sectors are the major forms of energy consumption [2]. In the past years, the global authority pushed for a reduction of gas emissions, a use of green energy sources and a efficient utilization of energy. Moreover, public investments are increasing for research based on minimizing the use of hydrocarbons for electric energy generation and transportation. New technologies with high efficiency and no-emission result necessary to encourage the challenge. In transportation sector, in the last years, several hybrid and full-electric vehicles have been developed by the major automotive manufactures and governments have lunched several plans for the growing of electric vehicle distribution. Moreover, the proliferation of renewable energy plants, such as photovoltaic systems, has been due to the government incentives. xiii

Introduction

Figure 1: Long-term energy savings from improvements in energy efficiency [1]. The research described in this dissertation regards power electronics converters applied to renewable energy and urban mobility. The main motivations of this research concerns the advantages on the use of VSIs, instead of no-standard technologies in order to increase conversion efficiency. In fact, considering new technologies, such as multilevel converters, benefits in terms of energy efficiency improvements are usually not well balanced by the more complexity in the structure and control. Three-phase VSIs are widely used in industrial applications, renewable systems, motor controls, distributed generations. Therefore, proper optimization techniques have to be adopted to improve their performance. Multi-inverter systems based on VSI present benefit respect to the single-converter systems, improving the conversion efficiency and the power quality increasing can be achieved. These systems have high reliability and high flexibility compared to standard structures.

Original contribute This dissertation provides some recent trends in high performance power conversion systems based on Voltage Source Inverter. By means of an optimal design of VSI control technique an improvement of their performance is achieved. A new method for the compensation of the VSI non-linearity at steady-state conditions is presented. In details, the compensation of the effect of the dead-time, as well as the ones due to the other non-linearities, is an important technical issue to reduce voltage drop and current distortion for VSI. Two high-efficiency high-performance power conversion systems are proposed for photovoltaic plants and electric vehicle applications. Both system are equipped with suitable control algorithms. In details, − parallel VSIs conversion system for photovoltaic applications; − multi-inverter electrical drive for double motor electric vehicles. xiv

Introduction

The main contribute of this dissertation concerns the approach of control of VSI and multi-inverter systems ensuring high conversion efficiency and high performance of the power converter.

Applications Power electronics is a technological sector related to the control of energy flows from sources to loads. The power control is realized by means of switching semiconductor devices. In general, power electronics has a big amount of applications [2], [3]. The power conversion structures presented in this dissertation can be focused on the following applications: − photovoltaic; − electric vehicle; − biomedical.

Photovoltaic applications Distributed generation, such as photovoltaic systems, has been widely developed in last years due to both safeguards of environment increasing of power consumption and government incentives. Photovoltaic (PV) plants have high installation costs due to the price of the PV modules [2]. Thus, the increasing of the conversion efficiency is a technological requirement. Moreover, the intermittent nature of the solar resource introduces issues regarding the stability, reliability and power quality of the utility grid. The main contribute of this dissertation in PV field is the approach of control of multi-inverter systems in parallel configuration [4]. In details, a parallel VSIs structure with proper control algorithm is presented. It allows obtaining high conversion efficiency and high quality of the ac current thanks to a suitable interleaving modulation and a proper selection of the best VSIs configuration. This structure finds application as conversion unit in photovoltaic plants; moreover it can be used in industrial applications.

Electric vehicle applications Electric vehicles (EVs) are considered a solution for the reduction of gas emissions and air pollution. EVs have several advantages compared to standard road vehicles, such as high efficiency and no-emissions. Unfortunately, the energy storage system has high costs, low life-cycle and slowly charges. Thus, the development of power electronics, electrical machines and energy storage system has a key role for the EVs expansion. xv

Introduction

In this dissertation a new topology of power conversion system based on tandem converter is presented for double-motor electric vehicles [5]. A suitable control structure is also performed with the aim to control the multi-energy storage system (batteries and supercapacitors) and to improve the vehicle performance. The vehicle implements the electric differential with a direct-torque control ensuring a high stability and a reduced mechanical transmission.

Biomedical applications The applications of power electronics to biomedical field are various and they are subject of intensive researches [6]. Medical equipments require stringent specifications related to the user safeguard. Many disabled persons are dependent on electric vehicle systems for the mobility inside and outside the home. Performance, stability and reliability of vehicles have an important role and these characteristics influence the life of the disabled person [7]. The vehicle requirements can be identified as: − high reliability; − high efficiency; − high stability; − high performance; − low emissions; − light weight and small volume; − respect of regulation concerning EMI/EMC. The topology of vehicle depends on the pathology that afflicts the disabled person. Thus, the vehicle has to be modular and the user interface has to be adapted to each user. Electric vehicle represents a valid solution for this application. First, this kind of technology safeguard the user thanks to the low of emissions. The presented powertrain topology has low weight due to the reduced transmission section and the electric differential. The stability of the vehicle is increased thanks to highperformance electrical drivetrain equipped with torque control to ensure the stability of the driving on various surfaces and conditions. The reliability is also increased by means of energy storage system efficiency. A supercapacitor bank is included to provide the required peak power and to avoid the overload of the batteries. High maneuverability is usually obtained with the driving assistant of electric equipment. The described technology can be applied to handling systems with electromechanics actuators and devices. Low power equipments can be powered with the proposed power conversion system with high efficiency thanks to both supercapacitors and a suitable control algorithm. In details prostheses, surgical robots, xvi

Introduction

artificial limbs are example of these applications.

Methodological approach The methodology approach is crucial for the research activity to define a systematic procedure on a certain objective. An experimental-research based model has been adopted and it is based on the following steps: − problem review; − theoretical analysis; − simulation analysis; − experimental analysis. Figure 2 represents the flowchart of the methodological approach. To gain familiarity with the specific aspect and to know the state of the art of the area of interest, a bibliographic analysis of the background is necessary. In research, the theoretical analysis represents an important step to provide an explanation of the system, by means of mathematical models. The parameters of this models can be achieved either mathematically or by experimental testing. A new structure and/or a new control concept can be carried out by the state of art analysis matched with future improvement. Computer simulations, modelling circuits and analysis tools are instruments used to investigate the behavior of the power conversion system and control algorithms. Model-based simulations and analysis tools are instruments used to investigate and verify the system behaviour. The proposed model is compared with standard technologies in the same operating conditions to show performance improvement, i.e. in terms of efficiency and power quality. In any case, the simulation results can confirm or not the hypothesis. Moreover, the simulation results can demonstrate the no-accuracy of the model. Thus, an improvement of the proposed system can be necessary. Finally, an experimental set-up is designed and implemented to fully-validate the proposed model or, used as feedback for a further improvement of the model itself.

Summary The dissertation is divided into two sections. The former one is a general introduction on the power electronics converters, with a particular attention on VSI and multi-inverters structures. In the latter one, several applications of these topologies in the field of renewable energy and electrical vehicles are presented. In details, the dissertation is organized as following: Power converters: configurations and modulations

xvii

Introduction

Figure 2: Flowchart of the methodological approach. – Chapter I presents an introduction to Power Electronics. Starting from the definition of power electronics converter, and after some considerations about the power semiconductor devices, this chapter presents an overview on power electronics converters. – Chapter II reports information about the three-phase Voltage Source Inverter (VSI). In particular, an accurate mathematical model is presented taking into account both ideal and real characteristics of power semiconductor devices. The state of the art of the modulation technique for inverters is reported taking into account the generated harmonic content. – Chapter III describes the main non-standard topologies of DC/AC power converters, that in the last few years have been presented with the aim to ensure both high power and high efficiency. Multilevel converter concept is introduced and widely analyzed. Moreover, several structures are reported. Emphasis is given to structures based on multi-inverter, such as parallel connection of standard VSIs and Tandem converters. After an overview of the state of the art, the mathematical models and modulation techniques analysis is reported. Moreover, starting from the causes of non-linearity for a VSI and the state of the art of the compensation methods, a new strategy for the VSI non-linearity compensations is presented and validate by means of both simulation and experimental results. Applications

– Chapter IV reports the applications of parallel connected VSIs to the xviii

Introduction

field of renewable energy. A novel power converter configuration for high power grid-connected photovoltaic (PV) systems is presented in this chapter. It allows increasing the conversion efficiency with respect to a classical solution, based on centralized inverter, in whatever operating conditions. In particular, the improvement of efficiency is due to both optimal power sharing algorithm and suitable interleaving modulation technique. – Chapter V shows a study on tandem converters with applications on electric vehicles. After a brief introduction on electric vehicles, a doublemotor powertrain topology is presented. Thanks to a supercapacitor auxiliary storage unit and to a suitable control algorithm, the proposed set-up allows optimizing the vehicle performance in terms of traction control and power flows. Finally some concluding remarks and future plans are presented.

xix

Introduction

xx

Power converters: configurations and modulations

1

Chapter I

Power Electronic Converters Power electronic converters are widely used to manage power flow between electrical sources and loads. In the last years, the development of power electronics has been due to power semiconductor devices improvements, in terms of power rating, switching frequency and efficiency. Moreover, costs reduction and increase of reliability have been also achieved. In power electronic field, power electronic circuit sizing and control are important aspects to correct handle a converter. Thus, in this chapter, a brief introduction on power electronic converters is given.

I.1

Introduction

A power electronic converter is an electrical system used to interface power sources to loads. If adequately controlled, it allows adapting voltage and/or current static characteristics, such as RMS and frequency. A base scheme of the power conversion concept is shown in fig. I.1. It is able to control with high efficiency the power flows between two or more different systems using power electronic devices (§I.2). Power electronic converters are generally based on: − power semiconductor devices; − storage elements (i.e. capacitors and inductances); − transformers; − passive elements (i.e. resistances). They are widely used in several applications, such as residential, commercial, industrial, transportation, telecommunications, energy conversion and aerospace systems. In details, they are targeted to be used in server, telecom, power supplies, solar inverters, industrial motor control systems, robotics, traction vehicles, ship propulsion, electrical car and energy transmission. In fig. I.2 the topologies of 1

CHAPTER I. Power Electronic Converters

Figure I.1: Power electronic converter principle. power semiconductor devices are correlated to the application areas.

I.2

Power semiconductor devices

The phenomenon of semiconductance was observed by K. F. Braun in 1874 and in 1929 W. Schottky obtained experimental results on a metal-semiconductor junction [8]. These new materials were quickly used to rectifying alternating current instead of mechanical switches. The p-n junction was discovered in 1947 by Shockley, Bardeer and Brattain and they found the basis for the future developments in power electronics. In 1952 and 1954, General Electric and Texas Instruments manufactured the first germanium diode and the first silicon transistor, respectively. Before the 1960s, semiconductor devices were characterized by low current and voltage capability (less than one ampere and few tens of volts). Later on, several patents have been presented regarding solid-state electronics and semiconductors devices characterized by more capability and reliability. Moreover in the 1990s microprocessors, integrated circuits and third generation power switches were developed. Nowadays, Silicon Carbide Junction Transistors are studied to reduce size/weight/volume and increase conversion efficiency of power electronic devices. Power electronic converter operating conditions are function of the features and behaviour of its most important components: power semiconductor devices. In detail, a brief summary of several power semiconductor devices is reported in terms of voltage, current and switching frequency capabilities.

I.2.1

Ideal and real characteristics

A power semiconductor device has two stable working points: the on-state and the off-state [10]. For an ideal switch, the on-state is characterized by zero voltage on its terminals and any current in any directions. Whereas, during the off-state no current is flowing into the device independently of the voltage. Moreover, it 2

I.2 Power semiconductor devices

Figure I.2: Power semiconductor devices in relation to the application areas [9].

changes its state instantaneously. The ideal behaviour of a power semiconductors devices is depicted in fig. I.3. The analysis of power converters can be easily made considering the characteristics of ideal switch. A real switch has different limitations compared to the ideal one, in particular it is characterized by: − direction of on-state current; − on-state voltage drop; − off-state leakage current; − off-state maximum voltage; − maximum switching frequency. Taking into account the type of control, power semiconductor devices can be divided into three categories [3]: − diode; 3


Figure I.3: Ideal power semiconductor devices. − thyristor ; − controllable switches. The diode is an uncontrollable switch and the on/off-states depend on power circuit. the thyristor is semi-controllable switch. In details, the on-state is set by a control signal, while off-state is function of the working conditions. The controllable switches is also called fully-controllable switch and its on/off-states are set by means of a control circuit. Several power semiconductor devices can be included in the third category, such as Bipolar Junction Transistor (BJT), Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), Gate Turn-Off thyristors (GTO) and Insulated Gate Bipolar Transistors (IGBT). In fig. I.4, the electric model and the static characteristic of some power semiconductor device topologies are reported. Detailed informations about the power semiconductor devices are collected in [3].

I.2.2

Power losses

A power circuit implemented with ideal switches is considered lossless. Power semiconductor devices improvements are oriented of increasing both switching frequency and power density. Thus a suitable control strategy has to be adopted to reduce device power losses. Furthermore, a thermal study of the system is required to correct manage a power electronic converter [11]. Almost all power semiconductor devices, included in power converter, operate in “switching mode”. In this operation mode, the switch works with two stable states (turned on, turned off) [3]. The transitions from conducting state to the non-conducting one and vice-versa cause an undesirable loss of energy. A power semiconductor device is affected by static loss, during the on/off-state, and dynamic loss, during the switching time. The former loss, called conduction loss, mainly depends on the current that is flowing in the device, while the latter loss, called switching loss, is function of the switching frequency of the power semicon4


Figure I.4: Power semiconductor devices: symbols and characteristics.

ductor device. Moreover, a diode has reverse-recovery loss instead that switching loss during the turn-off. A generic fully-controllable power device is depicted in fig. I.5 a). During the off-state, no current flows through the switch and, during the on-state, the current flows only in one direction. Considering the test-circuit depicted in fig. I.5 b), the voltage and current waveforms of the generic power semiconductor device are shown in fig. I.6. In particular, it possible to notice that the turn-on and turn-off are not instantaneous and the voltage drop is non-zero in the on-state. The leakage current during the off-state is negligible. Several methods for estimation conversion losses are presented in literature and collected in [12, 13]. The evaluation of the power losses of a power converter is 5


a)

b)

Figure I.5: a) Generic controllable switch b) Power semiconductor device test circuit. complicated, since they are function of several system parameters. Taking into account the device characteristics and measuring load current and switching command, a simple and precise method for power losses estimation of a power semiconductor device is analyzed. In particular, approximating a switch with a series connection of dc voltage source (Von ), representing on-state zerocurrent collector-emitter voltage, and a collector-emitter on-state resistance (Ron ), the switch conduction loss (Pcd ) is given by: 2 Pcd = Von IAVG + Ron IRMS

where: IAVG IRMS

(I.1)

average switch current; RMS switch current.

The switching loss (Psw ) is calculated considering the energy losses of the power device during turn-on and turn-off [14]. In general, the switching losses are proportional to switching frequency and turn-on and turn-off time. In particular, considering the energy per pulse, function of current power device, during turn-on (Eon ) and turn-off (Eoff ), the Psw can be estimated as follows: ! TX TX v fsw v fsw 1 Eon,q δon,q + Eoff,q δoff,q Psw = (I.2) Ts q=1 where: q index of turn-on, turn-off or reverse-recovery transition; Tv period of the grid voltage; fsw switching frequency; 1 when the turn-on of the switch occurs δon,q 0 otherwise 1 when the turn-off of the switch occurs δoff,q 0 otherwise 6


Figure I.6: Instantaneous power losses of a power semiconductor device. The balance of these losses is function of the used switch, thus the parameters of conduction and switching power losses can be calculated by means of the parameters reported in the datasheet of the power device. As matter of fact, these parameters are function of the chosen device, but also of the operating conditions in terms of processed power and environment temperature. The conversion efficiency (ηc ) of a power conversion system can be expresses by: ηc =

Pout Pin

(I.3)

where Pout and Pin are respectively the output and input total active power of the power converter. The power losses of power electronic converter can be divided in: conduction losses (Pcd ), switching losses (Psw ) and control circuits power losses (Pct ). The control circuits power losses (Pct ) are usually considered as a constant value, thus the Pct have a strong impact on the conversion efficiency when low power is processed. Conduction losses (Pcd ) are function of the load current, thus they increase with 7


the require power, while switching losses (Psw ) are mainly due to the switching frequency and the dc-link voltage. Thus the total power losses of the power converter (Ploss,c ) are yield as: Ploss,c = Pcd + Psw + Pct (I.4) Moreover, the power converter efficiency can be expressed as function of Ploss,c as: ηc =

I.2.3

Pout Pout + Ploss,c

(I.5)

Thermal characteristic

Power losses are the causes of the power semiconductor thermal behaviour. In fact, switches are usually mounted on a heatsink with the aim to keep the junction temperature in the safe operating area, fulfil the manufacturer’s limits. Several methods are available to waste the produced heat, such as: − natural air cooling; − forced air cooling; − water cooling. Thus, the thermal behaviour of the power device depends on the thermal impedance from junction to case of the switch (Rjc ), the thermal impedance of the interface device-heatsink (Rch , depending on the materials and shape of the contact area) and the thermal impedance of the heatsink (Rha ), as shown in fig. I.7(a) [15]. A steady-state thermal model of the system is depicted in fig. I.7(b) and the thermal impedances are schematized as a thermal resistances (°C/W) neglecting the dynamic behaviour. Power losses are modelled as a current flowing through the thermal resistance, creating a temperature rising, represented by means of voltage rising. The thermal model respects Kirchhoff’s and Ohm’s laws. Therefore, the total thermal resistance from the junction to the environment, Rja , is obtained as: Rja = Rjc + Rch + Rha

(I.6)

The design of the heatsink, in terms of desired thermal resistance to avoid the junction overtemperature, is yield as following: Tj − Ta − (Rjc + Rch ) (I.7) Pm where Tj is the maximum temperature of the junction and Ta is the temperature of the environment far away from the heatsink. Pm is the maximum power can be dissipated by the device case and is equal to the maximum allowable heat generated by conduction loss (eq. I.1) when the nominal current is processed. If more than one power semiconductor device is thermally coupled to a heatsink, the thermal model becomes complex and switches should be spaced to obtain a uniform power density. Rha =

8

I.3 Power electronic converters classification

(a) thermal behavior

(b) thermal model

Figure I.7: Switch and heatsink system.

I.2.4

Safe Operating Area

Power semiconductor devices are selected on the basis of the considered application, desired power and performance. The Safe Operating Area (SOA) gives informations about power semiconductor device operating area. For an optimal selection of a power semiconductor device, the following arguments have to be considered [16]: − delay time; − switching losses; − packaging; − operating current density; − operating voltage; − operating power; − application. Figure I.2 shows the application region of several switching devices as function of the required power and the switching frequency. In figure I.8(a), the operating area of the power device function of rate voltage and current is reported. Silicon carbide Junction Transistors, new border development in power semiconductor devices, are exhibit ultra-fast switching capability, square safe operating area, temperature-independent transient energy losses and switching time (fig. I.8(b)).

I.3

Power electronic converters classification

In literature, different classifications of power electronic converters are available [3]. In particular on the basis of the input/output frequency, the power converters 9


(a) current-voltage-frequency dependance [3]

(b) frequency-power dependance [17]

Figure I.8: Comparison of power semiconductor devices operating area. are classified in: − dc-dc − dc-ac − ac-dc − ac-ac Power converters with an ac side are also classified considering the number of phases (i.e. single-phase, three-phase, multi-phase systems) and the number of voltage levels (i.e. two-level, three-level, multi-level converters). Moreover, power 10

I.4 Harmonics content

converters are defined bidirectional or unidirectional if the power flow direction through the converter is reversible or not. As example, in the case of ac-dc or dc-ac converter, in a rectifier -mode the average power flows from the dc to the ac side, while in a inverter -mode the power flows in the opposite direction. Inverters are also classified in base of the source type, in particular there are Voltage Source Inverter (VSI) and Current Source Inverter (CSI) (§II). Power converters are divided in three categories on the basis of how they are controlled: − line-frequency converter, when the commutation of the semiconductor devices depends on the line-voltage waveform. − switching converter, when the commutation frequency of the semiconductor devices is higher than the line frequency. − resonant converter, when the commutation of the semiconductor devices is with zero voltage and/or current. Resonant converter are controlled in soft-switching mode; thus, power semiconductor devices can be used at much higher frequencies due to the lower switching losses, compared to hard-switched converter.

I.4

Harmonics content

As well known, power electronic converters are a non-liner elements, in particular they provide the desired output with different harmonics in terms of current and voltage.

I.4.1

Fourier analysis

The Fourier theory is a closed-form to analytically evaluate the harmonics content for power electronic conversion system. In particular, it is a mathematical methods which allows obtaining the spectrum components of power converter waveforms, such as current and voltage [18]. In general, a periodic function f (t) can be expressed by means the Fourier analysis [3, 19] as following: f (t) = F0 +

∞ X h=1

∞

fh (t) =

X 1 a0 + (ah cos(hωt) + bh sin(hωt)) 2

(I.8)

h=1

where: h oder of the harmonic; ω fundamental pulsation of the waveform; F0 average value on the fundamental period; Z 1 T 1 F0 = f (t)d(ωt) = a0 T 0 2 11

(I.9)


(a) h ≤ 5

(b) h ≤ 15

Figure I.9: Example of Fourier analysis. 2 ah = T

Z

2 bh = T

Z

T

f (t)cos(hωt)d(ωt)

(I.10)

f (t)sin(hωt)d(ωt)

(I.11)

0 T

0

F0 , ah and bh are defined Fourier coefficients. If the function is odd, bh is equal to zero (with h=0, ..., ∞), while if it is even, ah is equal to zero (with h=0, ..., ∞). The harmonic amplitude is function of the Fourier coefficients. The h-th harmonic has a pulsation h-times the fundamental frequency, thus the harmonic pulsation is defined as following: ωh = hω

(I.12)

In fig. I.9(a), a simple Fourier analysis example is depicted. Considering that the function is an odd waveform and imposing an approximation of fifth order, the waveform ys is decomposed as a fundamental y1 (having the same period of ys ) and the third and fifth harmonics (y3 and y5 ). The result of the decomposition is y 0 . Increasing the number of harmonics the result will fit the ys , as shown in fig. I.9(b). In literature, some index are presented in order to easy determinate the quality of a waveform. The most common index is the Total Harmonics Distortion (THD), that is defined as the ratio between the harmonic components to the fundamental component, as following: pP∞ 2 h=2 Fh THD = · 100 (I.13) F1 This index gives information about the total waveform distortion, it is clear that two waveforms with the same value of THD can have different harmonics distribution. The RMS of the waveform is calculated taking into account all the harmonics 12

I.4 Harmonics content

components, as shown in the following equation: s FRMS =

I.4.2

1 T

T

Z 0

v u ∞ u1 X 2 f (t)d(ωt) = t F 2 (h) T 0

(I.14)

Power analysis

A steady-state analysis of the harmonics content effects on an electrical circuit can be made by means of the Fourier analysis. Assuming a grid voltage equal to:

vs (t) = vs1 (t) +

∞ X

vsh (t)

h=2

=

√

2Vs1 sin(ω1 t) +

∞ X √

(I.15) 2Vsh sin(ωh t)

h=2

where: ω1 pulsation of the fundamental; ωh pulsation of the h-th harmonic. The current can be represented as following:

is (t) = is1 (t) +

∞ X

ish (t)

h=2

=

√

2Is1 sin(ω1 t − Φ1 ) +

∞ X √

(I.16) 2Ish sin(ωh t − Φh )

h=2

where: Φ1 phase angle between voltage and current fundamental; Φh phase angle between h-th voltage and current harmonics. Considering eq. I.14, the voltage and current RMS values Vs and Is on the fundamental period T1 = 2π/ω1 are carried out: s Vs = s Is =

1 T1

Z

1 T1

Z

T1

vs2 (t)dt

0

0

13

(I.17) T1

i2s (t)dt


Thus, by means of eq. I.16, the following relations are obtained: v u ∞ X u 2 Vs = tVs12 + Vsh h=2

v u ∞ X u 2 + 2 Is = tIs1 Ish

(I.18)

h=2

It is possible to notice that a square-waveform has a greater RMS value compared to a sine wave one, due to the harmonic content. On the basis of the basic definition of average true power P , Z T1 1 vs (t)is (t)dt (I.19) P = T1 0 and considering eq.s I.15 and I.16, the true power P is obtained noting that the integrals of all cross-product terms are zero, ! ! Z T1 ∞ ∞ X X 1 P = vs1 (t) + vsh (t) is1 (t) + ish (t) dt T1 0 h=2 h=2 (I.20) ∞ X = Vs1 Is1 cos(Φ1 ) + Vsh Ish cos(Φh ) h=2

In case of a purely sinusoidal grid voltage, √ vs (t) = 2Vs1 sin(ω1 t) the true power P is yield by means of eq. I.20, Z T1 √ √ 1 P = 2Vs1 sin(ω1 t) · 2Is1 sin(ω1 t − Φ1 )dt T1 0 = Vs1 Is1 cos(Φ1 )

(I.21)

(I.22)

The current components do not contribute to the average active power consumption if there are no corresponding isofrequential voltage components. On the contrary, the apparent power S is correlated to all the harmonics content, as function of the voltage and current RMS value: S = Vs · Is

(I.23)

The power factor P F is defined as the ratio of the active power on the apparent power: P PF = = cos(Φ) (I.24) S Using the definition of RMS value (eq. I.14), P F can be written as follows: PF = q

cos(Φ1 ) 1 + T HDi2s

14

(I.25)

Chapter II

Voltage Source Inverter Fully-controlled dc-ac converters are commonly used to produce a controllable sinusoidal ac output starting from a dc voltage source. The output waveform is regulated by means of a modulation technique, that, acting on the semiconductor power devices, allows modifying amplitude, frequency and phase of the output waveform. Inverters are characterized by an harmonic distortion of the input/output current and voltage waveforms that is function of both operating condition and modulation technique. In this chapter, three-phase Voltage Source Inverter is discussed in terms of mathematical model and modulation techniques.

II.1

Introduction

Inverters are widely used in power electronics especially in industrial applications. Taking into account the supply source, dc-ac converter can be classified as Voltage Source Inverter (VSI) and Current Source Inverter (CSI), as shown in II.1. In particular, the dc-link uses a capacitor to regulate voltage ripple and to store energy for former topology and an inductor to regulate current ripple and store energy for the latter one. Due to the dynamic response, in industrial applications VSI is often preferred to CSI to obtain high reaction time of the system and, thus, high-performance in transient and in steady-state. In fact, VSI allows using smaller commutation time than CSI. Nowadays, CSIs are used for very high power applications. The power flow through an dc-ac power converters is reversible, thus two topologies are presented [20]: − inverter (dc-ac): the power flows from ac side to dc side; − rectifier (ac-dc): the power flows from dc side to ac side; 15

CHAPTER II. Voltage Source Inverter

a) Voltage Source Inverter (VSI)

b) Current Source Inverter (CSI)

Figure II.1: Structure of a two-level dc-ac converter. For example, a dc-ac converter, starting from a dc source, can supply an ac motor drive. Moreover, it can be also used to get the power of a photovoltaic field into the ac grid. VSIs are divided into 3 categories [3]: − Square-wave inverters - inverter has to control only the ac output voltage frequency, in fact the dc voltage is controlled in such a way to regulate the magnitude of ac output voltage; the output voltage is similar to a square wave. − Pulse-width-modulated inverters - starting from a constant dc-link voltage, inverter controls the magnitude and the frequency of the ac side by means of Pulse Width Modulation (PWM) technique. − Single-phase inverters with voltage cancellation - inverter controls the magnitude and the frequency without PWM techniques, even if a constant dc-link voltage is used; voltage cancellation technique is only possible for single-phase inverter.

II.2

Voltage Source Inverter basic concept

Voltage Source Inverter is composed by one or more base structures (fig. II.2(a)) according to the number of phases. The base structure is arranged by means of two fully-controllable switches and two free-wheeling diodes connected to a dc-link. For, example, three-phase VSI consists of three legs, one for each phase. The state of two switches of the leg is controlled as complementary pair to avoid the short-circuit on the dc source. In detail, if S + is closed, S - must be opened. Thus, the behaviour of the leg can be defined by one control signal S. The two 16

II.2 Voltage Source Inverter basic concept

(a) scheme

(b) averaged model

Figure II.2: Base structure of a Voltage Source Inverter (VSI). switches of a leg are usually defined as commutation cell. The following convention is considered: S = 0 −→ v10 = 0 S = 1 −→ v10 = Vdc

(II.1)

where: v10 pole voltage (difference of potential between the points 1 and 0); Vdc dc-link voltage. Therefore, considering switches to be ideal, the leg output voltage does not depend on the load current direction and can be yield as: v10 = S · Vdc

(II.2)

The averaged model of a VSI leg is depicted in fig. II.2(b). The current generator S · I1 and the voltage generator S · Vdc represent the contribute introduced by the phase on the dc-link current Idc and on the ac-side voltage v10 , respectively.

II.2.1

Real behavior

The non-linearity of VSI causes the increasing of harmonic distortion and losses in the fundamental voltage waveforms [21]. The non-linear characteristics of VSI are mainly due to dead-time on the switching signals, but also to the turn-on and turn-off delays, to voltage drop across power devices [22]. In order to avoid short-circuits during the commutations, due to the finite turnoff time of power devices, it is necessary to introduce for each leg a time delay (dead-time) on the switch-on command of the power devices, as show in fig. II.3. In details, S ’+ and S ’- represent the switching signals of the up and down switch of the leg including the dead-time delay. During the dead-time, both switches 17


of the leg are turned off and the output voltage depends on the conductions of the freewheeling diodes. In particular, if the load current is flowing through the switch at the turn-on command, the dead-time causes an error on the output voltage; otherwise, if the current is flowing into the freewheeling diode at the time of the turn-on command, the dead-time has no effect on the output voltage waveform, as shown in fig. II.3. Thus, the output voltage results different from the control signals introducing a voltage error. ∆v10 can be evaluated over the modulation period Ts by means of the real pole voltage (v10 ) and the ideal one ∗ (v10 ) as following: Z Ts 1 ∗ (v10 − v10 )dt (II.3) ∆v10 = Ts 0 Moreover, taking into account the effects due to dead-time (Td ), turn-on and turnoff delays (Ton and Toff ) and saturation voltage of active switch Vs and forward voltage of anti-parallel diode Vd , the voltage error can expressed in the following equations [23]: Td + Ton − Toff Vs − Vd ¯ * Vs + Vd (Vdc − Vs + Vd ) + V10 + Ts Vdc 2 Td + Ton − Toff Vs − Vd ¯ * Vs + Vd =− (Vdc − Vs + Vd ) + V10 − Ts Vdc 2 (II.4)

i1 > 0 → ∆v10 = i1 < 0 → ∆v10

* where V¯10 is the average value of the ideal pole voltage over the modulation period Ts . Thus, voltage duty cycle variation and output voltage drop, due to non-ideal behaviour of the VSI, lead to the total voltage distortion according to fig. II.3. The voltage distortion increases with the switching frequency increasing and introduces harmonic components on the current spectrum. Compensation schemes can be implemented to eliminate these adverse influences (§III.7.4).

II.3

Three-phase Voltage Source Inverter mathematical model

Three-phase two-level Voltage Source Inverter (VSI) is still one of the most adopted topology of power converter. A VSI is composed by three legs, one for each phase, arranged by two fully-controlled power semiconductor devices equipped with related free-wheeling diodes. The structure of a VSI is depicted in fig. II.1 a). The electric state of a three-phase VSI can be identified by means of three bits correlated to the control signals. Since each output terminal can only assume two voltage values (0, Vdc ), the standard VSI is named two-level. Moreover, power semiconductor devices have a turn-off time greater than the turn-on one, thus, to avoid a short-circuit of the power supply during the switching time, a dead-time 18

II.3 Three-phase Voltage Source Inverter mathematical model

Figure II.3: Non-linearity effect on the pole voltage of a VSI. on each leg is necessary to ensure that the turn-on happens when the turn-off is effectively finish. A delay-time circuit is considered with the aim to delay the turn-on of the switches. During the dead-time, both switches of the leg are turned off; thus the output voltage depends on the conductions of the freewheeling diode. The real VSI, thus, has a non-linear characteristics, mainly due to dead-time of the switching signals, but also to the turn-on/off delays, to voltage drop across power devices. However, for the discussion the behaviour of the ideal VSI is considered, while the analysis of a real VSI can be easily carried out by means of the principle reported in §II.2.1. The pole voltages vi0 , with i=1, 2 and 3, are directly correlated to the state of the switches of the i-th leg, as shown in Tab. II.1. Thus, knowing the control signals of the three up switches, the state of the conversion system is unequivocally defined by means of an array of three bits (S1 , S2 , S3 ). By means of the Kirchhoff’s law, the phase voltage vin , with i=1, 2 and 3, can be defined as the sum of the pole voltage vi0 and the voltage v0n , as follows:    v1n = v10 + v0n (II.5) v2n = v20 + v0n   v3n = v30 + v0n Taking into account the star connection of the load and considering a symmetrical 19


0

Vdc

v10

S1 =0 (S1+ =0, S1- =1)

S1 =1 (S1+ =1, S1- =0)

v20

S2 =0 (S2+ =0, S2- =1)

S2 =1 (S2+ =1, S2- =0)

v30

S3 =0 (S3+ =0, S3- =1)

S3 =1 (S3+ =1, S3- =0)

Table II.1: Pole voltages of a VSI load, the following relation is verified between the phase voltages: v1n + v2n + v3n = 0

(II.6)

Thus, v0n is obtained substituting into eq. II.6 the set of eq.s II.5 v0n =

1 (v10 + v20 + v30 ) 3

(II.7)

Therefore, the phase voltages are defined as function of the pole voltages, as following:      v1n 2 −1 −1 v10 2 v2n  = −1 2 −1 v20  (II.8) 3 −1 −1 2 v30 v3n Considering the relations between the pole voltages and the gate signal expressed in eq. II.1 and Tab. II.1, the following equation is obtained:      2 −1 −1 S1 v1n 2 v2n  = Vdc −1 2 −1 S2  (II.9) 3 −1 −1 2 S3 v3n The phase to phase voltages are defined as difference of the phase voltages, but also of the pole voltages, as shown in eq. II.10.    v12 = v1n + v2n = v10 + v20 (II.10) v23 = v2n + v3n = v20 + v30   v31 = v3n + v1n = v30 + v10 By means of the definition of space vector (A.1 in §A), the three-phase voltage system of a VSI is represented as follows [24]: v=

2 4 2 (v1n + v2n ej 3 π + v3n ej 3 π ) 3

(II.11)

Using eq.s II.5 and II.6, the space vector of the output voltage of a VSI can be also written: 2 4 2 v = (v10 + v20 ej 3 π + v30 ej 3 π ) (II.12) 3 20

II.3 Three-phase Voltage Source Inverter mathematical model

S1

S2

S3

v10

v20

v30

v

v0

0

0

0

0

0

0

0

v1

1

0

0

Vdc

0

0

2 V 3 dc

v2

1

1

0

Vdc

Vdc

0

1 2 V ej 3 π 3 dc

v3

0

1

0

0

Vdc

0

2 2 V ej 3 π 3 dc

v4

0

1

1

0

Vdc

Vdc

− 32 Vdc

v5

0

0

1

0

0

Vdc

4 2 V ej 3 π 3 dc

v6

1

0

1

Vdc

0

Vdc

5 2 V ej 3 π 3 dc

v7

1

1

1

Vdc

Vdc

Vdc

0

Table II.2: Configurations of a standard VSI. Thus, taking into account the definition of pole voltage (eq. II.1), v=

2 4 2 Vdc (S1 + S2 ej 3 π + S3 ej 3 π ) 3

(II.13)

On the basis of the state of the VSI (S1 , S2 , S3 ) and the dc-link voltage value, the output voltage space vector is obtained and the commutation function can be also defined as following: fc =

4 2 2 (S1 + S2 ej 3 π + S3 ej 3 π ) 3

(II.14)

The commutation function associates to the VSI state a space vector of unit magnitude, while the phase is function of the considerate configuration. The output voltage space vector is easy defined as: v = Vdc fc

(II.15)

The admissible configurations of a VSI (N ) are finite and equal to: N = 23 = 8

(II.16)

where the number 2 represents the admissible state of each leg and 3 the number of legs. The N configurations are collected in Tab. II.2 and represented on the Gauss plot in fig. II.4. The voltage space vectors of a VSI describe a hexagon, its vertices are six active vectors of amplitude equal to 32 Vdc with a phase shifting of 60°. At the centre of the hexagon, the two zero vectors (v0 and v7 ) are placed. The Gauss plot is divided by the voltage space vectors into six sectors and the commutation function fc describes the hexagon with normalized amplitude. 21


Figure II.4: Output voltage space vectors of a standard VSI.

II.3.1

Averaged mathematical model for Voltage Source Inverter

The averaged model of a three-phase VSI is depicted in fig. II.5, assuming the absence of the zero-sequence component and taking into account fig. II.2(b) [25]. In details, considering a balanced load and the steady-state condition, the circulating current is zero and each phase leg can be split into two contributes: − Si · Ii : the current generator represents the contribute introduced by the i-th phase on the dc-link current Idc ; − Si · Vdc : the voltage generator represents the contribute introduced by the i-th phase on the ac-side voltage vi0 . If a non-balanced load is introduced, the averaged circulating current (I0 ) is nonzero at the steady-state and it is function of the averaged phase currents (I1 , I2 , I3 ), as shown in the following equation: I0 = I1 + I2 + I3

(II.17)

Since, modulation technique for VSI are usually characterized by triple harmonics, it is possible to define the zero-sequence duty-cycle (S0 ) as: S0 = S1 + S2 + S3 Thus, eq. II.18 can be written as: S0 S0 S0 + S2 , + S3 , =0 S1 , 3 3 3 22

(II.18)

(II.19)

II.4 Modulation techniques

Figure II.5: Averaged model of a three-phase Voltage Source Inverter. and, taking into account the zero-sequence contribute, new duty-cycles are obtained: 0 0 0 S1 + S2 + S3 = 0 (II.20) where: S0 3 0 S0 S2 = S2 , 3 0 S0 S3 = S3 , 3 0

S1 = S1 ,

(II.21)

Therefore, the zero-sequence effect is represented by means of: − −

II.4

S 0 I0 3 : current generator impacting on the dc-side current; S0 Vdc 3 : voltage generator impacting on the ac-side voltage.

Modulation techniques

A power electronic converter controls the power flow between source and load. The control strategy commands the behaviour of the converter acting on the switches by means of a modulation technique. The wide diffusion of VSI causes a considerable research activity in the field of VSI modulation technique. Thus a large variety of modulation technique has been presented in literature [20, 24, 26–32], which is characterized by different methods, concepts and performance. The selection of different modulation techniques depends on the rated power, the converter topology, the switching frequency, the semiconductor devices and the application. Thus, the dynamic performance of a power electronic converter are mainly due to the switching frequency and to the modulation technique. On the basis of switching mode operation, the modulation strategies are usually divided into two classes [26]: 23


Figure II.6: Averaged model of a three-phase Voltage Source Inverter with nonbalanced load. − open-loop control ; − closed-loop control. Open-loop control carries out the commutation pattern starting from the voltage control reference. The switched voltage space vector is generated by means of a control algorithm and it provides a fundamental voltage equal to the reference one. Open loop technologies are, for example: − Square-Wave Modulation technique, − Carried-Based Pulse Width Modulation technique (CBPWM), − Space Vector Modulation technique (SVM); Closed-loop control regulates the control reference injecting the current into the system and using a tolerance band. In details, in this category there are: − Hysteresis current control, − Sub-oscillation current control − Predictive current control. In the following sections, these modulation techniques are presented for threephase Voltage Source Inverter.

II.4.1

Square-wave modulation technique

Square-wave operation, called also six-step modulation, for three-phase Voltage Source Inverter is a simple modulation technique based on controlling the switches in such a way to obtain the desired output frequency, while the magnitude of the output voltage is regulated varying the amplitude of the dc-link. In square-wave 24


operation, VSI is modulated each π/6 considering the 6 active voltage space vectors applied with the sequence v1 - v2 - v3 - v4 - v5 - v6 . Each switch is modulated “on” for 180°, having a duty ratio of 50%, thus at each instant three switches are “on”. Since, each switch is modulated with the desired output frequency (f ), the modulation time Ts is: 1 Ts = (II.22) f The dc-link voltage has to be controlled to obtain the desired voltage magnitude. Fig. II.7(a) shows the switches state, the pole voltage and the phase voltage of each phase. The output voltage is characterized by a fundamental RMS line-toline voltage VLL,RMS function of the dc-link voltage, as shown in the following equation, r 3 4 VLL,RMS = Vdc ≈ 0.78Vdc (II.23) 2 2π and by a considerable harmonic contribute. In detail, the harmonic RMS line-toline voltage VLL,h is also function of the harmonic order h, VLL,h ≈

0.78 Vdc h

(II.24)

(with n = 1, 2, 3, ...)

(II.25)

where h = 6n ± 1

Figure II.7(b) shows the harmonics contribute of the six-step modulation achieved by means of Fourier analysis. As shown later on, the output voltage obtained with a six-step modulation is the highest value that it is possible to carry out from a VSI.

II.4.2

Carried-based Pulse Width Modulation

The drawback of the six-step modulation is the necessity to change the dclink voltage for obtaining the desired magnitude of the output voltage. Thus, Pulse Width Modulation (PWM) carries out the desired output voltage in terms of frequency and magnitude, using a VSI with constant dc-link voltage. It is clear that the switching frequency of the devices is higher than the desired output one with this technique. Carried-based Pulse Width Modulation (CB-PWM) is the most common method for pulse width modulation [26]. During a sub-cycle Ts , the control signal of each leg is generated comparing a sine wave vcontr (having the same frequency of the reference fundamental voltage) with a triangular waveform vtri (carrier, having higher frequency). For the considered case the modulation is called Sinusoidal Pulse Width Modulation (SPWM). Since PWM is widely used, there are a lot of different versions as shown in [20] having different carrier characteristics. The features of these two waveforms are correlated by means of two indexes: 25


(a) output waveforms

(b) Fourier analysis

Figure II.7: Square-wave modulation. − amplitude modulation ratio ma ; − frequency modulation ratio mf . The amplitude modulation ratio ma is defined as: ma =

Vbcontr Vbtri

(II.26)

where Vbcontr and Vbtri are respectively the peak amplitude of the control signal and of the triangular waveform. The frequency modulation ratio mf is: mf =

ftri fcontr

(II.27)

where fcontr and ftri are respectively the frequency of the control signal and of the triangular waveform. While the amplitude modulation ratio can be chosen higher than one, the frequency modulation ratio has to respect the following relation: ftri ≥ fcontr 26

(II.28)


in fact the fcontr represents the desired output frequency f , while ftri is the switching frequency of the devices. The switching state of the generic leg i is controlled by means a comparison of vcontr,i and vtri , in particular: vcontr,i ≥ vtri −→ S = 1 −→ vi0 = Vdc vcontr,i ≤ vtri −→ S = 0 −→ vi0 = 0

(II.29)

Moreover, the number of sine-wave depends on the phases number of the power converter, while, in general, the triangular waveform is unique for a converter. Figure II.8 shows the switching instants of power devices for three-phase VSI with SPWM technique, generated by comparing the common carrier signal vtri with * * * three reference sinusoidal signals (vcontr,1 , vcontr,2 , vcontr,3 ), moved in phase of 2/3π. From Fourier analysis, the ac line-to-line outputs have fundamental component at fcontr and voltage harmonics that are placed around the switching frequency ftri and multiples of switching frequency. In the case of ma ≤ 1, SPWM operates in linear range, in fact, the amplitude of the fundamental component varies linearly with ma : √ 6 ma Vdc ≈ 0.612Vdc (II.30) VLL,RMS = 2 The operation mode in which the modulation index is major than 1 is called overmodulation region. In this region, low harmonics appear in the spectrum and the relation between the amplitude of fundamental component and modulation index is not linear. Moreover, PWM with third harmonic injection,for a given dc-link voltage, leads to higher line side voltage compared SPWM.

II.4.3

Space Vector Modulation

Space Vector Modulation (SVM) is based on space vector representation of the VSI. In general, knowing the connection between the switching pattern and the phase voltage of a VSI (§II.3), the reference voltage space vector v* is generally not one of the admissible configurations of an inverter (Tab. II.2). Thus, to obtain the desired output, it is necessary to switch between two or more configurations. Contrary to CBPWM, in the SVM there is not separate modulators for each phase. Space Vector Modulation controls the inverter configuration during the modulation period Ts in such a way to obtain an average voltage space vector equal to the desired one [33]. The reference voltage space vector v* of a VSI can be expressed as follows: v* = V * ejγ where: V * amplitude of the voltage space vector; γ phase of the voltage space vector in Gauss plot (with γ(0, 2π)). 27

(II.31)


Figure II.8: PWM concept. Starting from the phase γ, the sector, in witch v* is placed, can be identify and labeled with k. To minimize the harmonics distortion, during the modulation period Ts a linear combination of the VSI space vector vk , vk+1 and v0 /v7 is applied through the weighs αk , αk+1 and α0 [24]. As shown in fig. II.9(a) the considered VSI active space vectors are the ones on the bordering of the sector. Inside the Ts the vector vk is applied for a duration of αk Ts , the vector vk+1 for αk+1 Ts and the vector v0 for α0 Ts , thus: αk + αk+1 + α0 = 1

(II.32)

Using this technique, the reference voltage space vector v* can be obtained by means of the average of the space vectors under a modulation period, as shown in the following equation: ! Z Ts Z α k Ts Z αk Ts +αk+1 Ts 1 * vk dt + vk+1 dt + v0 dt (II.33) v = Ts 0 αk Ts αk Ts +αk+1 Ts Taking into account that the space vectors vk and vk+1 can be considered constant in modulation period and that v0 is zero, the equation is easily solved: 1 (vk αk Ts + vk+1 αk+1 Ts ) Ts = vk αk + vk+1 αk+1

v* =

28

(II.34)


(a) Gauss plot

(b) sapling time distribution

Figure II.9: Space Vector Modulation concept. The distribution of the space vectors in the modulation time is depicted in fig. II.9(b). The application times αk and αk+1 are calculated thought the components of v* in the directions of vk and vk+1 respectively. In detail, π √ V* −β αk = 3 sin Vdc 3 (II.35) √ V* αk+1 = 3 sin (β) Vdc where β is the phase of the reference voltage space vector referred to the k-th sector. These two parameters give information about the v* position in the Gauss plot, while the α0 is related to the magnitude of the vector and it is carried out as following: α0 = αk + αk+1 (II.36) By means of eq.s II.35 and II.36, the VSI output domain is defined forcing α0 =0 and considering the following equation: π √ V* sin +β =1 (II.37) αk + αk+1 = 1 −→ 3 Vdc 3 Moreover, using a SVM it is possible to obtain all the space vectors included into the hexagon that respect the eq. II.37, but only in the circumference inscribed in that hexagon the SVM has a linear behavior. The radius of that circumference is equal to: π √3 2 Vdc sin = Vdc ≈ 0.5774 · Vdc (II.38) 3 6 3 Figure II.10 shows the SVM domain. The amplitude of the line-to-line fundamental component is carried out by the following equation: r √ 3 3 VLL,RMS = Vdc ≈ 0.703 · Vdc (II.39) 2 3 29


Figure II.10: SVM domain.

II.4.3.1

Switching sequences

The placement of the VSI vectors in the switching interval is not univocal and defined in the SVM technique (eq. II.33). This degree of freedom, based on the choice of the switching pattern, leads to different current ripple waveforms [20, 34–36]. In [34] an analysis of the switching sequences, with respect to the zero-voltage space vector placement into the switching interval is presented. It evaluates the performance of different patterns in terms of current ripple shape and current harmonic content. In particular, considering the same duty-cycle and the same switching frequency, the current ripple for different pulse placement is showed in fig. II.11. It is clear that the current ripple in II.11(a) has the same RMS of the one in fig. II.11(b), but with zero average value. This figures shows the classical definitions of symmetrical modulation and asymmetrical modulation. In [35] an analytical explanation of the effects of placement of the zero-voltage space vector is presented. An optimization of the current ripple RMS during the fundamental period can be achieved performing a suitable zero-voltage space vector placement. Voltage vector sequences based on symmetrical modulation ensure that only one inverter leg commutates when voltage vector that has to be applied changes, thus each leg commutates once into each modulation interval, as shown in fig. II.12 (reference is made to sector I). The zero-voltage space vector is divided into three ap30


(a) symmetrical modulation

(b) asymmetrical modulation

Figure II.11: Placement of active voltage pulses within carrier interval.

Figure II.12: Switching pattern of symmetrical modulation. plication intervals and both v0 and v7 vectors are used. There are some mutations of the symmetrical modulation, such as the two-phase modulation techniques [20]. In this category there is the Discontinuous Pulse Width Modulation (DPWM) with additional Zero Sequence Signal (ZSS). Two-phase modulation methods are based on the idea that each 60° only two phases are switched. Thus, each 60° one phase is “clamped” to low or up value of the dc-link voltage. That allows reducing the switching frequency to 2/3 with respect to a symmetrical modulation as shown in fig.s II.13. In particular, two solution are available applying the v0 vector (fig. II.13(a)) or v7 vector (fig. II.13(b)). The admissible switching patterns obtained splitting the non-zero-voltage space vector are investigated in [36]. Under the hypothesis that only one phase must be switched for a state, with a maximum number of three in half of the modulation interval, all the possible switching sequences for the SVM technique are reported in fig. II.14. In details, with reference to sector I, several symmetrical sequences are obtained and can be divided into: − conventional sequences: (0127 - 7210); − special sequences: (0121 - 1210), (1012 - 2101), (2721, 1272) and (7212 2127). There are also other sequences in which only two phases are switched each 60°, called clamping sequence, characterized by a Discontinuous Pulse Width Modula31


(a) sequence (012 - 210)

(b) sequence (127 - 721)

Figure II.13: Switching pattern of two-phase modulation. tion (DPWM). This technique allows reducing the power losses. In details these sequences are characterized by the followings patterns divided into: − symmetrical sequences: (012 - 210) and (127 - 721); − asymmetrical sequences: (012), (210), (721) and (127). Moreover, a combination of the two modulation patterns is depicted in fig. II.15, and in the following chapter labeled with clamped sequence. As example, with reference to sector I, adopted modulation pattern is 7-2-1-2-7, for the former 30° of the sector, and 0-1-2-1-0 for the latter 30°. II.4.3.2

Comparison

In previous sections it was showed that SVM allows obtaining higher values of the maximum reached voltage space vector in the linear operation with respect to SPWM. In details, a comparison between the amplitude of the line-to-line fundamental component evaluated for different modulation techniques is shown in fig. II.16. In [33] an accurate comparison between the harmonics content of SVM and PWM is reported.

II.4.4

Hysteresis control

Hysteresis control determines the switching state of each leg by means of the error between the reference and the actual phase current [26]. The control scheme is depicted in fig. II.17. In details, three hysteresis controllers carry out the switching signal of the i-th leg starting from the phase current error and the hysteresis band (b). The following set of equations is taken into account: ( if (i*i − ii ) > b −→ Si = 0 with i = 1, 2, 3 (II.40) if (i*i − ii ) < b −→ Si = 1 32


Figure II.14: Switching sequence combinations with reference to sector I [36].

This control method has a very simple structure and high dynamic performance. Its drawback is no-constant switching frequency. In fact, it depends on the bandwidth and on the current waveform, as depicted in fig. II.18. High quality current is achieved when small bandwidth is adopted, but it leads an high switching frequency. An other disadvantage is due to the sub-harmonics presence. Moreover, there is no interconnection between the three phase controllers, thus some out-ofbands are find considering that:

i1 + i2 + i3 = 0

(II.41)

The usage of hysteresis control is usually limited to low power applications. 33


Figure II.15: Clamping sequence.

Figure II.16: Operating region for different modulation techniques.

II.4.5

Sub-oscillation current control

The drawbacks of hysteresis control can be limited using a PI control structure that allows reducing the error between the phase current reference (i*i ) and the actual one (ii ) by means of a proportional and an integral action. The obtained voltage reference space vector (v* ) is implemented by means of a CBPWM or a SVM technique, that is subordinated to the current closed-loop. The combination of PWM and current control makes benefits on the current harmonic distortion and a constant switching frequency is obtained. The nonzero error at the steady-state is a disadvantage of this control. 34


Figure II.17: Hysteresis control scheme.

Figure II.18: Current behavior of the hysteresis control.

II.4.6

Predictive current control

Predictive current control allows reducing the effects of the non-zero current error at the steady-state by means of a vectorial control [31, 32]. With reference to fig. II.20, the power conversion system can be represented by the following set of equations:  v − L d i − v = 0 g f dt (II.42)  v = Vdc f where: vg i v f Lf Vdc

grid voltage space vector; grid current space vector; voltage space vector of inverter; space vector commutating function of inverter; inverter output inductance; dc-link voltage of inverter.

Starting from the current reference space vector i* , the predictive control has been implemented as depicted in fig. II.21. In particular, considering that Ts represents 35


Figure II.19: Sub-oscillation current control scheme.

Figure II.20: Power conversion system model. the sampling interval and the superscripts “m” indicates quantities evaluated at the m-th sampling time, the current reference space vector, i∗(m+1)Ts , is compared to the actual current space vector, imTs . The voltage reference space vector, v∗mTs , is obtained as follows: Lf ∗(m+1)Ts v∗mTs = i − imTs − vgmTs (II.43) Ts The obtained voltage reference space vector (v∗mTs ) can be realized by means of a CBPWM or a SVM technique, that is subordinated and synchronized to the current closed-loop. Considering a SVM, the commutating functions f ∗mTs can be basically evaluated as follows: Lf ∗(m+1)Ts 1 mTs mTs ∗mTs i −i − vg (II.44) f = Vdc Ts High performance are achieved with this closed-loop control scheme thanks to a feed-forward effect, obtained by including the current reference space vector at the (m + 1)-th sampling time and the e.m.f. voltage vgmTs . Moreover, predictive controls have an important disadvantage due to the dependence with the parameters variation. 36

II.5 Total Harmonics Distortion evaluation

Figure II.21: Predictive control scheme.

II.5

Total Harmonics Distortion evaluation

The analysis of the spectral propriety of the waveforms produced by power converters is an important aspect to take into account. Fourier theory (§I.4.1) is usually employed to evaluate the harmonic spectrum of periodic waveform, such as PWM output current/voltage and dead-time effects. It could be convenient to compare different systems by means of an overall factor rather than the individual harmonic value. The Total Harmonics Distortion (THD) factor, defined in eq. I.13, is widely used in power electronics. The THD of a converter output current or voltage waveform is correlated to the switching frequency and to the adopted modulation technique (as shown in previous sections). In [29] an analytical analysis is presented to demonstrate the dependence of the current harmonics on the amplitude and phase of the reference voltage space vector, the adopted VSI switching vectors and the switching pattern. In literature, starting from the system parameters and the SVM switching pattern, there are several methods for the current THD factor calculation. In particular, the methods can be divided into two classes, frequency domain analysis and time domain analysis. The former method is based on the Fourier analysis, while the latter one integrates the instantaneous voltage error. Considering a three-phase two-levels voltage source inverter with a SVM, the current ripple depends on the error between the instantaneous space vector output voltage (one of the 8 space vectors output voltage of a VSI) and the reference voltage space vector. In [36, 37], the RMS current ripple is carried out computing the RMS “stator flux ripple vector”, obtained by means of the time-integral over a subcycle of the instantaneous voltage error space vector. A closed-form expression of the current THD has been achieved, but the estimation method depends on the switching pattern. A general time domain analysis is based on the reconstruction of the current ripple trajectory [35, 38, 39]. Starting from the differential eq. II.42 and the model depicted in fig. II.20, the instantaneous current space vector (i(t)) during the m-th 37


sampling time can be expressed as: Z t 1 i(t) = (v − vg ) dτ Lf 0

0 ≤ t ≤ Ts

(II.45)

In general, the instantaneous voltage space vector v of VSI is equal to the sum of a fundamental component (v) and a ripple component (e v). The average value of the ripple component over Ts is equal to zero thanks to SVM. Moreover, assuming that the grid voltage space vector has only fundamental component, the (IV.8) becomes: Z t Z t 1 1 (v − vg ) dτ + (e v) dτ i(t) = Lf 0 Lf 0 0 ≤ t ≤ Ts (II.46) e = i(t) + i(t) Therefore, the fundamental component of current (i(t)) is the result of the fundamental component of voltage, while the current ripple component (ei(t)) depends on the voltage ripple component. It should be noted that the average value of ei(t) is function of the adopted modulation technique, whereas the average value of the voltage ripple is always equal to zero. In the case of the symmetrical SVM the average value of the current ripple over Ts is equal to zero, whereas in the case of an asymmetrical SVM it is not equal to zero (fig. II.11). The current ripple space vector can be evaluated over Ts with the following equation: Z t ei(t) = 1 e dτ = v Lf 0 0 ≤ t ≤ Ts (II.47) Z t 1 = (v − v(t)) dτ Lf 0 The THD can be yield as follows: T HD =

∆iRMS iRMS

(II.48)

where ∆iRMS and iRMS are respectively the RMS value of the ripple and the RMS value of the fundamental of the phase current.

38

Chapter III

High efficiency DC/AC power converters In the last few years, new power converter topologies have been introduced as alternative in high power and medium voltage applications. These new topologies allow ensuring both high conversion efficiency and high quality of voltage and current rating. These topologies of power converters were developed to overcome the power semiconductor limits in terms of voltage and current. The basic concept is based on the series/parallel connection of switches and dc voltage source to perform a staircase of voltage waveform. Capacitors, batteries, and renewable energy voltage sources can be used as multiple dc voltage sources.

III.1

Introduction

The power electronics trend of the last years is focused on increasing the power rating, reducing the size and improving the power quality and the efficiency of power conversion systems. Thus, improvement in power semiconductor technology regards both switching characteristics and higher voltage and current rating. The increasing of switching frequency allows obtaining high power quality, but the power losses can be significant, especially for high power applications. High power applications are based on both classical power converter topology using high power semiconductor devices and new converters topology built up with mature technology of medium power semiconductor devices. The series or parallel connection of switches with the aim to achieve high voltage and high current, respectively, has serious problems in terms of voltage/current sharing, synchronization of the control, device dissimilarity [40]. Moreover, increasing the number of devices, no extra degree of freedom is obtained. In order to obtain a satisfactory conversion efficiency and taking into account power 39

CHAPTER III. High efficiency DC/AC power converters

semiconductor devices limitations, in terms of maximum switching frequency and power rating, several works are available in literature in which the reduction of the current ripple is achieved by means of an optimal design of the modulation technique and/or of new conversion structures. Power electronic converters application requires: − high efficiency; − high power density; − low harmonic content; − low weight; − small dimension; − fast operation.

III.2

Historical background

DC/AC power converters for high power applications are usually design starting from VSIs. Moreover, some new structures, such as multilevel converters, change completely the architecture of the system. They are controlled by means of traditional or custom modulation techniques. Others topologies combine more standard VSIs optimizing the conversion system performance. Multilevel converters (MLC) are based on the connection of more power semiconductor devices to obtain high voltage and/or high current power conversion systems. Applying to each switch a fraction of the total dc-link voltage/current value, multilevel converter increases the number of voltage levels achieving a more sinusoidal waveform. These structures are characterized by great advantages, in terms of current/voltage waveforms quality and electromagnetic compatibility, furthermore conversion efficiency improvements can be, also, obtained using multilevel converters with a suitable control structure. However, these new solutions show advantages but, also, several limitations. Some disadvantages are observed and correlated to the complex and expensive structures and controls with respect to classical two-level voltage source inverters. Moreover, the number of adopted power semiconductor devices and capacitors or insulated sources is huge and function of the number of levels. The first multilevel converter structure has been designed by R. H. Bajer and L. H. Bannister in 1975 [41]. The new structure was called cascade H-bridge and was obtained by means of the series connection of several H-bridge with separate dc-link sources. The output voltage is characterized by several levels depending by the number of cells put in series. Afterwards, in [42] the Neutral-Point-Clamped PWM inverter (NPC-MLC) has been presented with a proper PWM technique. The power converter topology has high efficiency and less harmonic content of the output waveforms. NPC-MLC leg is composed by the series connection of more 40

III.3 DC/AC power converters topologies

than two switches and optimal voltage sharing in gained by means of additional diodes and capacitors connected to a neutral point. Since a proper control strategy has to be adopted to control the state of charge of the capacitors. In [40] the Flying-Capacitor Multilevel structure (FC-MLC) is presented using, so called, “flying capacitor”. New configuration have emerged in [43, 44] for high power applications combining standard VSI and/or MLC. In particular, topologies based on parallel connection of standard VSIs and tandem converters (called also dual 2-level 3-phase cascade inverter ) are presented. Parallel VSIs configuration [32] is characterized by the connection of several standard two-level Voltage Source Inverters having common or isolated dc-links and connected on the ac sides by means of interphase reactor (so called current-balancer) or transformers. Controlling the VSI units with different switching patterns, a current quality improvement is obtained. Parallel connection of NPC-MLCs was presented in [45, 46]. Tandem converter, instead, is obtained connecting two two-level VSIs or MLC (having common or isolated dc-link) to an open-winding load [47]. Both configurations are affected to common-mode current circulation, thus it is recommended a galvanic isolation or a proper control strategy. Therefore, several studies are presented in literature with the aim to optimize the performance of the standard VSI. Emerging topologies like asymmetric hybrid cells and soft-switched multilevel inverters have also an important role in power electronic applications [48].

III.3

DC/AC power converters topologies

This chapter reviews the state of the art of high-efficiency DC/AC power converter structures. Several topologies are considered and analyzed with their advantages and disadvantages. Moreover, the major modulation techniques proposed in literature are reported. The traditional MLC topologies are analyzed: − diode-clamped (Neutral-Point-Clamped) (§III.4.4); − capacitor-clamped (Flying-Capacitors) (§III.4.5); − cascaded H-bridge (§III.4.6). Moreover, other structures have been presented: − tandem converter (§III.5). − parallel VSIs converter (§III.6). Finally optimization techniques for two-level VSI are studied and reported in §III.7 41


III.4

Multilevel converters

The family of multilevel converter is considered as an important alternative in power electronic applications. Multilevel converters were born for high power applications, such as traction systems, transmission lines, high-power motor drives, renewable energy. Nowadays their use is also suitable for medium-low power applications, like electrical vehicles and distributed generation, where, thanks to the waveforms quality, the improvement of the performance can be achieved.

III.4.1

Multilevel basic concept

As well known, a standard VSI is characterized by a two-level voltage, it means that the pole output voltage can assume two values: 0 and Vdc (§II.2). Figure III.1(a) shows the two-level VSI leg arranged with two ideal switches and fig. III.2(a) the pole voltage. Multilevel converters are composed by an array of power semiconductor devices, as depicted in fig. III.1. The dc-link is split in several dc portions and, during the commutations, the switches are subjected to a lower dc-link voltage. The output voltage has a stepped waveform and it is obtained with the aggregation of these dc-link voltage portions. However, the rated voltage of the power semiconductor switches depends only upon the way the dc-link voltage source is split. The structure in fig. III.1(b) generates a three-level pole voltage, in details v10 V can assume the voltage values 0, 2dc and Vdc thanks to the clamping point, as shown in fig. III.2(b). The number of obtained levels names the structure as threelevel converter. That concept can be generalized to structures with n-level (fig. III.1(c)) having a n levels pole voltage. Thus, v10 can assume the voltage values 0, (n−2)·Vdc Vdc 2·Vdc 3·Vdc and Vdc . Moreover, considering a star connection n−1 , n−1 , n−1 , ..., n−1 load, the line-to-line voltage has a number k of levels, while the phase voltage is characterized by p levels, obtained by means the following set of equations: (

k = 2n − 1 p = 2k − 1

(III.1)

For example, a 9-level converter has 9 pole voltage levels (fig. III.3(a)), 17 line-toline voltage levels (8 negative levels, 8 positive levels and the zero-level, as shown in fig. III.3(b)) and 33 phase voltage levels (fig. III.3(c)). Multilevel converter generates a high voltage quality and higher is the levels number, lower the voltage harmonic distortion and the dv/dt are. The MLC benefits are combined with a complex structure, an increasing number of devices and an elaborate control. The voltage imbalance problems of the capacitors has a key role in the control design. 42

III.4 Multilevel converters

(a) two-level inverter

(b) three-level inverter

(c) n-level inverter

Figure III.1: Multilevel concept.

(a) n=2

(b) n=3

Figure III.2: Pole voltage levels generated by an inverter with n-level expressed in [kV] [49].

III.4.2

Multilevel converter mathematical model

The mathematical model, reported in §II.3 for a three-phase two-level voltage source inverter, can be generalized for a three-phase n-level converter with a star connected load [49]. A simple MLC structure is depicted in III.4. The pole voltages vi0 , with i=1, 2 and 3, are directly correlated to the state of the switches of the i-th leg, as shown in the following equation:     v10 S1 v20  = 1 Vdc S2  (III.2) n−1 v30 S3 where Si is the state of the i-th leg, with i=1, 2 and 3, that is correlated to the states of the commutation cells of the leg as described in §II.2. In details, Si can assume all the integer values in the range (0, n-1) in order to represent the voltage levels. For example, in a three-level inverter, Si can assume the values 0, 1 and 2, 43


(a) pole voltage [kV]

(b) line-to-line voltage [kV]

(c) phase voltage [kV]

Figure III.3: Voltage levels generated by an inverter with 9-level [49].

Figure III.4: General three-phase n-level inverter scheme. thus pole voltage vi0 is, respectively, 0, 21 Vdc and Vdc . Taking into account eq.s II.5, the phase voltages vin , with i=1, 2 and 3, are directly obtained from the pole voltages as shown in eq. II.8. Thus, starting from space vector definition (eq. A.1 in §A), the output voltage space vector of a multilevel converter is obtained: v=

III.4.3

2 4 2 Vdc (S1 + S2 ej 3 π + S3 ej 3 π ) 3n−1

(III.3)

Multilevel converter redundant states

Multilevel converter leg has a number of switching states (ns ) that is function of the number n of levels and of the number of phases. Thus, considering a threephase MLC, the switching state is yield as following: ns = n3 44

(III.4)


(a) n=2

(b) n=3

(c) n=5

Figure III.5: Voltage space vector generated by an inverter with n-level [49]. Two or more switching states can carry out the same voltage space vector, so they are called redundant states. Different switching states may have different effects on the sources or on the converter components also if they carry out the same voltage space vector. Thus, redundant states generate a degree of freedom in multilevel converter and they are usually adopted to optimize the converter performance. For instance, redundant vectors are used in diode-clamped converter to balance the voltage level of dc capacitors or to reduce the conversion losses. In spite of the redundant states depend on the number of converter admissible configurations and the architecture, a n-level converter has a number of output voltage space vector (nv ) that is only function of the number n of levels (fig. III.5), and it is carried out by: nv = 3n · (n − 1) + 1 (III.5) Figure III.5 demonstrates that increasing the number n of levels, the resolution of the admissible voltage space vectors increases obtaining in this way a high voltage quality similar to a sine-wave. The number of redundant states (nr ) of a specific voltage space vector, is obtained by means of the related switching state (S1 , S2 , S3 ), as following [49]: nr = n − (Smax − Smin ) (III.6) where Smax and Smin are the maximum and the minimum values of the related switching state: ( Smax = max(S1 , S2 , S3 ) (III.7) Smin = min(S1 , S2 , S3 ) Two different kinds of redundant states are defined on the basis of the number of phases that they involves. In particular, joint-phase redundancy involves all the three phases, while intra-phase redundancy is referred to one phase.

III.4.4

Diode-Clamped multilevel converter

The diode-clamped converter provides multiple voltage levels through the connection of the phases to a series bank of capacitors by means of clamped diode [42]. 45


(a) n=3

(b) n=5

Figure III.6: Diode-Clamped multilevel converter with n-level.

Figure III.6(a) shows one leg structure of the three-level diode-clamped converter, where two capacitors are connected across the dc-link capacitor resulting in one additional level thanks to the clamping diode. The additional level is the neutral point of the dc-link, so this topology is also called Neutral-Point-Clamped (NPC) inverter. By increasing the number of capacitors it is possible to increase the number of levels, as shown in fig. III.6(b), but to access to the neutral point only even numbers of capacitors are admissible. Otherwise, if odd numbers are considered the structure is called Multiple-Point-Clamped (MPC) inverter. Thus, in diode-clamped inverter the dc-link is split into equal steps by capacitors bank. The balancing of the voltage across the capacitors is an important issues for NPC-MLC and a huge amount of works are available in literature regarding this problem. In this section the description is limited to three-levels diode-clamped multilevel converter, but it can be easy enlarged to a number n of levels. Three-level diode-clamped multilevel converter (fig. III.6(a)) includes two addiV tional capacitors (C1 and C2 ) charged to 2dc to obtain the neutral point N, in this way the dc-link voltage is split into three levels. The structure consists of 0 0 four fully-controlled power semiconductor devices (T1 , T1 , T2 , T2 ) and two diodes (D1 and D2 ), so called clamping diodes. In this converter structure, switches V and diodes block a voltage equal to 2dc . Considering a n-level structure, these Vdc switches have to block n−1 while the reverse voltage blocked by the diodes is equal 46


0

0

S1

T1

T1

T2

T2

v10

0

0

0

1

1

0

1

0

1

1

0

Vdc 2

0

v1N -

Vdc 2

2

1

1

0

0

Vdc

Vdc 2

-

1

0

0

1

undef ined

undef ined

Table III.1: Switching states of a three-level NPC-MLC (n−2)·V

dc [48]. It is easy to understand how, increasing the number n of levels, to n−1 the block voltage decreases. Moreover, the diodes number works out by means of (n-1) · (n-2). As described in §II.2, in order to avoid short-circuit of the dc-link, not all the available combinations of the switches are admissible. Thus, two commutation 0 0 cells (T1 - T1 , T2 - T2 ) have to be considered in the leg and the switches of the commutation cell have to be controlled as complementary pair. Thus, the i-th commutation cell can be controlled by means a single switching signal Ti , that represents the switching state of the first element of the cell. The switching state Sj of the j-th leg works out from the following equation:

Sj =

n−1 X

Ti

(III.8)

i=1

The node 1-phase can be connected to any nodes of the bus by means of the diodes. The behaviour of the NPC-MLC leg is described in tab. III.1 in terms of leg switching state S1 , devices state, pole voltage v10 and potential of the phase node with respect to the neutral point v1N . Of course, ideal power semiconductor devices are considered and the effect of the dead-time is neglected. In the case of real devices, the description reported in §II.2.1 may be easily extended for multilevel converter. The table shows that not all the configurations lead to a defined output voltage, but a configuration output depends on the load current direction. Moreover, for the considered topology there are no intra-phase redundancies, but only joint-phase redundancies. The equalization of the capacitors voltage has a key role for diode-clamped technology, in fact it can lead the converter performance. Basically, the regulation of the capacitor state of charge can be achieved if the average current in each capacitor is equal to zero. Of course, the voltage value of the capacitors depends on the modulation pattern, thus, an additional control section is necessary to regulate the capacitors state of charge by means of an additional converters and/or an proper modulation technique that takes advantage of joint-phase redundancies. 47


(a) n=3

(b) n=5

Figure III.7: Capacitor-Clamped multilevel converter with n-level.

III.4.5

Capacitor-Clamped multilevel converter

The capacitor-clamped converter produces a multiple voltage levels connecting the phase node to a bank of capacitors [40], thus this topology is also called flying-capacitor multilevel converter (FC-MLC). This structure is similar to NPCMLC, but it presents some advantages, in terms of number of components, in fact no clamping diodes are introduced, and in terms of redundant states, in fact it provides intra-phase redundancies that can be used to balance the flying capacitors Vdc voltages. Indeed, the voltage over each capacitor has to be keep constant to n−1 and it allows to generate additional levels on the output voltage. The leg of a FC-MLC is depicted in fig. III.7(a), considering a three-level structure (n=3), and in fig. III.7(b), a five-level one is shown (n=5). Taking into account a number of levels equal to three, the structure need only one flying capacitor C3 charged to half of the dc-link voltage. Table III.2 shows the relationship between the leg switching state S1 , the devices state and the pole voltage v10 . Thus, it is possible to notice that two commutation cells are available 0 0 (T1 - T1 and T2 - T2 ) and that some configurations are not allowed to avoid the short-circuit of the clamping capacitor C3 and the dc-link source. In particular the possible configurations (Nconf ) for a n-level FC-MLC works out as follows: Nconf = 2n−1 48

(III.9)


0

0

S1

T1

T1

T2

T2

0

0

1

0

1

1 2

v10 0

0

1

1

0

1

0

0

1

Vdc 2 Vdc 2

1

0

1

0

Vdc

Table III.2: Switching states of a three-level FC-MLC For example, for a three-level FC-MLC there are 4 configurations per phase leg, while for a five-level FC-MLC , Nconf is equal to 16. As shown in tab. III.2, a three-level flying-capacitor inverter provides an intraphase redundancy, indeed there are two configurations which allow obtaining S1 =1. They can be properly selected in order to regulate the state of charge of the capacitor C3 and of the dc-link capacitors (C1 and C2 ) providing the same pole voltage. In fact, applying one of these two configurations, the charge or the discharge occurrence of the capacitors is function of the load current directions. The main disadvantages of the flying-capacitor structure is the necessity to control the state of charge of the capacitors. Thus, the degree of freedom of this structure has to be used to obtain good performance and it is not properly possible to use it to increase the overall efficiency. Moreover, the number of flying capacitors increases as the number of levels. In details, for a n-level FC-MLC a flying capacitors per phase leg in addition to (n − 1) main total of (n−1)·(n−2) 2 dc-bus capacitors are required, making the capacitors voltage balancing control complicated.

III.4.6

Cascaded H-bridge

Cascaded H-bridge consists of a cascaded connection of n basic H-bridge structures fed by n isolated dc sources [41, 50]. The topology can be easily scaled, but the increasing of the number of galvanic isolated dc sources (can be obtained by means of isolation transformers) is in general a disadvantages of this structure. Moreover, in some applications, such as photovoltaic plants and batteries bank systems, where there is easy to arrange several isolated sources, cascaded H-bridge converter is widely commercialized. The isolated sources can be substituted by capacitors for active filter applications (providing zero active power) and taking advantage of redundant states to regulate the capacitors state of charge. The base structure of the power converter is the H-bridge, called cell, depicted in 0 fig. III.8(a). Each cell is composed by two commutation cells (T1 - T1 and T2 0 T2 ), one per leg. Figure III.8(b) shows a five-level cascaded H-bridge converter. 49


(a) base unit, n=3

(b) n=5

Figure III.8: Cascaded H-bridge multilevel converter with n-level.

0

0

S1

T1

T1

T2

T2

v10

-1

0

1

1

0

−Vdc

0

0

1

1

0

1

1

0

0

0

1

0

0

1

Vdc

0 1

Table III.3: Switching states of a three-level cascaded H-bridge converter.

Table III.3 represents the possible switching states of the cell. In details, it has been characterized by a three-level voltage (−Vdc , 0, Vdc ). A three-level cascaded H-bridge inverter provides an intra-phase redundancy, indeed there are two configurations which allow obtaining S1 =0. Selecting redundant states it is possible to meet a particular goal, such as the reduction of switching losses or of the ripple of the dc source current [51]. The increasing of the number of voltage levels is obtained adding cells in cascaded, each H-bridge provides two additional levels on the output voltage. Moreover, these configuration has a modular structure, in fact it is possible to disconnect some cells switching on the upper switches or the lower ones, showing an intrinsic reliability. Thereby, cascade H-bridge was the founder of cascade converter family.

50


III.4.7

Multilevel converter modulation techniques

To take advantage of the degree of freedom of these new structures, such as the extra voltage levels of MLC, in recent years, several studies have been developed with the aim to increase their performance [49, 52, 53]. Several modulation techniques are introduced extending traditional modulation strategies to these new topologies, such as multilevel sinusoidal pulse-width modulation, multilevel selective harmonic elimination and space-vector modulation. Moreover, the modulation techniques for MLCs are more complex due to the control of power semiconductor devices with respect to standard topologies. A classification of the modulation control algorithms for multilevel converter are collected in fig. III.9 and divided in two categories regarding the operating switching frequency. In details, the control of the power flow of a converter is regulated by the commutation of the switches. The switching frequency can be chosen equal or greater than the desired fundamental component, thus, three macro-classes are identified: − low switching frequency - the switching frequency is closer to the output fundamental frequency. In this category there are: − Space Vector Control (SVC), − Selective Harmonic Elimination (SHE); − mixed switching frequency - used for converters working with cells having different switching frequencies. In this catery there is: − Hybrid multilevel modulation; − high switching frequency - these modulation are the extension of the standard PWM for MLCs. This category is divided into: − Space Vector PWM (SV-PWM), − Phase-Shifted PWM (PS-PWM), − Level-Shifted PWM (LS-PWM). In general, to achieve high quality of the converter output waveforms, high switching frequency is necessary. However conversion losses have to be taken into account to avoid conversion efficiency degradation. For a multilevel converter the overall levels of the output voltage increase thanks to the multiple switches, thus redundant states can be used to optimize the switching losses. A brief analysis of the fundamental modulation techniques for MLCs is reported in this section. III.4.7.1

Space Vector Control

The Space Vector Control (SVC), also called Nearest Vector Control is a modulation technique based on the space vector representation of power converter. In particular, starting from the reference voltage space vector (vs∗ ), the output vector 51


Figure III.9: Classification of multilevel converter modulation techniques. is chosen by means of a “minimum distance ” algorithm approximating vs∗ with the nearest voltage vector. In fig. III.10(a) the principle of SVC is shown for a 11-level MLC. The red dashed line represents the reference voltage space vector trajectory in the Gauss plot, while the gray hexagons define the area in which the matching space vector has to be applied on the basis of the “minimum distance ” algorithm. SVC allows achieving a low switching frequency and, at the same time, high performance in terms of waveform quality when the number of levels of the power converter increases [49]. III.4.7.2

Selective Harmonic Elimination modulation

Selective Harmonic Elimination (SHE) allows achieving an harmonic elimination by means of the variation of the switching signals on the basis of the Fourier analysis (§I.4.1). The number of harmonic that can be eliminated is function of the number of MLC levels. SHE is usually adopted for high power applications. Defining the n-level voltage waveform with a 2n − 1 number of switching angles, the off-line algorithm carries out the values of the switching angles to obtain a low-order harmonics elimination [53]. Figure III.10(b) shows the obtained PWM waveforms and the harmonic contents with a ratio between the switching and the fundamental frequencies equal to 11 and different switching angles. The SHE becomes more complex with the levels increasing due to the solving of the transcendental equation system. III.4.7.3

Hybrid PWM modulation

Hybrid PWM modulation chooses the switching frequency on the basis of the processed power and in the case of cascaded configuration (§III.4.6), it allows achieving high performance in terms of power quality and conversion efficiency 52


(a) SVC

(c) hybrid modulation

(e) PS-PWM

(b) SHE

(d) SV-PWM

(f) LS-PWM

Figure III.10: Multilevel modulation techniques concept [52]. 53


[53]. The cell having higher dc-link and/or processed power is modulated with low frequency; to increase the current quality, the other cell is commutated with higher switching frequency. In fig. III.10(c) the behaviour of the hybrid PWM modulation for a three-cell system with different dc-link voltage (Vdc1 < Vdc2 < Vdc3 ) is represented. In details, Cell 3, characterized by higher dc-link voltage, works with low switching frequency. At the contrary, Cell 2 and Cell 1 operate with higher switching frequencies in relation of their dc-link voltages. The output voltage looks like a traditional high-frequency multilevel modulation technique and it is possible to appreciate the contribute of each cell to the total voltage design. III.4.7.4

Space Vector Modulation

Space Vector Modulation (SV-PWM) is the extension of the SVM (§II.4.3) for MLC. This strategy allows obtaining a good-approximation of the reference voltage space vector applying during the sampling time the three vectors of the boundary of the hexagon in which the reference vector takes place [49]. The principle of this modulation strategy is depicted in fig. III.10(d) considering a three-level converter. The redundant state of the converter can be applied to increase the converter performance in terms of capacitors state of charge stabilization or efficiency increasing. III.4.7.5

Phase-shifted modulation

Phase-shifted modulation (PS-PWM) is based on pulse-width modulation, using carrier-based sine-triangular modulation technique (§II.4.2) equipped with multi-carrier in horizontal shift mode [52]. The number of carriers and their shifts are function of the number of levels n. In particular, n − 1 carriers are necessary for a n-level converter leg, one per each commutation cell. Moreover, the phase shift of the carrier is obtained as 360°/n − 1 to uniform distribute the carriers in the switching period. This modulation is widely used for FC-MLC. A five-level carrier based modulation for MLC is depicted in fig. III.10(e). It is possible to notice that four carriers and one sine-wave are necessary to obtain a five level phase voltage. The harmonic spectrum of the output waveform is characterized by a fundamental, having the frequency of the sine-wave, and the switching harmonics are placed at four times the switching frequency of each commutation cells. Thus, a strong THD reduction can be achieved. III.4.7.6

Level-shifted modulation

Level-shifted modulation (LS-PWM) uses carrier-based sine-triangular modulation technique equipped with multi-carrier in vertical shift mode [52]. The same principle expressed for PS-PWM is applied. In general, the harmonics appear with a frequency equal to n times the frequency of the carrier signal. Due to 54


the necessity to balance the state of charge of the capacitors of the structure, the effective switching frequency increases. The LS-PWM concept is shown in fig. III.10(f) where phase (a), opposite (b) and alternative opposite (c) dispositions of the carriers are depicted.

III.5

Tandem converter

A tandem converter, also called dual 2-level 3-phase cascade inverter or cascaded converter, consists of two standard two-level three-phase Voltage Source Inverters (widely discussed in Chapter II) connected to two dc voltage sources (Vdc1 and Vdc2 ), while the ac sides feed a open-phase load [47]. Figure III.11(a) shows a tandem converter with two separated dc-links, in fig.s III.11(b) and III.11(c) series and parallel configurations with common dc-link is depicted. Both configurations need additional control for the common mode currents, thus in this paragraph the solution with separate dc-links is analyzed. Cascaded converter consists in twelve fully-controlled power semiconductor devices. Since the state of two switches of each leg is complementary pair to avoid the short-circuit on the dc sources, a Tandem converter can be controlled by means of 6 bits (S1,1 , S1,2 , S1,3 , S2,1 , S2,2 , S2,3 ). By means of II.16, the number N of configurations of a cascaded converter is finite and equal to: N = 26 = 64

(III.10)

where two are the voltage levels of each leg and six is the number of legs. Moreover, some redundant states are carried out and not all the switching states generates a different load voltage space vectors, as it is analyzed in §III.5.2. This topology is able to carry out a multilevel voltage if a proper modulation technique is adopted. Moreover, it has an higher number of available states for a given number of active switches compared to MLC [47]. From point of view of output voltage space vector, this power converter topology is equivalent to a three-level or four-level converter, but it has the advantage to be composed by standard two-level VSI structure.

III.5.1

Tandem converter mathematical model

With reference to the tandem converter scheme, shown in III.11(a), the load voltage space vector v can be calculated as the potential differences between the pole voltages of the VSIs [47]. In detail, by means Kirchhoff’s law, the load phase voltage are:    v1 = v1,1 − v2,1 + v01 ,02 v2 = v1,2 − v2,2 + v01 ,02 (III.11)   v3 = v1,3 − v2,3 + v01 ,02 55


(a) separate dc-links configuration

(b) series configuration

(c) parallel configuration

Figure III.11: Tandem converter topologies.

56


where: vy vx,y v01 ,02

phase voltage of the load (with y=1, 2 and 3); pole voltage of inverter x (with x=1, 2 and 3 and y=1, 2 and 3); potential difference between the points 01 and 02 .

Considering that the dc-link sources have a galvanic isolation and a balanced load, the following relations are obtained: ( i1 + i2 + i3 = 0 (III.12) v1 + v2 + v3 = 0 By means the set of eq.s III.11 and III.12, the voltage v01 ,02 is calculated: v01 ,02 =

1 (v1,1 − v2,1 + v1,2 − v2,2 + v1,3 − v2,3 ) 3

Substituting eq. III.13 into eq. III.11, it is possible to yield:  1 1 2   v1 = (v1,1 − v2,1 ) − (v1,2 − v2,2 ) − (v1,3 − v2,3 )   3 3 3   1 2 1 v2 = − (v1,1 − v2,1 ) + (v1,2 − v2,2 ) − (v1,3 − v2,3 )  3 3 3      v3 = − 1 (v1,1 − v2,1 ) − 1 (v1,2 − v2,2 ) + 2 (v1,3 − v2,3 ) 3 3 3

(III.13)

(III.14)

Through the definition of space vector, the load space vector v (A.1) is easily defined: 2 4 2 v = (v1 + v2 ej 3 π + v3 ej 3 π ) (III.15) 3 Thus, the eq. III.16 is modified using the set of eq.s III.14, obtaining: 2 4 2 v= (v1,1 − v2,1 ) + (v1,2 − v2,2 )ej 3 π + (v1,3 − v2,3 )ej 3 π (III.16) 3 Moreover, v = v1 − v2

(III.17)

where: v1 voltage space vector of inverter 1 ; v2 voltage space vector of inverter 2 ; 2 4 2 (v1,1 + v1,2 ej 3 π + v1,3 ej 3 π ) 3 2 4 2 v2 = (v2,1 + v2,2 ej 3 π + v2,3 ej 3 π ) 3

v1 =

(III.18)

Equation III.17 can be also expressed considering the commutation function defined in eq.s II.14 and II.15 [54]: v = Vdc1 fc1 − Vdc2 fc2 57

(III.19)


where: fc1 commutation function of inverter 1 ; fc2 commutation function of inverter 2 ; 2 4 2 T11 + T12 ej 3 π + T13 ej 3 π 3 2 4 2 T21 + T22 ej 3 π + T23 ej 3 π = 3

fc1 = fc2

(III.20)

Figure III.12 shows the admissible voltage space vectors for a tandem converter with different ratio between the two dc-link voltage values, under the condition Vdc1 + Vdc2 = Vdc . Figure III.12(a) represents the case of a two-level three-phase Voltage Source Inverter because Vdc2 =0 and the inverter 2 is a star connection. When Vdc2 = 51 Vdc1 , fig. III.12(b) shows the star of a standard VSI with a small inverter patterns around each voltage space vector. Increasing the Vdc2 compared to Vdc1 the space vector star of inverter 2 becomes bigger. In details, with Vdc2 = 1 2 Vdc1 the tandem converter has the same behaviour of a four-level converter (fig. III.12(c)) and in the case of Vdc2 = Vdc1 of a three-level converter (fig. III.12(d)). In the letter two cases there are some space vectors of the two inverters that are overlapping. In details, the number of redundant states (nr ) is function of the dclink voltages values and taking into account eq. III.10 it can be yield as follows: 1 Vdc1 −→ nr = 15 5 1 Vdc2 = Vdc1 −→ nr = 27 2 Vdc2 = Vdc1 −→ nr = 45 Vdc2 =

III.5.2

(III.21)

Tandem converter redundant states

The load voltage space vector v of a tandem converter is function of the dc-link voltage values and of the switching states of inverter 1 and 2 [55]. Three operating modes are defined: − fc1 6= 0; fc2 = 0 → v=

2 Vdc1 fc1 3

(III.22)

the tandem converter generates the vectors star depicted in fig. III.13 a); − fc1 = 0; fc2 6= 0 → 2 v = − Vdc2 fc2 3

(III.23)

the tandem converter generates the vectors star depicted in fig. III.13 b); 58


(a) Vdc2 =0

(c) Vdc2 =

(b) Vdc2 =

1 V 2 dc1

1 V 5 dc1

(d) Vdc2 = Vdc1

Figure III.12: Voltage space vector of a cascade converter [47]. − fc1 6= 0; fc2 6= 0 → v=

2 2 Vdc1 fc1 − Vdc2 fc2 3 3

(III.24)

the tandem converter generates a voltage space vectors star that is function of the dc-link voltage values. In details, the output voltage space vectors are the superposition of the two voltage space vectors stars of both inverters. In this way, more configurations are available and with reference to the dc-links ratio several redundancies are highlighted. Two notable cases are presented: − Vdc1 = Vdc2 = 12 Vdc The power converter has the behaviour of a three-level converter, the 64 space vectors are distributed in the Gauss plot as depicted in fig. III.14 in accordance with 2 hexagons with amplitude: 2 2 1 2 2 Vdc1 , Vdc1 + Vdc2 = Vdc , Vdc (III.25) |v| = 3 3 3 3 3

59


a)

b)

Figure III.13: Voltage space vectors of a) inverter 1 and b) inverter 2. It is possible to discern 18 active vectors and the null vector obtained as differences between the space vectors generated by each inverter. Thus, several redundancies are find are represented in fig. III.15. − Vdc1 = 2 · Vdc2 = 32 Vdc The power converter has the behaviour of a four-level converter, the 64 space vectors are distributed in the Gauss plot as depicted in fig. III.16 in accordance with 3 hexagons with amplitude: 2 2 2 2 2 Vdc1 − Vdc2 , Vdc1 , Vdc1 + Vdc2 = |v| = 3 3 3 3 3 (III.26) 4 2 2 Vdc , Vdc , Vdc = 9 9 3 It is possible to discern 36 active vectors and the null vector obtained as differences between the space vectors generated by each inverter. As well know, redundancies of a MLC are often used to balance the state of charge of capacitors and to avoid their voltage drift. For tandem converter, dclink sources are separated and, thus, the redundancies can be used to maximize the power conversion system performance, such as minimize switching losses [55].

III.5.3

Tandem converter Modulation techniques

The two dc-link voltage levels suggest to operate with different switching frequencies of the two inverters in such a way to optimize the switching losses. In details, it is possible to suppose low switching frequency for the inverter with higher dc-link voltage and high switching frequency for the other one, with lower 60


Figure III.14: Voltage space vectors of cascaded converter with Vdc1 = Vdc2 = 1 2 Vdc .

Figure III.15: Redundancies distribution of a cascaded converter with Vdc1 = Vdc2 = 12 Vdc .

61


Figure III.16: Voltage space vectors of cascaded converter with Vdc1 = 2 · Vdc2 = 2 3 Vdc . dc-link voltage. The notable case of tandem converter, in which both inverters are characterized by the same dc-link voltage value, is often modulated with a unique switching frequency. The analyzed modulation techniques for standard VSI (§II.4) and for MLC (§III.4.7) are adapted to be used for a tandem converter. In details, the most common modulation strategies are [55]: − hysteresis control ; − mixed hysteresis-SVM control ; − Space Vector Modulation. The hysteresis control is based on the minimum distance voltage control [55]. In details, the control algorithm applies during each sampling time the voltage space vector with the minimum distance from the reference one (fig. III.17(a)). This control is preferable for power converters with an high number of levels, in fact, in this case it is also possible to obtain a strong reduction of current distortion. To better represent the desired load voltage, the output voltage can be synthesized by means of two contributes carried out by the two inverters. However, the inverters with high dc-link voltage can operate in hysteresis mode (low switching frequency) while the other one can perform a Space Vector Modulation to reduce the voltage error. This modulation techniques mixed hysteresis-SVM control 62

III.6 Parallel VSIs converter

(a) hysteresis contorl

(b) mixed hysteresis-SVM control

(c) SVM

Figure III.17: Modulation techniques for a tandem converter. allows achieving high performance in terms of current quality using a conversion system based on standard module conversion unit. Moreover, the redundant states can be used to optimize the switching frequency losses. In fig. III.17(b) the modulation concept is shown. Moreover, it is also possible to modulated each converter with a SVM and select the portion of voltage reference that each converter has to modulate on the basis of the dc-link ratio or taking into account the power amount to be performed by the dc-link sources [56]. The SVM principle for a tandem converter is depicted in fig. III.17(c).

III.6

Parallel VSIs converter

Multilevel converters represent a no-standard technology; benefits in terms of energy efficiency are usually not well balanced by the more complexity in the struc63


ture and control. Parallel connection of standard two-level VSI can represent a valid solution for high power applications or to obtain low harmonic content, but a proper control strategy has to be set-up in order to maximize the efficiency [57]. Three-phase VSIs are widely used in industrial applications, renewable systems, motor controls, distributed generations. The switching frequency of these converters has to be decreased for high power applications mainly due to switching losses; thus, large filters have to be installed to guarantee an high quality current. Parallel converters structures, based on the parallel of n standard VSIs, are considered as a interesting solution to reduce the power semiconductor device rating and to obtain an high quality current waveform. Moreover, these solutions have intrinsic reliability and redundancy, are easy to design, to manufacture and to revamp [58]. High efficiency and low harmonic content can be obtained by means of the interleaving modulation advantages. In particular, a higher apparent switching frequency at the parallel point is adopted, which is equal to n times the switching frequency of each unit. Parallel converter are used in three-phase drivers, active power filters, renewable energies, uninterruptible power supplies and fault tolerance system. The main problem of parallel VSIs connection is the presence of closed-loops between the VSI units producing current unbalancing of the converter stages and/or circulating current among the units [59]. Of course, when a synchronization of the switching signals of each leg of each unit is adopted, the circulating currents are minimized and they are only due to the intrinsic differences of the power semiconductor devices. Moreover, in this case the parallel converter degree of freedom is lost since it is used as a standard VSI with parallel connected power devices. As well know, circulating currents causes losses in the processed power, thus, several approaches have been presented in literature [25] to minimize this effect and they are analyzed in the following subsections, in details: − isolation techniques (i.e. separated dc-link sources, isolated transformer); − current-sharing reactors; − proper control techniques.

III.6.1

Parallel VSIs converter with isolation techniques

With reference to fig. III.18, the parallel converter system is arranged by means of the parallel of n units. The units are connected in parallel through n identical output filter (Lf ). An isolation of the dc source or a multi-source transformer is necessary to avoid the circulation of the currents between the n units [60–62]. In this approach, the overall parallel system is bulky and costly because of the additional power supplies or the ac line-frequency transformer. Thus, it is usually used where the galvanic isolation is already available and necessary, such as in the renewable applications or electric vehicles. For example, in a photovoltaic plants it is easy to split the photovoltaic modules to obtain isolated dc-link sources. 64


Figure III.18: Parallel converter topology with line-frequency transformer.

Moreover, for high power applications the line-frequency transformer is inserted to obtain a galvanic isolation with the grid and it is possible to introduce a multisource transformer to avoid the circulation of cross-currents. By assuming an ideal transformer, a parallel converter system can be represented by the following set of equations [4]:  dii  vg = vi − Lf    dt   vi = Vdci fi with i = 1, ..., n  n  X    ii  ig = i=1

where: vg ig vi ii fi Lf Vdci

grid voltage space vector; grid current space vector; voltage space vector of inverter i (with i=1,...,n); current space vector of inverter i (with i=1,...,n); space vector commutating function of inverter i (with i=1,...,n); inverter output inductance; dc-bus voltage of inverter i (with i=1,...,n). 65

(III.27)


Figure III.19: Parallel VSIs converter with current-sharing reactors.

III.6.2

Parallel VSIs converter with current-sharing reactors

In [45, 59, 63] a technique for parallel connection of three-phase two-level VSI by using current-sharing reactors, with common dc-link source and modulated by means of shifted-PWM is reported. The current-sharing reactor, also called coupled inductor, has a high zero-sequence impedance and allows obtaining only a prevention of the zero-sequence current, but the low-frequency circulating current has to be minimize by means other techniques [39, 64, 65]. The model of coupled inductor for parallel VSIs converter is reported in [66]. In details, fig. III.19 shows one phase-leg of a four-parallel VSIs converter (n = 4). L1 and L2 are the current-sharing reactors for currents i1 + i2 and i3 + i4 , respectively. Moreover, L3 is the current-sharing reactor for the currents i12 + i34 . The function of the reactors is to balance the shared current between the four units. For example, if the current i1 increases with respect to the current i2 , an emf reaction is generated in such a way to obtain a decreasing of i1 and an increasing of i2 . When the current balancing is achieved, no e.m.f. reaction is generated. The i-th leg of the converter is controlled by means of a CB-PWM (§II.4.2), where ∗ the carrier vtri,i , a triangular waveform, is compared to the signal control vcontr,r in order to obtain the leg switching signal, thus, the output voltage vi0 . In figures III.20, the PWM waveforms of the converter are depicted. It is possible to notice that, taking into account the standard shift 360°/n, the triangular waves are shifted by 90° from each other. This technique is called interleaving modulation and is widely discussed in §III.6.4. Thanks to the reactors effect, the output voltage vr0 works out as the mean value of the voltage of each leg, as shown in the following 66


Figure III.20: Control and output waveforms for parallel VSIs converter with current-sharing reactors. equation: vr0 =

v10 + v20 + v30 + v40 4

(III.28)

∗ The value of the fundamental component of vr0 is given by means of vcontr,r , whereas the harmonic content is reduced thanks to the interleaving modulation. This techniques has the same harmonic spectrum of a equivalent standard VSI with quadruple switching frequency. The output voltage vr0 has five voltage levels obtained as (2n + 1) where n is the number of parallel units. Considering a threephase system, the line-to-line voltage has nine levels. The described concept can be extended to other topologies with different base unit, such as multilevel converter units.

III.6.3

Parallel VSIs converter with circulating current control

A parallel VSIs conversion system, in which individual converters are connected both ac and dc sides directly in parallel, without additional passive components, as shown in fig. III.21, need a proper control structure to minimize the circulating 67


currents [25,67]. This topology allows reducing the size and the cost of the system, but the control strategy results more complex. Parallel VSIs are affected by two topology of circulating-currents [39]: − zero-sequence circulating current; − low-frequency circulating current. Figure III.21 shows the zero-sequence circulating current i0 that occurs between two inverters when opposite zero vectors (i.e. v0 and v7 ) are applied. Moreover, in case of unbalancing of the system parameters and/or non-synchronization of inverters patterns a low-frequency cross-current can appear. Circulating currents have to be avoided because they increase the rms current value of each inverter without providing a load power increasing. Several solutions are available in literature with the aim to reduce the circulating current. As results, the reduction of the circulating-currents allows a easy design of the VSI units, avoiding over-sizing. III.6.3.1

Zero-sequence circulating current model

Considering a non-balanced load, at steady-state the parallel topology of fig. III.21 can be represented by means of the averaged model, as shown in fig. III.22 and as widely described in §II.3.1. The averaged circulating current I0 is defined as (eq. II.17) [25]: I0 = I10 = I11 + I12 + I13 = −I20 = −(I21 + I22 + I23 )

(III.29)

where I10 and I20 are the averaged cross-current of inverter 1 and 2 respectively, while Ixy is the averaged phase current of the inverter x phase y. By means of eq. II.18, the zero-sequence duty cycles of inverter 1 (S10 ) and inverter 2 (S20 ) are carried out as: S10 = S11 + S12 + S13 S20 = S21 + S22 + S23 Thus, it is possible to write: S10 S10 S10 + S12 , + S13 , =0 S11 , 3 3 3 S20 S20 S20 S21 , + S22 , + S23 , =0 3 3 3

(III.30)

(III.31)

and, using eq. II.21, therefore: 0

0

0

0

0

0

S11 + S12 + S13 = 0 S21 + S22 + S23 = 0 68

(III.32)


Figure III.21: Direct parallel connection of VSIs. As shown in fig. III.22, three loops, composed by the ac phases of the two inverters and the zero sequence voltage generators, can be observed. Thus, a zero-sequence circulating current I0 flows in these loops without transfer power to the load. The equivalent circuit of the circulating current I0 is shown in fig. III.23. Moreover, considering the eq.s III.32 and III.29, the dynamic behaviour of the zero-sequence current is described by means of the following equation: Vdc · (S10 + S20 ) = (Lf1 + Lf2 )

dI0 dt

(III.33)

Parallel VSIs converters are usually modulated with an interleaving modulation. As it is shown later on (§III.6.4), interleaving modulation technique, by means of the phase-shifting, has as natural consequence the occurrence of opposite zero vectors between the two inverters, making a short-circuiting of the dc-links capacitors [67]. Moreover, as described in §II.4.3.1, SVM can be characterized by different zero-sequence depending on the placement of the zero vectors. At the same manner, PWM modulation adopts usually a third harmonic injection. Zero-sequence circulating current can be reduced increasing the value of the line inductor, but low-dynamics of the system will be obtained. Moreover, a commonmode inductor solution is analyzed in §III.6.2. The values of the common-mode inductance of the current-sharing reactor is usually calculated considering the maximum averaged values of the circulating current by means of eq. III.33. 69


Figure III.22: Averaged model of a parallel converter with two VSI units.

Figure III.23: Averaged model of the zero-sequence circulating current.

III.6.4

Parallel VSIs converter modulation techniques

Parallel VSIs converters are widely used in high-current application thanks to the possibility to reduce the switching frequency and/or the filter size with the advantage of an interleaving modulation [68]. Standard PWM or SVM are also possible, but the degree of freedom of the structure is ignored and there are several problems of synchronization between the switching signals. Assuming that each unit is modulated by means of a SVM technique (§II.4.3), a suitable phase-shift delays among modulation patterns is possible to obtain a strong ripple reduction of the output current [61]. As shown in §II.4.3.1, in the case of single inverter, the current ripple is function of the reference voltage space vector, the selected modulation pattern and the system parameters (such as output filter, dc-link voltage and switching frequency). Moreover, where a number of n VSI units is in parallel configuration (fig. III.18) the ripple shape of the current in the node of parallel depends on the selected phase-shift delay Si and on the total number of modulated units. Phase-shift delay of VSI unit i (Si ) is referred to the modulation pattern of unit 1. In particular, the case of Si =0 corresponds to a no interleaving modulation and it has the largest ripple of the grid current. The phase-shift delay can assume a 70

III.7 Optimization techniques for two-level VSI

number between 0 and 1. In the case of the parallel of two VSIs, S2 , with respect to the pattern of the first inverter, is usually 41 or 12 . In the case of n=3, the notable phase-shift delays of units 2 and 3 with respect to unit 1 are ( 13 , 23 ) and ( 16 , 26 ). Moreover, non conventional phase-shift can be adopted. In [61] the behaviour of interleaving modulation is studied in the case of two and three VSIs parallel conversion system and it is analyzed the ripple of the current at the point of parallel considering several phase-shift and different reference voltage space vector. In general the phase-shift delays of unit i with respect to the unit 1 can be worked out as follows: Ts (III.34) Si = (i − 1) n where Ts is the Space Vector Modulation sampling time. In the case n=3 and only two units are modulated, the phase-shift delays of each units are: Ts (S1 , S2 , S3 ) = 0, , 0 (III.35) 2 Fig. III.24(a) demonstrates the ripple reduction principle on the grid current, once the above mentioned modulation technique is adopted. in details, the grid current shows a smaller ripple compared to the ones of the two modulated units. In the case of three modulated units, the following phase shifts are applied to each unit: Ts 2Ts (III.36) (S1 , S2 , S3 ) = 0, , 3 3 Thus, fig. III.24(b) shows the ripple reduction principle in this case. The quality of the grid current increases with the number of modulated units. Thanks the intrinsic redundancy and of the modularity of the converter topology, when a module fails, the system is also able to provide an harmonic compensation, within certain limits. For application in which the VSI units are directly connected in parallel on the ac and dc sides, a circulating current is present (as analyzed in §III.6.3). In this case the interleaving modulation technique is still used. In details, the grid current takes the advantages of the ripple reduction, but the current of the units is affected by a zero-sequence cross-current. Thus, to avoid to uncontrol the current of each units, proper modulation techniques has to be adopted [58].

III.7

Optimization techniques for two-level VSI

A standard two-level Voltage Source Inverter can have better performance in terms of waveforms quality and efficiency by means of optimization techniques acting on the hardware structure of the converter and/or on the control section. 71


(a) two units interleaving modulation

(b) three units interleaving modulation

Figure III.24: Switching pattern and current of inverter 1, inverter 2 and inverter 3 and grid current with n=3.

72


Figure III.25: Resonant filter VSI. In details, the optimization techniques for standard VSI, discussed in this section, can be divided into: − hardware optimization − output filter analysis; − dc-link resonant circuit. − control technique optimization − hybrid modulation techniques; − compensation of the non-linearity.

III.7.1

Output filter for VSI

VSI output filters are used to reduce the current harmonic content caused by switching mode operation. With reference of the structure depicted in fig. III.25, several topologies of filter are widely used [69, 70]. The most common topologies are: − L-filter ; − LC-filter ; − LCL-filter. L-filter is a first order filter since it is composed by a three-phase inductor connected in series to the power converter. The structure is depicted in fig. III.26(a). This topology is characterized by an attenuation of 20dB/decade over the whole frequency range, as shown in fig. III.27. L-filter is usually adopted for inverter with high switching frequency where it is easy to achieve high attenuation ratio. The main advantage of this structure is the simplicity and the absence of resonant frequency. However, it presents the vantage of low dynamics, when high values of 73


(a) L-filter

(b) LC-filter

(c) LCL-filter

Figure III.26: Output filter topologies. inductance is necessary to get the desired attenuation. Moreover, large inductor filter has a high voltage drop due to the parasitic resistance. LC-filter is a second order filter composed by an inductor and a capacitor, as shown in fig. III.26(b). LC-filter has a cut-off frequency (f0 , resonant frequency) that divides the behaviour of the filter. In details, before f0 the filter does not change the current value. Whereas, after f0 the filter provides an attenuation of 12dB/octave. The Bode diagram of the magnitude of the transfer function is depicted in fig. III.27. Considering ideal components, the transfer function Fs (s) of an LC-filter is carried out as: Fs (s) =

1 1 + sLf + s2 Lf CR

(III.37)

To mitigate the resonant frequency behaviour near f0 , a dumping circuit is usually adopted, such as resistances. The transfer function of the filter and, thus, the attenuation of the resonant peak change on the basis of the dumping circuits topology (series or parallel). The design of the filter is a compromise between the voltage and current quality acting on the capacitance and inductance values respectively. As high value of inductance causes a low-dynamic response, high value 74


Figure III.27: Bode diagram for filter topologies. of capacitance determs problem due to an high inrush current. LCL-filter is a third order filter (two inductors and one capacitor). The structure is depicted in fig. III.26(c). The filter is characterized by an attenuation of 60dB/decade after f0 . By means of the Bode diagram it is possible to notice how the performance of the filters increasing with the filter order (fig. III.27). In fact, LCL-filter shows a better decoupling between the converter and the grid, reducing, in this way, the dependence of the conversion system from the grid parameters. With LCL-filter it is possible to achieve the same current ripple reduction with smaller values of inductance compared to previous filter topologies, thanks to the capacitor contribute. However, thanks to the capacitor contribute, this kind of filter allows obtaining the same current ripple reduction using a small values of inductance with respect to the others. Thus, the filter has to be designed according to the parameters of the conversion system. In details, the cut-off frequency has to be accorded with one half of the converter switching frequency. The cut-off frequency can be calculated as following: 1 f0 = 2π

r

Lf1 + Lf2 Lf1 Lf2 CR

(III.38)

A dumping circuit is also considered for LCL-filter to resonance around f0 . 75


Figure III.28: Resonant dc-link VSI.

III.7.2

Parallel-resonant dc-link VSI

(a) LC resonant circuit

(b) CLC resonant circuit

(d) LC circuit with three switch

(c) LC circuit with one switch

(e) LC circuit with four switch

Figure III.29: Resonant dc-link circuit topologies. Voltage Source Inverter with resonant dc-link allows obtains a zero-switching losses [71]. In fact, the switches can be commutated when the voltage is zero (Zero Voltage Switching, ZVS), achieving a strong losses reduction. In this way, a high switching frequency can be adopted obtaining, at the same time, low distortion 76


and high efficiency. The circuital structure of a parallel-resonant dc-link VSI is depicted in fig. III.28. The dc-link has a resonant tank circuit that is able to decouple the source to the dc-link behaviour. The base concept of resonant dc-link inverter is to add a simple LC circuit (fig. III.29(a)) to a standard VSI. This additional circuit generates an oscillation of the dc-link voltage. Additional capacitor can be added to the circuit (fig. III.29(b)) to stabilize the dc-link voltage. Other resonant topologies are obtained with the inclusion of switches as depicted in fig.s III.29(c), III.29(d) and III.29(e). Other advantages are related to the non necessity to snubber circuit and to the noise reduction. The increasing of the rating of power semiconductor devices due to the high current and voltage that they have to tolerate is a disadvantage of this structures. Moreover, the modulation technique is a no-standard technology and has to be adapted to the selected resonant circuit. Therefore, the inclusion of the resonant circuit increases the complexity and the costs of the power conversion system not often well balanced by the conversion efficiency increasing [72].

III.7.3

Hybrid modulation techniques

To obtain a current ripple reduction, a Voltage Source Inverter can be modulated by means of a SVM (§II.4.3) with hybrid modulation technique. In details, a multiple switching sequence can be adopted into the sector. In fact, considering the magnitude and the phase of the reference voltage space vector, there is no best sequence in all the sector area. In [36] several hybrid modulation are presented dividing the SVM sector several areas with the aim to optimize the current THD. The distribution of the switching patterns in the SVM sector is depicted in fig.s III.30(a), III.30(b) and III.30(c) for the hybrid modulation technique with three, five and seven areas respectively. Hybrid modulations are also adopted in the case of parallel VSIs converter (§III.6). As analyzed in §III.6.4, interleaving modulation allows obtaining a current ripple reduction on the point of parallel by means of a proper phase-shift delay among the modulated units. The ripple reduction depends on both modulation pattern and phase-shift delay. Thus, an optimization technique can be developed selecting the pattern and the delay on the basis of the position of the reference voltage space vector in the Gauss plot [61]. In fig. III.31, the RMS of the ripple current is depicted taking into account several modulation pattern and different the notable phase-shift delay for a two VSIs parallel converter. In details, “90d” corresponds to S2 = 41 and “180d” to S2 = 12 .

77


(a) three-zone

(b) five-zone

(c) seven-zone

Figure III.30: Hybrid SVM technique. The spatial regions A, B1, B2, C1, C2, D1, and D2 are the regions of superior performance of sequences 0127, 0121, 7212, 1012, 2721, 012, and 721, respectively [36].

III.7.4

Non-linearity compensation techniques for VSI

[Original contribute] The causes of the non-linear behaviour of a Voltage Source Inverters are several. The dead-time, for example is inevitable delay to avoid short-circuit of the dc source during the switches commutations (§II.2.1). Other effects are correlated to the physical behaviour of power semiconductor devices, such as the voltage drop, the output voltage/current transient and the turn-on/turn-off delay times. In particular, power devices react to the turn-on/turn-off of control signal with a delays (Ton , Toff ), that are function of the semiconductor topology, power rating, temperature and actual current. Since the turn-off time is greater than the turn-on time, to avoid short-circuit of dc source, a delay time Td , called dead-time, have to be introduced. The non-linearity of VSI causes the increasing of harmonic distortion and loss in the fundamental voltage waveforms [23, 73]. The real behaviour of the converter causes considerable effects to the voltage syntheses, that leads a current waveform distortion and a maximum modulation index limitation [26]. In particular, considering high switching frequency applications, the effects of the turn-on/turn-off and dead-time are more emphasize, while the voltage drop effects are significant 78


Figure III.31: Comparison between different modulation pattern and phase-shift delay for a two VSIs parallel converter [61]. when high power is processed [73]. The compensation of the effect of the dead-time, as well as the ones due to the other non-linearities, is an important technical issue to reduce voltage drop and current distortion. III.7.4.1

State of arts

In literature, non-linearity effects of VSI are widely analyzed and different solutions have been proposed to achieve the voltage distortion compensation. Traditional compensation methods can be classified into two main categories on the basis of the way as the voltage error, due to non-linearity characteristics, is detected and compensated [21]. In a category, based on averaging theory, the error voltage is averaged over an entire cycle and added to the reference voltage according to the direction of the load current. In the other one, pulse-based compensation methods, the voltage error in evaluated within each PWM pattern and compensated in the next PWM period. The methods of the first category usually have a quite slow compensation action, while the ones of the other category are more accurate and faster, but increase the overhead on the control unit. The main problems of these methods are the correct calculation of the compensation voltage and the accurate detection of the zero-crossing of the current, since the compensation depends on the load current polarity. The compensation can be only evaluated according the dead-time and the other parameters of the power devices (§II.2.1). Several authors proposed a start-up identification of the parameters to calibrate the system model. Moreover, these uncertain parameters are not exactly measurable and are function of the operating conditions. In [74] a predictive algorithm for VSI is presented with the aim to compensate the 79


Figure III.32: VSI control structure. non-linearity effects by means of an analytical prediction of the dead-time effects in each PWM cycle. The zero current crossing has been taken into account by means of an estimation of the phase current. For the dead-time compensation, a great reduction of the voltage distortion can be achieved commutating in each sampling time, only on switch of the leg according to the phase current sign, while the other switch is kept “off ” [75]. That method allows to avoiding the dead-time, when the sign of the current is certain, and the voltage distortion is only due to the others non-linearity effects. The detection of the current sign, especially at the zero-crossing, has a key role considering this method. An accurate model-based compensation method is presented in [76] for the analytical compensation of the VSI non-linearity. However, some parameters can change during the operating conditions, for instance, the voltage drop across the switches changes with load current and frequency. The parameters mismatch could lead a deterioration of the performance in terms of the voltage error compensation. An observation of the voltage error can be a proper method to avoid the parameter variation effects [77]. III.7.4.2

Recursive dead-time compensation techniques

A new method for the compensation of the VSI non-linearity at steady-state conditions is presented. The algorithm is based on a recursive method: it evaluates step-by-step the voltage distortion on the basis of the difference between the reference current and the measured one, at the end of each sampling period. At steady-state, this voltage distortion is used to correct the reference voltage space 80


Figure III.33: Non-linearity compensation algorithm principle. vector to be applied at the same sampling period inside the following steady-state voltage period. The voltage distortion is kept until a further change of operating condition occurs. This approach is particular suitable for high power PV plant, where the operating conditions change slowly and the dead-time effect can be considerable. With reference to fig. III.32, a predictive control (§II.4.6) of VSI has been implemented. In particular, starting from the load current reference space vector (i∗ ), the voltage reference space vector (i∗ ) of the inverter is given: L ∗ ∗ i vnTs = − inTs − R · inTs (III.39) Ts (n+1)Ts where Ts represents the adopted Space Vector Modulation (SVM) sampling interval, subscripts “n” indicates quantities measured or calculated at the n-th sampling time. The proposed compensation technique is based on step-by-step evaluation of the voltage distortion, calculated considering the ideal (full-compensated) and the actual (no-compensated) inverter output currents. As a matter of fact, the difference between the current reference space vector (i∗ ) and the measured one (i), at the end of each sampling period, is related to non-linear behaviour of VSI. The proposed voltage compensation technique evaluates the total voltage drop at each n-th sampling time within the steady-state voltage waveform, as shown in fig. III.33. This voltage drop is, then, imposed as voltage correction in the same nth sampling time at the following voltage waveform evolution. Considering that voltage drop at each sampling time depends also on the initial conditions, i.e. evolution at the previous sampling period, a recursive method can be applied, which 81


Figure III.34: Non-linearity compensation algorithm time evolution. correct one sampling time voltage distortion per period. In particular, considering a steady-state conditions, the compensation technique builds up an array, Vc , of Nc voltage space vectors with: T Nc = (III.40) Ts where T represents the fundamental period. The algorithm needs Nc consecutive evolutions of current waveforms to fill out the voltage array. Taking into account the model depicted in fig. III.32, each n-th element of the voltage array is calculated in n-th sampling time of the n-th evolution of current waveforms by means of the following equation: Vc [n] = v∗(nTs ) +

Lf ∗(n+1)Ts (i − i(n+1)Ts ) Ts

(III.41)

Therefore, to compensate the voltage distortion at the n-th sampling time, within the n-th evolution of the steady-state voltage, the algorithm applies the voltage correction as indicated in III.41, calculated at the n-th sampling time in the previous (n − 1)-th evolution of the steady-state voltage. The time evolution of the algorithm principle is shown in fig. III.33. Therefore, the complete steady-state voltage compensation is achieved after a time equal to N · T . The proposed algorithm is based on the hypothesis that the current ripple has a zero-average in the sampling time. Using a symmetrical modulation techniques this assumption is in general verified. Unfortunately, the introduction of the VSI non-linearity produces a distortion of the current waveforms, but also in terms 82


of current ripple. Further developments of the recursive dead-time compensation methods has to be equipped of an additional signal taking into account the ripple distortion due to the VSI non-linearity. III.7.4.3

Simulation results

®

A numerical analysis, performed by using the SimPower System Toolbox of Matlab-Simulink , has been carried out in order to validate the proposed algorithm. A complete simulation, including power electronic converter, passive components, load and control has been arranged. In particular, the characteristics of Mitsubishi power modules PM100DSA120 have been considered. Td and Vdc have been set to 8 µs and 370 V respectively. As load, a resistance of 12 Ω and an inductance of 2 mH have been used. A symmetrical SVM with switching frequency of 10 kHz have been implemented. Thus, for instance, if the frequency of the reference current is set to 50 Hz, the algorithm needs N =200 consecutive steady state evolutions to evaluated the voltage errors and to fill out the voltage array. In fig.s III.35(a) and III.35(b), the waveforms of load phase current, |i∗RMS |=8.5 A, with and without the voltage compensation are depicted. Moreover, the ideal load voltage vL∗ and the average value of the actual one vL are respectively shown in fig.s III.35(c) and III.35(d). It is possible to notice the validity of proposed compensation algorithm, in fact, the RMS values and THD of the currents are respectively 7.5 A and 5.9% without compensation, 8.1 A and 5.2% in the other case.

®

III.7.4.4

Experimental results

After the preliminary numerical analysis, a VSI based test bench has been set up to experimentally validate the proposed compensation technique. In particular, Mitsubishi power modules PM100DSA120 has been used to perform the power converter. The control algorithm and symmetrical SVM have been implemented by means of a DSP (implemented by means of a DSP modular system of dSPACE ) and by the CPLD board, based on Altera max 7000, respectively. Experimental results, obtained under the same operating conditions of numerical analysis, are here reported. In detail, the waveforms of load phase current with and without the voltage compensation, when |i∗RMS |=8.5 A is imposed, are shown in fig. III.36(a) and III.36(b). Whereas, fig. III.36(c) and III.36(d) show the voltage waveforms. It is possible to notice that the experimental results fully match to simulates one. This result confirms the validity of proposed algorithm. In particular, the RMS values of currents are equal to 7.7 A, without compensation, and 8.4 A with the voltage compensation. Furthermore, the THD of the load current is 6.1% and 5.0% respectively. A higher value of Td has been also adopted to emphasize the compensation effect of the proposed algorithm. The load phase currents, nocompensated and compensated, are respectively reported in fig. III.37(a) and

®

®

83

®


(a) load current waveform and reference without the proposed compensation algorithm

(b) load current waveform and reference with the proposed compensation algorithm

(c) load voltage space vector and the ideal one without the proposed compensation algorithm

(d) load voltage space vector and the ideal one with the proposed compensation algorithm

Figure III.35: Simulation results considering a dead time equal to 8 µs. III.37(b) when Td is equal to 16 µs. The RMS values of currents are equal to 7.0 A, without compensation, and 8.0 A with the voltage compensation. Moreover, the THD of the load current is 9.8% and 6.9% respectively.

84




(c) load voltage space vector and the ideal one without the proposed compensation algorithm

(d) load voltage space vector and the ideal one with the proposed compensation algorithm

Figure III.36: Experimental results considering a dead time equal to 8 µs.



Figure III.37: Experimental results considering a dead time equal to 16 µs.

85


86

Applications

87

Chapter IV

Power conversion systems for photovoltaic applications In the field of renewable energy, the improvement of the efficiency of photovoltaic (PV) power conversion systems is still one of the most important technical requirements. In this chapter, after a brief introduction on power conversion system for PV applications, a novel power converter configuration for high power grid-connected photovoltaic systems is presented. It allows increasing the conversion efficiency with respect to a classical solution, based on centralized inverter, in whatever operating condition. In particular, the improvement of efficiency is due to both optimal power sharing algorithm and suitable interleaving modulation technique.

IV.1

Overview of PV power conversion systems

Recent researches on Photovoltaic (PV) applications have been focused on increasing the overall efficiency, stability, reliability and power quality of the system. PV plants are usually classified on the basis of the connection to the grid, in details there are: − grid-connected system; − stand-alone system. Grid-connected power conversion systems are inject power from a PV generators into the grid. The Point of Common Coupling (PCC) defines the boundary between the PV plant and the grid utility. Stand-alone systems are equipped with battery bank to store the generated power and this topology is minority compared to grid-connected systems. The schemes of the two topologies are depicted in fig. IV.1(a) and IV.1(b), respectively. 89

CHAPTER IV. Power conversion systems for photovoltaic applications

(a) grid-connected

(b) stand-alone

Figure IV.1: Photovoltaic system.

Power conversion system for grid-connected PV plants has to fulfil three different requirements, such as: − to control the power injected into the grid; − to regulate the power provides by the PV generator; − to avoid the islanding operation. In details, the power conversion system has to adapt the generated power to the grid requirements, in terms of shape and quality of current and voltage waveforms. Moreover, the conversion system has the function to regulates the PV generated power in such a way to extract the maximum available power. Thus, it is necessary to develop a control algorithm to track the Maximum Power Point (MPP) [78,79]. The MPP Tracker (MPPT) control strategy are based on different schemes: perturb-and-observe, incremental-conductance, parasitic capacitance or constant voltage. PV power conversion system handles also the anti-islanding protection to avoid that portion of the utility network is provided by the PV generator when the main grid is disconnected. Thus, islanding detection methods results necessary [79]. Photovoltaic power conversion system are classified on the basis of the PV plant structure or the converter topology [79–81]. Considering the PV modules connection, the power conversion systems are classified as: − centralized technology; − string technology; − multi-string technology; − module technology; − master-slave control ; − team operation. 90

IV.1 Overview of PV power conversion systems

The PV inverter topologies are depicted in fig. IV.2. Centralized technology is bases on a central inverter connected to a PV field obtained as the parallel of PV strings (fig. IV.2(a)). The dc-link of a centralized inverter has to be designed for high current and high voltage, thus this solution is usually adopted for high power applications. The switching frequency of the converter has to be decreased for high power applications mainly due to switching losses; thus, large filters have to be installed in PCC to reduce current Total Harmonic Distortion (THD), as technical standards require. Moreover, the structure results simple, but not flexible. The centralized converter implements a common MPPT algorithm for the overall PV generators. Thus, the MPP is not reached for all the strings and there are losses of power due to a large group of connected PV strings. Each string can be controlled by a MPPT algorithms by means of a dc-dc converter (multi-string technology, fig. IV.2(b)) or including VSI for each string (string technology, fig. IV.2(c)) allowing to increase the efficiency of the PV field. While the centralized technology is usually adopted for three-phase system, the string and multi-string technologies are used for medium-power single-phase applications. These structures have simple design and installation procedure, moreover it is easy to switch-off a section affected by fault. Each PV module can be connected to a micro-inverter obtaining the solution called module-technology. Fig. IV.2(d) shows the structure of this topology. This solution has higher installation cost, however the operating costs are reduced due to the lower mismatch losses. The obtained design results flexible and fault-tolerant. The drawback of a module technology is the decreasing of the conversion efficiency due to the low power of inverters, but also the high costs. New concepts, based on master-slave control and team-operation, have been developed in last few years combining the advantages of string and centralized technologies with the aim to reduce the costs and to increase the efficiency [82]. As reported in §I.2.2, a power converter is affected by conduction losses, switching losses and constant power losses. Control circuit power losses have a strong impact on the conversion efficiency when low values of output power are required. In case of modular structures, total power losses are the sum of power losses of each unit. Since it is possible to disconnect some units on the basis of the value of the output power reference and it allows reducing the impact of constant power losses on conversion efficiency. These new topologies optimize the power losses of the power conversion system managing the number of modulated units. Master-slave operating mode is used when more than two inverters are connected in parallel on the dc-link side (fig. IV.2(e)). The master inverter controls the number of modulated units on the basis of the available power from the PV generators. This technology allows increasing the efficiency of the power conversion system, especially when low-power is generated. In details, the inverters are controlled to work near the point of maximum conversion efficiency, increasing the number of modulated units with the incremental of the power that has to be processed. 91


(a) centralized technology

(b) muli-string technology

(c) string technology

(d) module technology

(e) master-slave control

(f) team operation

Figure IV.2: Photovoltaic inverter topologies. The increasing of efficiency for low output power is proved. The disadvantage of this solution is that the PV field, even if is composed by several strings, has a unique MPPT control algorithm. Team operation is adopted for string technology inverters connected in parallel. The topology structure is depicted in fig. IV.2(f). In details, when low-power is produced by the PV strings, the switches SA and SB are switched-on, connecting the PV strings in parallel, and just one inverter is modulated. In this way, the impact of the constant power losses can be reduced with the increasing of the generated power, the number of activated inverter increases. In particular, when high power is available from the PV field, each string is connected to a converter and each unit implements a proper MPPT control. Moreover, at nominal power, each PV string is connected to a proper VSI with its MPPT control. Fig. IV.3 shows the conversion efficiency of master-slave and 92

IV.1 Overview of PV power conversion systems

Figure IV.3: Curve of efficiency of several topologies of PV power conversion system [83]. team-operation solutions with respect to the centralized and string technologies. The PV voltage can be amplified on the basis of inverter requirement by means of a dc-dc converter obtaining a multiple-stage power conversion system. For instance, the multi-string technology has a multi-stage structure, while centralized inverter can be connected to the PV plant directly (single-stage structure) or by means a dc-dc converter. Multiple-stage power conversion system has a degree of freedom, the dc-dc converter implements the MPPT algorithm while the inverter implements the grid control. A transformer can be included between the power conversion system and the grid for isolation issue (line-frequency transformer ) or in the conversion system for operating issue (high-frequency transformer ). The former one is bulky and costly, but it is inserted for safety reason or it is required by the utility, especially for high-power PV plants. New power conversion system topologies with multiple-stage structure prefer to use high-frequency transformer for their reduced dimension and weight. Both transformers topologies causes additional power losses (cores and windings losses). The development of high-frequency cores has an important effect on the PV conversion system in terms of efficiency increasing and costs reduction.

IV.1.1

Power conversion system topologies

For three-phase PV power conversion systems, different topologies of inverter are reported in literature: 93


− two-level Voltage Source Inverter; − multi-level converter; − parallel connection of VSIs. Voltage Source Inverters (VSIs) are widely used to interface PV strings to the grid, converting PV dc-link voltage into ac current for the utility. VSIs are equipped with an output filter to fulfil the grid requirements in terms of current quality at the PCC. The converter is controlled to both maximizing the energy from the PV modules and to comply standards required by the utility (THD, active and reactive power, islanding operation, synchronization). In literature, several solutions have been proposed for high power PV plants, such as multilevel converters and parallel connection of VSIs [80,84,85]. They guarantee high values of the conversion efficiency and, at the same time, the respect of the connection standards to the grid. However, all these solutions have advantages but, also, several limitations. Multilevel converters represent a no-standard technology; benefits in terms of energy efficiency are usually not well balanced by the more complexity in structure and control. Parallel connection of standard inverters can represent a valid solution, but a proper control strategy has to be set-up in order to maximize the efficiency. As a matter of fact, parallel connection can be suitable at particular operating conditions, but not always in the entire operative range. Other structures of parallel connection of single/three-phase inverter obtaining a modular structure of multilevel converter for high-voltage/high-power applications are collected in [62]. More details about the structures, the models and the modulation techniques of VSI, MLC and parallel connection of VSIs are presented in §II and §III.

IV.1.2

Filters topologies

Low-pass output filters have been placed between the power conversion system and the grid to meet the harmonic requirements of the utility at the PCC. Filter topologies are widely analyzed in §III.7.1. In PV applications, the use of L-type filter is quite common due to the simple structure. Usually an high value of inductance is required to respect the THD limit. Thus, the system dynamics are reduced and an high voltage drop is introduced due to the windings resistance. LC-type filter, instead that L-type, is recommended especially for high-power applications to obtain a better attenuation of the switching components. A high value of capacitor has selected to increase the efficiency, but a compromise has to be found to avoid the increasing of the inrush current. Moreover, the phenomenon of the resonance appears on the ac side in the case of second-order filter. LCL-type filter has advantages in terms of components sizing and decoupling with the grid impedance. The obtained attenuation is higher even if low values of capacitor and inductor are inserted [86]. 94

IV.2 Multi-inverters power conversion system

An electrolytic capacitor is considered in the dc-side, as power decoupling between the strings and the grid and it is usually placed in parallel with the strings or on the dc-link of the inverter. Assuming a constant dc-link voltage (Vdc ), the value of the capacitance is chosen by means of the following equation: C=

PPV 2ωVdc Vˆdc,r

(IV.1)

where PPV is the nominal power of the PV plant, ω is the grid pulsation and Vdc,r is the amplitude of the dc-link voltage ripple.

IV.1.3

System sizing

The choice of semiconductor devices, power conversion system, passive elements, as well know, makes effects on the system size, losses and price [87]. Thus, power design of a photovoltaic power conversion systems takes into account: − PV plant power rating and structures; − average solar radiation and temperature of the installation site; − power semiconductor devices characteristics and costs; − power conversion systems performance and costs; − utility grid requirements at the point of common coupling. The PV output power and voltage are calculated using the PV field model considering the dependence with solar radiation, site temperature, electrical feature of the PV modules and system configuration (series-parallel connection of modules). High-power PV system are usually equipped with IGBT power converters. The switching frequency is chosen as trade-off with different variables, such as efficiency, costs and filter design. Moreover, cooling, dimensions and weight are factors to be taken into account. Fixed the power converter topology, the semiconductor technology and the power rating, the choice of switching frequency (fsw ) and the filter components sizing is a compromise between costs and efficiency with the aim to respect the utility requirements in terms of harmonic distortion of the provided current. Therefore, the voltage drop introduced by the filter has to be considered. Additionally, the filter components are chosen in such a way to ensure the filter resonance frequency (f0 )restrains into the following range: 10f ≤ f0 ≤

fsw 2

(IV.2)

where f is the output fundamental frequency.

IV.2

Multi-inverters power conversion system

[Original contribute] 95


PV systems are often equipped with centralized inverters, especially for high power applications. In particular, strings are usually configured in such a way as to reach a sufficient value of the output voltage, in order to avoid additional amplifications. As conversion unit, a two-level VSI (labelled with inverter c, widely analyzed in §II) is typically adopted, as shown in fig. IV.4. A large output filter (Lf,c ) is needed to reach required THD values. A line frequency transformer is also necessary to guarantee a galvanic isolation. Figure IV.5 shows the scheme of the proposed PV power converter topology, based on parallel VSIs converter (§III.6). In particular, the centralized inverter is replaced by two or more VSI units (in this example, n inverters, labelled with numbers 1, 2, ..., n) connected in parallel and controlled by interleaving modulation technique. Three identical output filters (Lf ) are also included with a multi-sources line-frequency transformer to avoid circulating current. As it will be shown later on, conversion efficiency of the proposed solution allows obtaining higher efficiency if compared to centralized inverter solution. This advantage is achieved thanks to a proper inverter selection algorithm. In particular, it is based on a considerably reduction of switching frequency and the suitable selection of the best VSIs configuration function of the actual operating conditions. The parallel connection of VSIs has characterized by two degrees of freedom. The former one is due to the possibility to switch-off each unit on the basis of the processed power (master-slave operating mode, §IV.1). Moreover, the modulation patterns of the units can be shifted obtaining a current ripple reduction on the total current. In order to perform a valuable analysis and to achieve relative increment of energy efficiency, proposed structure has been compared to a centralized inverter one with the same power rating and working at the same operating conditions.

IV.2.1

Modelling and Control Strategy of Power Converter

With reference to fig. IV.5, considering an ideal transformer, the proposed grid-connected PV converter system can be represented by the following set of equations [4]:

 dii  vg = vi − Lf    dt   vi = Vdci fi with i = 1, ..., n  n  X    ii  ig = i=1

96

(IV.3)


Figure IV.4: Scheme of the grid-connected PV system: centralized inverter topology. where: vg ig vi ii fi Lf Vdci

grid voltage space vector; grid current space vector; voltage space vector of the i-th inverter; current space vector of the i-th inverter; space vector commutating function of the i-th inverter; inverter output inductance; dc-bus voltage of the i-th inverter.

A standard MPPT algorithm [78] has been adopted in order to carry out the value of the module of total grid current reference space vector i∗g . Phase of i∗g is chosen as function of the required power factor. The reference current space vector i∗i of each VSI is selected by means of an optimal power sharing algorithm. Starting from the reference current i∗i , a predictive control (§II.4.6) has been implemented for each VSI unit. In particular, the commutating functions of each VSI is evaluated as follows: Lf ∗(m+1)Ts 1 s − vmTs fimTs = ii − imT (IV.4) g i Vdci Ts In (IV.4), Ts represents the Space Vector Modulation (SVM) sampling interval, while superscripts “m”indicates quantities evaluated at the m-th sampling time. The power sharing algorithm, combined to interleaved modulation, allows achieving considerably reduction of losses. In the following sub-sections, interleaving modulation and of optimal power sharing algorithm are reported. 97


Figure IV.5: Scheme of the grid-connected PV system: interleaved inverters topology. Regarding the centralized solution fig. IV.4, considering an ideal transformer, the power conversion system can be represented by the following set of equations:  dig,c  vg = vc − Lf,c (IV.5) dt  vc = Vdc,c fc where: ig,c vc fc Lf,c Vdc,c

grid current space vector; voltage space vector of inverter c; space vector commutating function of inverter c; inverter output inductance; dc-bus voltage of inverter c.

Concerning MPPT algorithm and predictive control, they are the same of the proposed multi-VSIs solution.

IV.2.2

Interleaving Modulation

The centralized inverter and each VSI unit of proposed power conversion system are modulated by means of a SVM technique (§II.4.3). In order to improve the systems performance in terms of current ripple and of switching losses, the clamping sequence for symmetrical SVM has been adopted (fig. II.15, §II.4.3.1) [67]. With reference to the proposed solution, VSI outputs are connected to the primary windings of transformer through inductors Lf . By means of a suitable phase-shift 98


delays among modulation patterns of the n units, it is possible to obtain a strong ripple reduction of the output current to the point common coupling (§III.6.4). The phase-shift delay of i-th VSI unit (Si ) with respect to modulation pattern of unit 1 depends on the total number n of modulated units and is given by eq. III.34. Thus, it is possible to achieve the same ripple of the grid current at lower switching frequency for each unit, obtaining lower switching losses [4]. As described in the following section, the optimal power sharing algorithm works out the number of modulated units as function of the actual power.

IV.2.3

Power losses calculation

The total power losses (Ploss,tot ) of a PV power conversion system are carried out by means of the converter power losses (Ploss,c , §I.2.2), the power losses of a L-filter (Ploss,f ) and the power losses of the transformer (Ploss,t ). As described in §I.2.2, power losses of classical two-level VSI can be divided in: switches and diodes conduction losses (Pcd ), switches and diodes switching losses (Psw ) and control circuits power losses (Pct ). The conduction and switching power losses have been calculated taking into account the datasheet parameters of the power device. In details, the power semiconductor devices (switches and diodes) are approximate with a series connection of dc-link voltage source and a resistance. The switch and diode switching losses have been calculated taking into account the energy losses of the power device during turn-on, turn-off and reverse recovery. In particular, the energy per pulses are considered function of current power device, during turn-on (Eon ), turn-off (Eoff ) and reverse recovery (Err ). The control circuits power losses (Pct ) are usually taken into account as a constant value. Thus the Pct has a strong impact on the conversion efficiency when low power is required. Power losses of a L-filter (Ploss,f ) are composed by cores losses (PL,c ) and windings losses (PL,w ). This losses are function of the inductor manufacture parameters and are carried out as following [88]: √ PL,c =pc L(I0 2)z (IV.6) PL,w =Ir2 rL L + I02 rL L where: L inductor value [H)]; z constant of the inductor core; pc inductor core losses factor [W/(HAz )]; rL inductor windings resistance [Ω/H]; Ir RMS value of ac current ripple; I0 PV inverter output current. The power losses of filter dumping resistance has also to be included if a LC or LCL filter is adopted. 99


The transformer power losses (Ploss,t ) are divided in no-load losses and copper losses. The former ones are computed as hysteresis losses and eddy-current losses on the machine iron. The latter ones are correlated to the windings resistances. On the basis of the mathematical model expressed in §I.2.2, the conversion efficiency (ηp ) of the proposed power conversion system can be expresses by: n P

ηp = P n

Pout,i

i=1

Pout,i +

i=1

n P

Ploss,ci + +

i=1

n P

(IV.7) Ploss,fi + Ploss,t

i=1

where the subscript “i” indicates the contribute of the i-th unit and Pout,i is the active output power of the i-th VSI unit. In the following analysis, the power losses of the transformer and the filter are not considered.

IV.2.4

Total harmonics distortion calculation

Regarding a three-phase VSI with a Space Vector Modulation (SVM), the current ripple depends on the error between the instantaneous space vector output voltage (one of the 8 space vectors output voltage of a VSI) and the reference voltage space vector. From eq. IV.3, the instantaneous current space vector (ii (t)) of the i-th inverter during the m-th sampling time can be expressed as: Z t 1 ii (t) = (vi − vg ) dτ 0 ≤ t ≤ Ts (IV.8) Lf 0 By means of the method described in §II.5 and considering the proposed PV conversion system, the grid current ripple (ieg (t)) is the sum of the ripple of each modulated unit as shown in the following equation: ieg (t) =

n X iei (t)

0 ≤ t ≤ Ts

(IV.9)

i=1

Thus, the THD of the grid current can be calculated as follows: T HDp =

∆ig,RMS ig,RMS

(IV.10)

where ∆ig,RMS and ig,RMS are respectively the RMS value of the ripple and the RMS value of the fundamental of the grid phase current.

IV.3

Optimal power sharing algorithm

Starting from the current THD constrain and the value of the grid reference current i∗g , the optimal power sharing algorithm carries out the number of units 100

IV.3 Optimal power sharing algorithm

Figure IV.6: Flowchart of optimal power sharing algorithm. to be modulated with the interleaved technique, as well as their reference currents and switching frequencies to maximize the value of power conversion efficiency of the proposed system, as shows in fig. IV.6. Fig. IV.7 shows the flowchart of the proposed algorithm. First, it determines the minimum number of the units (nmin ) that have to be modulated by means of following set of equations: nmin = ceil

∗ Pac Pn

(IV.11)

∗ where Pac is the required total power and Pn is the nominal power of the VSI unit. By considering nmax as the number of total converter units, among the admissible nmax − nmin system configurations, the generic configuration characterized by n modulated units, with nmax − nmin ≤ n ≤ nmax , is called operating mode n. It can be described by means of the following equations:

 ∗  ii 6= 0  Si = (i − 1) Ts n

for i = 1, ..., n

(IV.12)

For each feasible configuration, the optimal power sharing algorithm identifies which values of the switching frequency, the same for all units, and of the reference currents allow to maximize the conversion efficiency of the system under THD constraint. In particular, the algorithm evaluates the conversion efficiency for several combinations (N ) of reference currents of the modulated units. The values 101


Figure IV.7: Flowchart of optimal power sharing algorithm. of the reference currents are selected under the constraints:  n X   |i∗ | = i∗ i

g

i=1   ∗ |ii | ≤ In

with i = 1, ..., n 102

(IV.13)

IV.3 Optimal power sharing algorithm

where In is the rating current of the VSI unit. The algorithm varies the switching frequency to carry out the maximum efficiency point for each reference currents combination, by taking into account the THD constraint. The value of switching frequency is selected by means of an incremental iterative method within the interval: fsw,min ≤ fsw ≤ fsw,max

(IV.14)

where fsw,min and fsw,max are the minimum and maximum switching frequency, respectively. M is the total number of switching frequency values which are considered by algorithm. By considering ∆f as the fixed frequency increment, it yields: M=

fsw,max − fsw,min ∆f

(IV.15)

Considering the generic operating mode n, for each j-th pattern of reference currents, the algorithm evaluates the conversion efficiency related to different values of the switching frequency of modulated VSI units. Since the computing of the maximum efficiency point for the the generic operating mode n is performed starting off with the smallest value of fsw , it is possible to avoid the analysis of all M values. In fact, the calculation is stopped once the k-th fsw allows achieving the respect of the following conditions: ( T HDpn,j,k ≤ T HDc (IV.16) ηpn,j,k ≥ ηc where T HDpn,j,k and ηpn,j,k respectively represent the values of grid current THD and conversion efficiency of the proposed system for the operating mode n when the j-th pattern of reference currents and k-th switching frequency are selected. The T HDc and ηc are the values of grid current THD and conversion efficiency for centralized solution, respectively. The details of the found operating condition (n, k, j, T HDpn,j,k , ηpn,j,k ), that allows maximizing the conversion efficiency and, at the same time, increasing the centralized inverter conversion efficiency, are stored as a local maximum efficiency point. Once all admissible system configurations have been tested, the algorithm selects the operating condition with the highest conversion efficiency among the local maximum efficiency points. A simplify version of the algorithm is also presented in [4] for a number of units equal to 3 and it is assumed that the optimal efficiency point is always obtained by means of an uniform power sharing of the modulated units. Starting from the current THD constrain of the centralized solution (THDc ) and the value of the grid reference current i∗g , the optimal power sharing algorithm carries out the number of units n to be modulated, as well as their reference currents (i∗i with i=1,2 and 3 ) and switching frequencies to maximize the value of power conversion efficiency of the proposed system (ηp ). In particular, considering 103


that the power rate of each VSI composing the proposed topology (Pn ) is equal to 1/3 of the total power, the following three operating modes are taken into account: ( • mode 1

• mode 2

• mode 3

(i∗1 , i∗2 , i∗3 ) = i∗g , 0, 0 (S1 , S2 , S3 ) = (0, 0, 0)

(IV.17)

∗ ∗  ig ig ∗ ∗ ∗   (i , i , i ) = , ,0  1 2 3 2 2  T   (S1 , S2 , S3 ) = 0, s , 0 2

(IV.18)

∗ ∗ ∗  ig ig ig ∗ ∗ ∗    (i1 , i2 , i3 ) = 3 , 3 , 3  T 2T   (S1 , S2 , S3 ) = 0, s , s 3 3

(IV.19)

In details, reference current of each unit is always equal to the total reference current divided by the number of the modulated units. Considering a generic value of i∗g , the optimal power sharing algorithm estimates first Pac , ηp and THDc of the centralized solution. With reference of Pac , the algorithm, on the basis of the nominal power (Pn ) of each unit, carries out the operating modes that can be selected for the proposed power conversion system, as shown in the flowchart of fig. IV.8(a). Then, for each admissible operating mode the algorithm identifies the value of the switching frequency (fsw ) that allows maximizing the conversion efficiency and obtaining a grid current THD value equal or lower than the one of the centralized solution (THDc ). In detail, to choose the optimal switching frequency, the algorithm, starting from a minimum switching frequency (fmin ), increases for each admissible operating modes the value with a fixed-step frequency increment (∆f ). For each combination (mode, fsw ), the algorithm estimates the total power losses and the current THD, as shown in fig. IV.8(b). Finally, the combinations characterized by the maximum value of conversion efficiency is chosen.

IV.4

Numerical results

®

Numerical analysis have been performed by using the SimPower System Toolbox of Matlab-Simulink in order to validate the proposed grid-connected PV converter system. In details, two test-benches have been set-up with different power rating to prove the results trend. Power rating of the power conversion systems has been made tacking into account the design optimization technique presented in [87]. 104

IV.4 Numerical results

(a) flowchart of the algorithm

(b) operating modes

Figure IV.8: Simplified version of the optimal power sharing algorithm .

105


Pn,c

300

[kW]

Vdc

800

[V]

|vg | ∗ ig,n

352.73

[V]

500

[A]

Lf,c

0.17

[mH]

IGBT module

CM1000 DXL-24S

Table IV.1: Parameters of Centralized PV System. n

2

3

4

5

Pn

150

100

75

60

[kW]

Vdc

800

800

800

800

[V]

|vg | ∗ ig,n

352.73

352.73

352.73

352.73

[V]

250

167

125

100

[A]

Lf

0.17

0.17

0.17

0.17

[mH]

IGBT module

CM600 DXL-24S

CM450 DX-24S

CM300 DX-24S

CM200 DX-24S

Table IV.2: Parameters of Single VSI Unit of Proposed Solution.

IV.4.1

High power test-bench

A complete simulation, including model of PV generator, power electronic converters, passive components and ac line generators, has been arranged both for classical and proposed converter topology. In particular, 185.13 W, 36.3 V PV modules have been considered and a 300 kW PV plant has been arranged. For the proposed power conversion system, different values of n have been considered. In particular, four proposed system configurations are analyzed respectively with 2, 3, 4 and 5 power units. Parameters of centralized and proposed power units are shown in Tab. IV.1 and Tab. IV.2. In both cases of centralized and parallel VSIs power conversion system, the characteristics of Mitsubishi IGBT have been considered to evaluate the power losses. In particular, conduction and switching power losses have been calculated by means of the device characteristics reported in their datasheets. Control circuit power losses have been imposed equal to 800 W for the centralized system and equal to 1/n for each single VSI unit of the proposed power conversion system. First, the performance have been carried out in terms of current quality of both systems. Considering the proposed power conversion system composed by 5 106


(a) inverter 1

(b) inverter 2

(c) inverter 3

(d) inverter 4

(e) inverter 5

(f) details of interleaving modulation

(g) grid current of proposed power conversion system

(h) grid current of centralized power conversion system

Figure IV.9: Operating mode 5 current waveforms.

107


(a) conversion efficiency

(b) THD

(c) power losses

(d) switching frequency

Figure IV.10: Characteristics of centralized inverter topology (a) and of interleaved inverters topology (n=5) (b).

Figure IV.11: Efficiency of centralized inverter topology (a) and of interleaved inverters topology (b) composed by different number of units. units (n=5), when the nominal peak value of grid current (707.1 A) is imposed, only mode 5 is admissible. Figure IV.9(a), IV.9(b), IV.9(c), IV.9(d) and IV.9(e) show the current waveforms for each unit during the operating mode 5. Reference currents and the switching frequency of the units are set to 141.4 A and 2.73 kHz, respectively. In particular, fig. IV.9(f) shows the details of currents of the single units and their sum, when the interleaved modulation is adopted. The grid currents of both proposed and centralized power conversion system are depicted in 108


fig.s IV.9(g) and IV.9(h), respectively. The THD values of grid currents are equal to 2%. In order to achieve the same THD value, it has been necessary to adopt a switching frequency equal to 9.95 kHz for the centralized inverter. Several tests have been performed to validate the optimal power sharing algorithm. The achieved results confirm that the proposed solution allows improving the efficiency of the whole PV system, with respect of centralized inverter solution. The results have been obtained adopting M =32 and N =5 in the implementation of optimal power sharing algorithm. In particular, fig. IV.10(a) shows the comparison between efficiencies of the proposed topology, with n=5, and of the centralized one working in the same operating condition in terms of current THD and required power (fig. IV.10(b)). Moreover, it is possible to notice that the number of activated VSI decreases, as the actual power reduces because the optimal power sharing algorithms disable step by step power units, in order to reduce the impact of Pct . As shown in fig. IV.10(c), the proposed power conversion system allows to achieve a strong reduction of power losses with respect to the centralized solution. In particular, the conduction power losses are approximately the same, whereas the constant power losses, function of the modulated units, and the switching losses decrease. The switching frequencies of the proposed topology and of the centralized one are depicted in fig. IV.10(d). In details, the switching frequency of the proposed power conversion system decreases with the increasing of number of the modulated units. Further, the maximum efficiency points of the proposed solution are characterized by reference current of each unit equal to the grid reference current divided by the number of the modulated units. Afterwards, the improvement of the conversion efficiency of proposed system with respect to centralized solution has been evaluated also for different values of n (2, 3, 4 and 5), as shown in fig. IV.11. It is possible to notice that as bigger the number of the units is, as the overall conversion efficiency increases. However, after n=4 the more complexity of the system, due to increase of the number of VSI units, is not well balanced by the improvement of the values of conversion efficiency. In fact, the improvement of efficiency in the case of n=5 is quite negligible with respect to case with n=4. In the case of n=3, the efficiency curves, shown in fig. IV.12, of the two systems have been evaluated also with different power devices, SKiiP1013GB172-2DL V3 for the centralized solution and SKiiP513GB172-3DUL V3 for the proposed topology.

IV.4.2

Low power test-bench

A complete simulation, including PV generator, power electronic converters, passive components and ac-line generators, has been arranged both for classical and proposed converter topology. In particular, 185.13 W, 36.3 V PV modules have been considered; parameters of the centralized and proposed power converters are shown in Tab. IV.3 and Tab. IV.4. 109


Figure IV.12: Efficiency of centralized inverter topology (a) and of interleaved inverters topology (b). Pn,c

47.21

[kW]

Vdc,c

617.10

[V]

|vg | ∗ ig,n

148.36

[V]

106.07

[A]

Lf,c

0.60

[mH]

Table IV.3: Parameters of Centralized PV System. Pn

15.74

[kW]

Vdc

617.10

[V]

|vg | ∗ ig,n

148.36

[V]

35.36

[A]

Lf

0.40

[mH]

Table IV.4: Parameters of Single VSI Unit of Proposed Solution. Figures IV.13(a) and IV.13(b) the grid current waveforms for the centralized and for proposed solutions respectively show, when the nominal peak value (150 A) of the grid current is imposed. In this operating condition, the THD of the grid current for both systems is equal to 2%. To achieve this result, centralized inverter has to work at 9.9 kHz of switching frequency, while each VSI of the proposed solution works at 4.2 kHz. Figure IV.13(c) shows the details of the interleaving modulation of three VSIs. A numerical analysis has been carried out to verify the increment of efficiency achieved with the proposed conversion system. To evaluate power losses, the characteristics of Mitsubishi power modules PM100DSA120 and PM300DSA120 have been respectively considered for the proposed solution and the centralized one. In

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110


(a) centralized power conversion system

(b) proposed power conversion system

(c) details of interleaving modulation of proposed solution during operating mode 3

Figure IV.13: Grid current waveforms

Figure IV.14: Numerical results: (a) efficiency of centralized inverter topology; (b) efficiency of interleaved inverters topology. particular, conduction and switching power losses have been calculated by means of the device characteristics reported in their datasheets. Control circuit power losses have been imposed equal to 70 W for each single VSI unit and 180 W for the centralized system. Several tests have been performed, and the achieved results confirm that the proposed solution allows improving the efficiency of the whole PV system with respect of centralized inverter solution. In particular, Fig. IV.14 shows the comparison between efficiencies achieved with the proposed topology 111


Power[%]

inverter 1

inverter 2

inverter 3

5

7.5A @ 15.5kHz

10

15.0A @ 15.5kHz

20

15.0A @ 15.5kHz

15.0A @ 7.3kHz

30

22.5A @ 7.3kHz

22.5A @ 7.3kHz

40

20.0A @ 4.4kHz

20.0A @ 4.4kHz

20.0A @ 4.4kHz

50

25.0A @ 4.2kHz

25.0A @ 4.2kHz

25.0A @ 4.2kHz

60

30.0A @ 4.2kHz

30.0A @ 4.2kHz

30.0A @ 4.2kHz

70

35.0A @ 4.2kHz

35.0A @ 4.2kHz

35.0A @ 4.2kHz

80

40.0A @ 4.2kHz

40.0A @ 4.2kHz

40.0A @ 4.2kHz

90

45.0A @ 4.2kHz

45.0A @ 4.2kHz

45.0A @ 4.2kHz

100

50.0A @ 4.2kHz

50.0A @ 4.2kHz

50.0A @ 4.2kHz

Table IV.5: Details of the operating modes of proposed solution. and for the centralized one. It is possible to notice that the number of activated VSI decreases, as the actual power reduces because the optimal power sharing algorithms disable step by step power units, in order to reduce the impact of Pct . Tab. IV.5 shows the details of the operating modes of the proposed configuration for several values of output power obtained considering a fmin = 2.0 kHz and ∆f =100 Hz.

IV.5

Experimental analysis

To verify the validity of the proposed PV converter system, a prototype in scale of the proposed power converter has been designed and manufactured (fig. IV.15).

IV.5.1

Experimental set-up

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Mitsubishi PM100DSA120 power modules have been used to implement the proposed power converter topology (fig. IV.15(b)). The centralized power converter has been implemented using the three VSI units in simple parallel connection. However, this approximation for the efficiency comparison of two systems is cautionary because the centralized inverter, implemented by PM300DSA120 modules, has lower conversion efficiency than the one of the solution with three paralleled VSIs. During the tests Lf and Lf,c have been equal to 5.0 mH and to 3.9 mH respectively. Programmable ac loads are used to perform the system load. The control algorithm has been implemented by means of a DSP modular sys112

IV.5 Experimental analysis

(a) scaled prototype

(b) power converters

Figure IV.15: Proposed power conversion system.

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®

tem of dSPACE . It has been interfaced with three modulation units (performed on CPLD board based on Altera max 7000), which implement the interleaving modulation technique (fig. IV.16(a)). In detail, the modulation unit of inverter 1 (CPLD master ) generates the synchronization signal, with period Ts , for the slave modulation units and, moreover, it is also used to run the DSP interrupt control task. Starting from the grid current reference space vector i∗g and the operating mode, the DSP performs the predictive control algorithm for each VSI unit. Through three digital input/output boards, it provides to the modulation units the SVM application times and the related sequences to be imposed in the next Ts taking into account the phase-shift for the interleaving modulation. Then, starting from the SVM application time, switching signals of each VSI are provided by the modulation units, as reported in §III.6.4. The experimental set-up structure of the control section is depicted in fig. IV.16(b).

IV.5.2


Figure IV.17(a) shows the load current when three VSI units are modulated. Figure IV.17(b) shows the details of the interleaved modulation for the operating mode 3 of proposed solution. when the current reference is equal to 18 A. In this operating condition, the THD of the load current for the both systems is equal to 3%. The switching frequency of the centralized inverter system has been set to 19.5 kHz, whereas the one of each VSI of the proposed solution has been equal to 4.9 kHz. Figures show the details of the interleaved modulation when mode 3 is adopted. Several tests have been performed to compare the efficiency of two systems. Voltech PM6000 power analyzers are used to measure the efficiency and to evaluate the

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113


(a) modulation units

(b) control structure

Figure IV.16: Experimental set-up.

(a) centralized solution

(b) operating mode 3 of proposed solution

Figure IV.17: Experimental results: load current. current THD. Control circuit power losses have been measured equal to 8 W for each single VSI unit and 24 W for the centralized inverter system. The experimental results for several operating conditions have been reported in Tab. IV.6. The performed tests have been made in the same operating conditions in terms of reference current, load values and dc-link voltages. Furthermore, for the ana∗ 0 S3x = (V.24) 0 if sign(ix ) ≤ 0 Thus, the inverter 3 voltage space vector can be yield as following: v ˜3 =

2 4 2 VDC3 (S31 + S32 ej 3 π + S33 ej 3 π ) 3

(V.25)

As example, considering fig. V.26(c), adopting the mode 4 modulation technique the states of the legs are (S31 , S32 , S30 )=(1, 1, 0), thus, the inverter 3 voltage space 153

CHAPTER V. Power converters for urban mobility

Figure V.27: Motor phase current during operating mode 5. 1

vector v ˜3 is equal to v32 = 23 Vdc ej 3 π . Moreover, V.26(d) represents the switching patterns of the three inverters. Finally, the imposition of the vectors v1∗ and v2∗ instead of vm1 and vm2 increase a bit the current ripple thought the motors. Details about this effect are shown in simulation and experimental results. V.2.4.5

Mode 5

Operating mode 5, (f1 6=0, f2 6=0, f3 6=0), is used to achieve the supercapacitor charge stabilization. In details, the supercapacitor bank is recharged by energy coming from battery banks (fig. V.25(e)). Hence, all inverters are commutated. The modulation strategy allows to keep constant to zero the average current through the motors and, at the same time, to have a current flow that recharges the dc-link capacitor of the inverter 3. With reference to the phase-1 current of the two motors (im1,1 , im2,1 ) and fig. V.27, the modulation patterns of the three inverters can be achieved by means of the following relations: if (im1,1 > 0 && im2,1 > 0)  ∗ v1 = v11 rise of im1,1 and im2,1 from 0 to imax v2∗ = v21  ∗ v3 = v31  ∗ v1 = v10 fall of im1,1 and im2,1 from imax to iL v2∗ = v20  ∗ v3 = v31  ∗ v1 = v10 fall of im1,1 and im2,1 from iL to 0 v2∗ = v20  ∗ v3 = v30 154

(V.26)

V.2 Multi-inverter electrical drive for double motor electric vehicles

if (im1,1 ≤ 0 && im2,1 ≤ 0)  ∗ v1 = v14 decrease of im1,1 and im2,1 from 0 to −imax v2∗ = v24  ∗ v3 = v34  ∗ v1 = v10 rise of im1,1 and im2,1 from −imax to −iL v2∗ = v20  ∗ v3 = v34  ∗ v1 = v10 increase of im1,1 and im2,1 from −iL to 0 v2∗ = v20  ∗ v3 = v30

(V.27)

where imax and iL are the current limits that define the recharging time of the supercapacitor bank and they have to be selected taking into account the current limits of inverters and motors. Moreover, the behaviour of the two motors can be non specular due to the differences of the motors parameters. V.2.4.6

Flowchart of the algorithm

The proposed power flows management algorithm allows respecting the power limits provided by the battery banks and regulating the state of charge of the supercapacitors. The flowcharts of the operating modes are reported in fig. V.28. In details, the flowcharts are based on the control of the supercap voltage Vsc that has to be kept in the interval: Vsc,min ≤ Vsc ≤ Vscmax

(V.28)

where Vsc,min and Vsc,max are the minimum and maximum admissible voltage of the supercapacitor bank. In particular, Vsc,min depends on the estimated energy usually recovered during the motor breaks, while Vsc,max depends on the rated voltage of supercapacitor. Moreover, the recharge action of mode 4 and mode 5 ∗ that represents the charging supercapacitor is regulated by means of a value Vsc voltage boundary.

V.2.5

Simulation results

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A numerical analysis, performed by using the SimPower System Toolbox of Matlab-Simulink , has been carried out in order to validate the proposed propulsion system. In particular, a complete simulation including electric sources, power electronic converters, traction motors and control has been arranged. The capacity value of supercap bank has been set to 6.6 F; as regards induction motors, the parameters are reported in tab. V.4. Figures V.29(a) and V.29(b) the duty cycles, designed to test all operating modes, for the traction motors 1 and 2 and their mechanical transients respectively show. 155


(a) Start and acceleration period

(b) Steady state period

(c) Deceleration periods

(d) Motors stop

Figure V.28: Flowchart of the power flows control of the vehicle. The motors accelerate up to 62 rad/s (0s < t ≤ 1.7s) and cruise for 1 s. After, the action of electric differential control has been imposed. Figure V.30 shows the steering angle during the duty cycle of the vehicle. On the basis of the Ackerman steering principle, the relative speed difference in the wheels is computed by using the data of the steering angle. Thus, the motor 1, connected to the outer wheel, accelerates up to 76 rad/s, whereas the motor 2, connected to the inner wheel, decelerates to 49.6 rad/s (2.7s < t ≤ 3.0s). The motors cruise for 1 s in the road corner and then the motor 1 decelerates to 62 rad/s and the motor 2 accelerates up to 62 rad/s (4.0s < t ≤ 4.3s). At the end of duty cycles, the motors cruise for 7.7 s (4.3s < t ≤ 12.0s), and decelerate to stop 156


rated power

1.1

[kW]

rated velocity

1405

[rpm]

rated current

2.65

[V]

mutual inductance

0.43

[H]

leakage inductance

0.04

[H]

stator resistance

7.5

[Ω]

rotor resistance

4.8

[Ω]

pole pairs

2 Table V.4: Parameters of the IM.

(a) traction motor 1

(b) traction motor 2

Figure V.29: Duty cycle and mechanical response (12.0s < t ≤ 13.0s). It is possible to notice the good path tracking achieved by means of a suitable closed loop traction control. During the time intervals 0s < t ≤ 1.7s, 2.7s < t ≤ 3.0s and 4.0s < t ≤ 4.3s the operation mode 2 is adopted in order to limit the supplied maximum power by battery banks. Moreover, to achieve a complete stabilization of the supercapacitor charge, the operating mode 4 (4.3s < t ≤ 12.0s) and mode 5 (13.0s < t ≤ 15.0s) have been performed during motors normal run and stop, respectively. Powers required by traction motors and their average values are respectively shown in figures V.31(a) and V.31(b). It is possible to notice power peaks during the acceleration of vehicle as well as during the action of electrical differential. According to operating mode 2, it is possible to limit the maximum power of battery banks as shown in figures V.32(a) and V.32(b). In particular, with reference to the waveform of the average power of battery banks, it is possible to notice that the value of power has been limited up to a constant value of 300 W in whatever operating condition. At the same time, high dynamic performance, in terms of speed response, have been guaranteed. These goals have been achieved by means of an optimal management of power boost of the supercapacitor bank (fig. V.33(a)). 157


Figure V.30: Steering angle during the proposed duty cycle.



Figure V.31: Power (a) and its average value (b) during the imposed duty cycle. The supercapacitor voltage during the entire vehicle duty cycle is reported in fig. V.33(b). It is possible to see that the supercapacitor voltage decreases during the accelerations of both motors because of provided power peaks; whereas the supercapacitor voltage increases during the intervals with constant speed (operation mode 4 ), during the regenerative braking (operating mode 3 ) and during the motors stop (operation mode 5 ). Furthermore, from fig. V.33(b) it is possible to notice that the proposed energy stabilization control allows to reach, at the end of the duty cycle, the same supercapacitor bank charging state of the beginning.

V.2.6


To verify the validity of the proposed propulsion system and its control, a scaled prototype of the traction drive has been designed and manufactured (fig. V.34). The power section is composed by three IGBT-based standard VSIs and one dcdc bi-directional converter interfaced with supercapacitor bank. The Mitsubishi PM100DSA120 power modules have been used to implement the power converters. The control algorithm has been implemented by means of a DSP modular system of dSPACE . It has been interfaced with three modulation units, which have been manufactured to generate the inverters modulation patterns: they have been

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®

158


(a) battery bank 2

(b) battery bank 2

Figure V.32: Power (a) and its average value (b) during the imposed duty cycle with the supercapacitor power boost.

(a) power

(b) voltage

Figure V.33: Supercap bank characteristics during the imposed vehicle duty cycle.

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implemented on CPLD board based on Altera max 7000. The modulation unit of inverter 1 generates the synchronization signal, with a period of 128 s, which is used to run the DSP interrupt control task. In particular, within each sampling time Ts , the DSP determines the necessary parameters to perform inverters modulation for the next Ts . These parameters, switching state vectors and their duty cycles, are transmitted to modulation units by means of a digital I/O board. On the basis of these parameters, the switching signals are generated by modulation units. Regarding the modulation of dc-dc bi-directional converter, the modulation unit of inverter 3 generates the switching signals receiving the switches states from digital outputs of dSPACE control system. Figure V.35 shows a picture of manufactured power unit. The supercapacitor bank is based on three Maxwell BPAK0020 modules (Tab. V.5) which have been connected in series to obtain the same value of capacity of the numerical analysis. The test system has been completed by two open winding 1.1 kW induction motors (Tab. V.4), fed by the cascaded inverters, and two programmable hysteresis brakes, equipped with

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®

159


Figure V.34: Picture of the proposed power unit. capacitance

20

[F]

rated voltage

15

[V]

maximum peak current

730

[A]

Emax

2.72

[Wh/kg]

Pmax

13.587

[W/kg]

Table V.5: Parameters of the Maxwell BPAK0020 supercapacitor module. flywheel (0.06 Kgm2 ), which have been used as mechanical load. The same motors duty cycles of the numerical analysis (figs. V.29(a) and V.29(b)) have been considered to analyze the performance of the traction drive. Figures V.36(a) and V.36(b) show the mechanical transient of the motors, when the supercap bank is used and the same dynamic performance are imposed. Figure V.37 shows the differential speed between the two traction rear wheels. First, the power flow control performance to limit the overloading of the battery banks during the motors start and electrical differential action has been analyzed. In particular, the powers of the inverters 1 and 2 and their average values are reported in figures V.38(a) and V.38(b) without the use of supercap bank. It is possible to notice that the inverters 1 and 2 provide power peaks during both the start and electric differential with the consequent overloading of battery banks. By means of the supercap boost control it is possible to limit the supplied power by the battery supplied inverters up to a constant value of 300 W. This condition allows avoiding the battery banks overload. Thus is reported in figures V.39(a) and V.39(b). Figure V.40(a) shows the power peaks provided by supercap bank 160


Figure V.35: Picture of the proposed power unit. during the mechanical transient of the motors. It is possible to notice the positive power peaks supplied to the drive during the start and electric differential steps. Thus, the supercap bank remains partially discharged as shown in fig. V.40(b). By means of the operating mode 4 and 5 as well as regenerative braking (mode 3 ), the supercap bank reaches the same charge state of the beginning at the end of the motors duty cycle, as demonstrated by the transient of supercaps voltage (fig. V.40(b)). The supercap bank current transient is depicted in fig. V.40(c). It is possible to see that the positive value of current correspond to supplied power to drive (operating mode 2 ), while the negative ones correspond to recharging of the supercapacitor bank (operating mode 3,4 and 5). Figures V.41(a) and V.41(b) show the currents of two motors during the operating mode 4 when an utilization of the 30% of zero sequence of inverters 1 and 2 is used. It has been verified that the supercapacitor recharge during the motors run has a low impact on the quality of the currents of the motors, but, at the same time, allows achieving a better stabilization action of the state of charge of supercap bank.

161




Figure V.36: Reference duty cycle (a) and speed response (b)

Figure V.37: Differential speed between the two traction rear wheels during the imposed vehicle duty cycle.

(a) Inverter 1

(b) Inverter 1

Figure V.38: Power (a) and its average value (b) during the imposed duty cycle without the use of supercap bank power boost.

162


(a) Inverter 1

(b) Inverter 2

Figure V.39: Power (a) and its average value (b) during the imposed duty cycle with the supercapacitor power boost.

(a) power (a) and its average value (b)

(b) voltage

(c) current

Figure V.40: Supercap bank characteristics during the imposed vehicle duty cycle.

163


(a) Motor 1 current

(b) Motor 1 current

Figure V.41: Operating mode 4.

164

Conclusions In this dissertation, high performance power conversion systems based on Voltage Source Inverter have been presented. New solutions in terms of power conversion structures and control strategies have been proposed. Both simulation and experimental results confirm the validity of the proposed solutions. In particular, the following research activities have been carried out: − non-linearity compensation technique for VSI; − parallel VSIs converter for photovoltaic applications; − multi-inverter electrical drive for double motor electric vehicles.

Non-linearity compensation technique for VSI A new method for the optimization of VSI performance is presented. The algorithm allows reducing the nonlinearity effects of a VSI, mainly due to deadtime, turn-on/off delays and voltage drops of power semiconductor devices. These nonlinearities increase the THD and the drop of the fundamental voltage waveform. The achieved results show that it is possible to reduce the non linearity effects by means of a recursive algorithm working at steady-state. Future improvements can be achieved extending the algorithm concept to the transient-state.

Parallel VSIs converter for photovoltaic applications A novel approach to parallel connected Voltage Source Inverter (VSI) for highpower photovoltaic application is presented. The proposed power conversion system allows achieving a conversion efficiency improvement in whatever operating conditions, replacing a centralized power conversion system by a number n of VSI units performed with interleaving modulation. An optimal power sharing algorithm with interleaving modulation have been developed with the aim to obtain considerably reduction losses. Both numerical results and the experimental ones 165


fully confirm the validity of the proposed power converter solution. Future developments are related to: − costs analysis; − evaluation of filter and transformer losses; − dead-time effect on the interleaving modulation.

Multi-inverter electrical drive for double motor electric vehicles The proposed propulsion system for double motor electric vehicles is based on three voltage source inverters, connected in the cascaded configuration. This set-up allows to interface two electrical machines to two battery banks and, also, to a boost supercapacitor unit. A suitable control allows optimizing power flows in whatever operating condition. In this way, dynamic performance are exploited but batteries are not overloaded. Besides, the traction control implemented on the proposed power unit allows to split traction torque and speed on the driving wheels, once the vehicle runs across a bend. Both a numerical and experimental implementation have been performed. All results confirmed the validity of the proposed set-up and traction control.

166

Appendix A

Space vector A.1

Introduction

Space vector representation and Clarke and Park transformations are widely used tools in high performances power electronics applications.

A.1.1

Space vector representation

The space vector, so called space phasor, is a mathematical tool used to describe three-phase systems [117] reducing the complexity of the system model. With the space vector, it is possible to describe a 6-variable system (three magnitudes and three phases of the system variables) in a complex variable mathematical structure (2 variables) by transforming a stationary circuit to a stationary reference frame in the Gauss plot (α-axis and β-axis orthogonal). The transformation allows to determinate the space vector (a) starting from the three-phase system variables (a1 , a2 , a3 , depicted in fig. A.1(a)), as shows in the following equation: a=

2 (a1 + a2 α + a3 α2 ) 3

(A.1)

2

where α = ej 3 π .

A.1.2

Clarke transform

Clarke transform is used to identify projection on an orthogonal stationary reference frame of the space vector a. In details, this transformation used the three-phase variables (a1 , a2 , a3 ) to calculate the two-phase orthogonal system 167

CHAPTER A. Space vector

(a) three-phase system

(b) Clarke transform

(c) Park transform

Figure A.1: Space vector transform.

components aα and aβ taking into account the following set of equations:  2 1 1   a = a − a − a α 1 2 3   3 2 2   !  √ √  2 3 3 aβ = a2 − a3  3 2 2        a = 2 (a + a + a ) 0 1 2 3 3 168

(A.2)

A.1 Introduction

where a0 is the homopolar component of the system. In many application this component is negligible or absent. Thus, eq.s A.2 become:  aα =a1    ! √ √   3 3 2 a2 − a3 (A.3) aβ =  3 2 2     0 =a1 + a2 + a3 Therefore, the space vector a is yield by means of the following equation: a = aα + jaβ

(A.4)

In fig. A.1(b), the transform principle is depicted. The orthogonal stationary reference frame is labelled with (α, β). The reverse transformation allows obtaining the three-phase system variables starting from the space vector a,      1  1 0 a1 aα 3 √   3 1  a2  = − 1  (A.5) 2 2√ 3  aβ 3 1 1 a3 a0 − − 2

A.1.3

2

3

Park transform

The Park transform allows to convert a fixed-axis representation (α, β) to a rotary reference frame (d, q). Assuming θ as the angle between the fixed and the rotational reference frame, the two-phase orthogonal system components ad and aq can be calculated starting from aα and aβ , as expressed in the following equations: ( ad =aα cos(θ) + aβ sin(θ) (A.6) aq = − aα sin(θ) + aβ cos(θ) The space vector a can be expressed as: a = ad + jaq

(A.7)

Figure A.1(c) shows the Park transform in the rotating reference frame (d, q). The vector in the rotating reference frame are transferred to a fixed reference frame by means of the reverse transform, as following: ( aα =ad cos(θ) − aq sin(θ) (A.8) aβ =ad sin(θ) + aq cos(θ)

169

CHAPTER A. Space vector

170

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Multi-Inverter Architectures for High Efficiency Power

Multi-Inverter Architectures for High Efficiency Power

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