Multi-layer Cross-point Binary Oxide Resistive Memory (OxRRAM) for Post-NAND Storage Application I. G. Baek, D. C. Kim*, M. J. Lee*, H.-J. Kim, E. K. Yim, M. S. Lee, J. E. Lee, S. E. Ahn*, S. Seo*, J. H. Lee*, J. C. Park*, Y. K. Cha*, S. O. Park, H. S. Kim, I. K. Yoo*, U-In Chung, J. T. Moon and B. I. Ryu Process Development Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd. * Devices Lab., Samsung Advanced Institute of Technology. San #24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyeonggi-Do, Korea, 449-711 Tel: 82-31-209-6234, Fax: 82-31-209-2729, E-mail:
[email protected] Abstract Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxRRAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array. Introduction As the PC driven memory market is gradually shifted to the consumer device driven one, the need for higher density and speed, lower power consumption, smaller form factor, and cheaper data storage gets drastically increased. Up to now, NAND is most successful for mobile compact storage application, while HDD is mainly used for massive bulky storage application. However, scaling limit is expected for NAND due to its retention problem, and HDD has inherent limitation regarding power consumption as well as form factor. As an alternative to increase memory density over the scaling limit, density multiplying technologies such as multi-layer and/or multi-level cell (MLC) structure have been proposed and under intensive study. The binary oxide resistive memory (OxRRAM) has many attracting points enabling it to be easily combined with these density multiplying technologies [1]. For examples, its simple cell structure, CMOS-friendly materials and low process temperature make it easy to add up another memory layer on top of the other ones. Even multi-level programming might be possible by controlling the set compliance current [2]. Also, 4F2 1D1R cross-point array structure can be realized due to its unipolarly programmable device properties. By combining multi-layer and 1D1R cross-point structure, memory density can enormously increase in the way already demonstrated in the multi-layer anti-fuse one time programmable ROM [3].
In this paper, three key technologies are taken into account to maximize memory density, which are shrinkage of the memory cell itself, stacking layers of 4F2 cross-point memory array, and rectifying elements to prevent cell to cell disturbance. Sub 100nm Size Active Cell In our previous work [1], we reported that programming current decreases as the cell size shrinks without much change in switching properties. To reduce the cell size, we developed a plug contact type bottom electrode (plug-BE) instead of a conventional planar bottom electrode. As shown in Fig. 1, plug-BE can effectively reduce the active memory area because memory switching only takes place within the current path which is defined by the bottom electrode. One can clearly see that relatively bright active memory area is well defined on top of the plug-BE while inactive area with larger grains is located outside of the plug-BE from the TEM images of a working cell in Fig. 2. With the plug-BE cell structure, we tested switching properties of the OxRRAM cells with as small as 50nm diameter, and found that sub 100nm size cells effectively reduce not only their operation current but also distribution of each resistance state. Fig. 3 shows that reset current keeps lower than 1.5mA with an average value of 0.8mA during cycling test. Although the average value is about 1/2 of that from a 0.2µm2 sized planar-BE cell, the maximum current value is around 1/5 because reset current distribution becomes sharper with the plug-BE structure. This means that the size of the control transistor or diode can be made 5 times smaller in the case of the plug-BE. Also Fig. 4 shows that the resistance distribution in each state is noticeably reduced with the plugBE structure. We think the reason for these improved cycling distributions is because smaller active memory area reduces the number of possible current paths in binary oxide such that formed current paths do not vary much while the cell is repeatedly switched on and off (See Fig. 5). Therefore, better memory performance is expected for the OxRRAM with smaller active cell area. As for the cell to cell current and resistance distributions, they do not look so different from one cell cycling distributions although we could not get enough number of data yet to give statistically meaningful result.
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The switching dynamics of a plug-BE cell is monitored with programming and reading pulses as displayed in Fig. 6. When 5ns set pulse and 2µs reset pulse are respectively applied, the cell can switch its resistance state to the other state within the pulse duration time. Set transition time is stably kept less than 5ns once the pulse voltage is higher than threshold voltage. Meanwhile, reset transition time varies depending on the off state resistance, and the reset pulse voltage needs to be within a certain operation range. Multi-layer Cross-point Structure Cross-point is an ultimate memory structure attainable as high as a few tens of Gb density with reasonable die size and design rule. However, density multiplying technique will be inevitable for higher density. The easiest way to multiply OxRRAM density is to perpendicularly stack electrodemetal/binary-oxide lines on top of the other lines as illustrated in Fig. 7 (a). This integration scheme needs only one additional mask per memory array layer. But repeated stacking is strictly limited by tight process margin and high film stress. In addition, a cell to cell disturbance cannot be avoided because there is no room for isolated diodes. On the other hand, plug-BE type cross-point scheme in Fig. 7 (b) is relatively free from these issues, and has many advantages mentioned in the previous section. In this case, 2 additional masks are necessary for stacking one additional memory array layer. We have successfully integrated 2-layer test array with 4×5 cross-point matrix as shown in Fig. 8. It is composed of one W metal line (M1), two electrode-metal/binary-oxide lines (M2, M3) and 2 plug-BE layers. Each metal lines and plugs are isolated with IMD oxides, and CMP process has been applied before binary oxide deposition. To check the interlayer interference, a cell in one layer is programmed on and off while monitoring the resistance change in the other cell located just below or above in the other layer. The results in Fig. 9 prove that there is no inter-layer interaction between the upper and lower layers regardless of each cell’s resistance state. However, there exists intra-layer interference without rectifying elements directly connected to the memory cells. Fig. 10 describes how leakage current paths make cell resistance misread. When the resistance was measured with all the unselected lines open, (3,3) cell, for example, has been changed from high to low resistance state after 3 neighboring cells were switched on because of the leakage path described in Fig. 10 (c). Theoretically this kind of misreading and misprogrammig issues can be avoided by proper biasing method, but the amount of necessary current becomes unreasonably large as memory density increases [4]. Accordingly, it is very important to find suitable rectifying elements to realize an ultra high density cross-point memory device.
Binary Oxide Diode The best candidate for the rectifying element is a Si-based diode since it is capable of high current density enough to operate an OxRRAM cell. However, Si-based diodes cannot be easily adopted for multi-layer stacking process because high temperature doped poly-Si process gives unbearable thermal budget to lower layers. As an alternative to the Sibased diode, prototype binary oxide diodes have been fabricated below 300oC to be assembled with OxRRAM cells as in Fig. 11 (a) [5]. Using NiO as p-type and TiO2 as n-type semiconductor, current density higher than 103A/cm2 and turn on threshold voltage around 0.7V has been verified. By directly combining the oxide diode with an OxRRAM cell, we could demonstrate that the cell module as small as 30×30µm2 works properly in forward direction while reverse current is well suppressed like Fig. 11 (c). But the current density still needs to be increased by a few orders for the oxide diode to be applied to reasonably small OxRRAM cells. Conclusion As one of the potential solutions to extend memory density beyond NAND Flash scaling limit, the multi-stack cross-point structured OxRRAM has been tested. We have promising results implying that the amount of one layer memory capacity can be added with simple 2-mask process without inter-layer or intra-layer interference. However, there still need further studies on a suitable rectifying module, 3-D programming and sensing scheme, and better memory materials. References [1] I. G. Baek, M. S. Lee, S. Seo, M. J. Lee, D. H. Seo, D.-S. Suh, J. C. Park, S. O. Park, H. S. Kim, I. K. Yoo, U-In Chung and J. T. Moon, “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses,” IEDM Tech. Digest, p. 587, 2004. [2] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D.-S. Suh, Y. S. Joung, and I. K. Yoo; I. R. Hwang, S. H. Kim, I. S. Byun, J.-S. Kim, J. S. Choi, and B. H. Park, “Reproducible resistance switching in polycrystalline NiO films,” Appl. Phys. Lett., vol. 85, p. 5655, 2004. [3] S. B. Herner, A. Bandyopadhyay, S. V. Dunton, V. Eckert, J. Gu, K. J. Hsia, S. Hu, C. Jahn, D. Kidwell, M. Konevecki, M. Mahajani, K. Park, C. Petti, S. R. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, “Vertical p–i–n Polysilicon Diode With Antifuse for Stackable FieldProgrammable ROM,” IEEE Elec. Dev. Lett., vol. 25, p. 271, 2004. [4] Yi-Chou Chen, C.F. Chen, C.T. Chen, J.Y. Yu, S. Wu, S.L. Lung, Rich Liu, and Chih-Yuan Lu, “An Access-Transistor-Free (0T/1R) NonVolatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device,” IEDM Tech. Digest, p. 905, 2003. [5] For a general oxide diode reference, see W. Y. Lee, D. Mauri and C. Hwang, “High-current-density ITOx/NiOx thin-film diodes,” Appl. Phys. Lett., vol. 72, p. 1584, 1998.
Authorized licensed use limited to: Samsung Electronics. Downloaded on August 25, 2009 at 23:46 from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: Samsung Electronics. Downloaded on August 25, 2009 at 23:46 from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: Samsung Electronics. Downloaded on August 25, 2009 at 23:46 from IEEE Xplore. Restrictions apply.
