Multi-level Switching of Triple-layered TaOx RRAM with Excellent Reliability for Storage Class Memory Seung Ryul Lee, Young-Bae Kim, Man Chang, Kyung Min Kim, Chang Bum Lee, Ji Hyun Hur, Gyeong-Su Park, Dongsoo Lee, Myoung-Jae Lee, Chang Jung Kim, U-In Chung, In-Kyeong Yoo and Kinam Kim Samsung Advanced Institute of Technology, San 14-1, Nongseo-dong, Giheung-gu, Yongin-si, Gyeonggi-do, 446-712, South Korea Tel) +82-31-280-9352, Fax) +82-31-280-9308, E-mail)
[email protected] Abstract A highly reliable RRAM with multi-level cell (MLC) characteristics were fabricated using a triple-layer structure (base layer/oxygen exchange layer/barrier layer) for the storage class memory applications. A reproducible multi-level switching behaviour was successfully observed, and simulated by the modulated Schottky barrier model. Morevoer, a new programming algorithm was developed for more reliable and uniform MLC operation. As a result, more than 107 cycles of switching endurance and 10 years of data retention at 85oC for all the 2 bit/cell operation were archieved. Keywords: nonvolatile memory, RRAM, resistive switching, multi-level cell, MLC Introduction A resistance switching memory is the most promising non-volatile memory candidate due to its low program/erase current, fast speed, and nano-scale operation characteristics. Among the various resistive change materials and structures, we proposed a bi-layered TaOx RRAM structure and realized its superior device reliability and performance in 1 bit operation [1,2]. Nevertheless, MLC operation is mandatory in order to achieve a high-density storage class memory beyond NAND flash [3]. In this paper, a triple-layered structure and an optimized programming method named ‘Constant Signal Pulse Programming (CSPP) are proposed for the highly uniform and reliable MLC operation which can be clearly understood by our modulated Schottky barrier model. Experimental A triple-layered TaOx RRAM device structure is composed of bottom electrode (BE)/TaOx/Ta2O5/top barrier layer/top electrode (TE), in which TaOx and Ta2O5 act as base layer and oxygen exchange layer, respectively. The TaOx layer was deposited by a reactive sputtering technique, and Ta2O5 layer was formed by a pulsed plasma oxidation process under an O2 ambient to control oxygen concentration in the film. In addition, a 1~2 nm-thick top barrier layer was inserted at the Ta2O5/TE interface in order to enhance MLC characteristics. The active area of our device is (500 nm)2. Result and Discussion Figure 1(a) and (b) show the typical resistance switching curve in DC sweep mode and its single-level cell (SLC) pulse endurance over 1012 cycles, respectively. Figure 2 (a), (b) and (c) display the in-situ high resolution scanning transmission electron microscopy (HR-STEM) images at pristine state, low resistance state (LRS) and high resistance state (HRS), respectively, in which, the LRS and HRS are formed in TEM apparatus, sequentially. It is directly observed that the resistive switching is originated from the formation and rupture of conducting path which is consisted of nano-sized Ta-rich oxide clusters in Ta2O5 layer. Figure 3 shows the AES depth profile of oxygen content in the Ta2O5 layer at various resistance states. This shows that the moving of oxygen ions to the deficient TaOx layer leads a LRS and returning of oxygen ions to Ta2O5 layer leads a HRS. In-situ HR-STEM observation (Fig. 2) and AES analysis (Fig. 3) results confirm that the SET/RESET operation in TaOx based RRAM is originated from the redox reaction of Ta-rich conducting path in Ta2O5 layer by transportation of oxygen ions (or oxygen vacancies) which correlate well with our previous reports [2,4]. Based on abovementioned results, an advanced theoretical 978-1-4673-0847-2/12/$31.00 ©2012 IEEE
model is built to understand the MLC operation. Here, the insulator volume (Ta2O5 layer) factor and consequent Schottky barrier modulation as a function of the external voltage are additionally considered (Fig. 4). The experimental I-V curves in Fig. 5(a) present that the off current was gradually decreased as a higher positive voltage (reset voltage) was applied, and is well consistent with the simulation results (Fig. 5(b)). In addition, the experimental pulse switching data depending on the reset pulse height (Fig. 6(a)) can also be reproduced by the switching model (Fig. 6(b)). These indicate that the degree of oxidation at the Ta2O5 layer can be controlled by the external reset-pulse height, resulting in the change of the resistance in almost-continuous level. In order to enhance the uniformity and reliability of multi -resistance states, we developed a new programming algorithm, named CSPP (Fig. 7). In CSPP algorithm, if the current level is out of the target range, constant reset pulses are repeatedly applied until the resistance level reaches the target range. Figure 7(c) shows the improved MLC operation results using the CSPP algorithm. Successful MLC operation needs the large on/off resistance window. To fulfill the requirements, we inserted a thin barrier layer at the Ta2O5/TE interface. It is possible that the layer blocks the background leakage current so that the on/off resistance ratio increases by decreasing the HRS current.(Fig. 8) Figure 9 shows the on/off ratio depending on the reset voltage with and without the barrier layer. The on/off ratio increases up to ~103 as the reset pulse height increases which is almost 50 times larger than the conventional structure. Moreover, the insertion of the top barrier layer improves the switching uniformity (Fig. 10), and suppresses the reset current below 20 μA by the control of the set compliance current (Fig. 11). Figure 12 shows the pulse endurance performance in 2 bits/cell operation using the CSPP, where the cell stably operates over 107 cycles for all the resistance levels. Figure 13 shows very uniform cell-to-cell distribution of resistance states where the smallest resistance window between levels is over 4 times, and the calculated BER (bit error rate) is below 10-6. Figure 14 shows the robust data retention of multi-level states. All the levels have good retention exceeding 10 years at 85oC. Table 1 summarizes multi-level switching characteristics of our RRAM device. Conclusion The resistance switching characteristics of triple-layered TaOx RRAM were investigated. The HR-STEM analysis directly shows the origin of resistance switching. The theoretical modeling successfully demonstrated the multi-level resistance switching behavior. Finally, with adopting the barrier layer and introducing the CSPP programming algorithm, the test device showed low reset current, over 107 switching cycles, 10 years data retention at a high temperature, and excellent uniformity for 2 bits/cell MLC operation. References [1] Y. B. Kim et al., Symp. VLSI Tech, p.52 (2011) [2] M. J. Lee et al., Nature Mater. 10, 625 (2011) [3] S. S. Shen et al., ISSCC, p.200-202 (2011) [4] J. H. Hur et al., Phys. Rev. B 82, 155321 (2010)
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Fig. 1. (a) Typical bipolar switching I-V curve, (b) the endurance of bi-layered TaOx structure.
Fig. 2. HR-STEM images of (a) pristine state, (b) LRS (set), and (c) HRS (reset). The Ta and O contents were confirmed by EELS.
Fig. 5. (a) Experimental and (b) calculated result of I-V curves for TaOx RRAM as a function of sweep voltage.
Fig. 8. Schematic illustration of barrier layer insertion effect.
Fig. 3. AES depth profile of Fig. 4. Equations for the Schottky TaOx RRAM at the various barrier modulation model. resistance states.
Fig. 6. (a) Experimental and (b) calculated result of pulse operations for TaOx RRAM as a function of reset pulse voltage.
Fig. 9. Modulation of on/off ratio in TaOx RRAM device with or without top barrier layer as a function of reset pulse voltage.
Fig. 7. The pulse input scheme of (a) conventional programming method and (b) CSPP method. (c) Comparison of MLC operation results without and with CSPP.
Fig. 10. Comparison of the switching Fig. 11. Reset current as a uniformity in TaOx RRAM devices function of the set compliance current. with various barrier layer.
Table 1. Summary of multi-level switching characteristics.
Fig. 12. Endurance performance in Fig. 13. Resistance distribution of Fig. 14. Data retention property of 2 bits/cell operation using CSPP. TaOx RRAM in 2 bits/cell operation. TaOx RRAM in 2 bits/cell operation.
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