Multiple-valued Programmable Logic Arrays With ... - CiteSeerX

Multiple-Valued Programmable Logic Arrays with Universal Literals Takashi UTSUMIt, Naotake KAMIURAt, Yutaka HATAj and Kazuharu YAMATOt

t

Mitsubishi Electric Corporation. 2-2-3, Marunouchi, Chiyodaku, Tokyo, 100, JAPAN.

$ Department of Computer Engineering, Himeji Institute of Technology. 2167, Shosha, Himeji, 671-22, JAPAN.

Abstract

Lei and Vranesic[7][8]and discussed in Refs.[S] and [IO]. A universal literal is a single-variable function and convert pvalued signals into pvalued signals. Universal literals have an ability t o manipulate more information than set literals. This paper introduces multiple-valued programmable logic array with universal literals and investigate what operator is the most suitable in the term of eliminating the array size among MAX, MIN, TSUM or TPRODUCT. The size (i.e. the number of outputs) of a universal literal generator[l2] (ULG for short) depends on the operator in the first-level array. Considering the size of ULG, this paper picks up four form PLAs: the MAX-of-TPRODUCT form, the MINof-TSUM form, the TSUM-of-TPRODUCT form and the TPRODUCT-of-TSUM form. It is shown that a upper bound of the array size is smaller than or equal to ( [logz plpw + p ( n - w)+ 1) x pn-l for pvalued n-variable functions. Experiments are done for 10000 randomly generated functions and some arithmetic functions to evaluate the array size. The results show that the MAX-of-TPRODUCT fform PLA is the most useful in eliminating the array size among the four form PLAs. This paper is organized below. Section 2 describes preliminaries to introduce multiple-valued PLAs with universal literals. Section 3 discusses some structures of the PLAs and shows a speculation for the upper bound of the array size. Section 4 shows the experimental results on randomly generated functions and some arithmetic functions. Section 5 concludes the technical results.

A universal literal is a single-variable function and has an ability to manipulate more information than a set lateral. The array size therefore could be eliminated b y using universal literal generators (ULGs for short) in programmable logic arrays (PLAs), compared to PLAs with set literals. This paper discusses what operator is the most suitable in the term of eliminating the array size. We find four solutions as the good operator structures t o eliminate the array size. A speculation of the upper bound of the array sizes is shown. Experiments are also done for randomly generated functions and some arithmetic functions. The experimental results show that the MAX-of-TPRODUCT form PLAs require the smallest array size.

1

Introduction

A multiple-valued very-large-scale-integration (VLSI) has attracted great interest in recent years as one of the most promising approaches for reducing interconnection complexity, both on-chip and between-chip. Multiple-valued logic design, however, requires much time and expensive costs because it is more complicated than that of binary logic circuits. As one of the circuit structures that succeed in overcoming this problem, multiple-valued programmable logic arrays (PLAs) have been studied by many researchers[l]-[6]. On multiple-valued PLAs, minimizing the array size is interesting because it reduces the chip area, the propagation delay and power dissipation. Generally, multiple-valued PLAs consists of literal generators, a first level array and a second level array[l]-[6]. The literal generator generates set literal functions. The signals of set literals and constants are connected to the first-level array. pValued set literal generators convert pvalued signals, 0, 1, and p - 1 into binary signals, 0 and p - 1. Universal literal function was introduced by

2

Let Q = { 0 , 1 , . . . , p - 1) be the set of pvalued logic values, and let X = ( z ~ , z Z , . . .,zn) be an input vector of n variables where zi takes on values from Q. A pvalued n-variable logic function f ( X ) is a mapping

"A,

163 0-8186-7910-7197$10.00 0 1997 IEEE

Preliminaries

Table 1: A universal literal (2 3 1 O),.

I o

2

1 3

(2310),12

2 1

3 0

where + is an ordinary addition. Note that De Morgan's laws hold for the logic system with TPRODUCT, TSUM and NOT and the logic system with MAX, MIN and NOT. A set literal zs is defined as follows: 2s = ifzES 0 otherwise,

("'

where a label S is a subset of Q . In the following discussions, decoders that generate set literals are called set literal generators (SLGs for short). A universal literal ( a0 a1 . . . a p - l ), is defined as follows:

),

=

a,,

where a o , a l , . . . , and a p - l E Q . [EXAMPLE 11 A four-valued universal literal (2 3 1 0), outputs the values shown in Table 1. (End of example)

3

Multiple-valued PLAs with Universal Literal Generators

Section 3 introduces multiple-valued PLAs with universal literals. The PLAs consist of universal literal generators, a first level array and a second level array. We have fl universal literals for pvalued logic. The number is too big to realize them in the PLAs. We can select some sets of ULGs to realize the PLAs. Figure 1 shows the set when we use MIN array as the

(2310),

(2333),.(3313),

=

.(3330),, (20OO),V(O300),

(2333),*(3313),

0 0 1 0 )=,

= (size of U L G ) x v +(size of SLG) x ( n - U) = peg, PlPU P(" - 4,

+

H2 = m. The width of PLA is equal to the number of product (or sum) terms on the logic expression. For the number of product (or sum) terms on the four forms with universal literals, the following theorem holds. [THEOREM 11 For the pvalued n-variable logic function f ( X ) implemented by the PLA with at least one ULG, the number of product (or sum) terms is pn-l or less. Proof : When we set the values of ( n - 1) variables ( 2 2 , 2 3 , . z), to ( b 2 , b 3 , . . ., b,) respectivcly, we can regard f ( x l , b 2 , b 3 , . . ., b,) as a single-variable function for the remaining variable 21,where ( b 2 , b 3 , . . ., b,) E

In the same way to Figure 1, we can show Figures 2, 3 and 4 on MAX, TSUM and TPRODUCT arrays. [EXAMPLE 21 The combinations shown in Figures 1, 2, 3 and 4 can implement (2 3 1 O)z, =

=

H1

first-level array t o realize any multiple-valued function.

(2310),

(2310),

(End of example) The size of ULG is equal to the number of signal lines emanating from the ULG. Their sizes are tabulated in Table 2. This table shows that TSUM and TPRODUCT operators are more suitable for eliminating the ULG size than MIN and MAX. Therefore this paper considers the following four expressions: .the MAX-of-TPRODUCT form, ethe MIN-of-TSUM form, ethe TSUM-of-TPRODUCT form, ethe TPRODUCT-of-TSUM form. In order to find the most useful PLA in eliminating the array size, we should deal with the PLA with ULGs and the PLA with mixture of ULGs and SLGs. Figure 5 shows the SLG when the operator in the first-level array is either MIN or TPRODUCT. Figure 6 shows the SLG when the operator is either MAX or TSUM. Their SLG sizes are same, p . Figure 7 shows a structure of the PLA with ULGs. Multiple-valued input variables are fed to ULGs or SLGs and output lines of them are inserted in the firstlevel array. No constant input is needed in the PLA because it employs at least one ULG. It is obvious that we can implement an arbitrary multiple-valued logic function by our PLA structure. Let the number of ULGs be U , then remaining ( n v) input variables are fed to SLGs in the pvalued nvariable m-output PLA. The following equations hold for the height of the first-level array, H I , and the height of the second-level array, Ha.

+

a1 . " a p - l

(2000),0(0100),

* ( 3 3 3 1 ),*( 3 3 3 2 ) , .

+

a0

=

o ( 0 2 0 0 ).o(

f:Qn-fQ. The operators NOT "-", MIN ((.",MAX "V" , TSUM "0" and TPRODUCT[ll] "*" are defined as follows: NOT : 21=(p-1)-21 MIN : 21 . 2 2 = m i n ( z 1 , 2 2 ) MAX : 21 v 22 = m a z ( z 1 , 2 2 ) : 21 0 z2 = min(z1 2 2 , p - l ) , TSUM T P R O D U C T : 21 * 2 2 = ~ U X ( Z 2~ 2 - ( p - l ) , O ) ,

(

(2310),

+

V(OOlO),,

164

s,

input variable

MIN

X-

ARRAY

Figure 1: ULG for the MIN array.

x x < 0 0 0 3 >x x < 0 0 2 0 >x < 0 0 3 0 >x x x < 0 3 0 0 >x x < 2 0 0 0 >x x

1

input variable

MAX

ARRAY

Figure 2: U L G for the MAX array.

I

ARRAY

Figure

4: ULG for

w s

a, )zl . z ? . a, )$, x p

. . . . .2;" * * 4 3 * . . . * Z,S", holds for any j ( j = 2 , 3 , . . a). x?

radix = p

' ( P - 1); ( P - 1)P

I ,

. ., b,) ' . a, )zl v 2 2 v 2 3 v . . . v x;" . . . a, ) z , 0 z$ 0 3$0. . .o32" n ?

.f(Zl, b 2 , b 3 , . (a0 a1 .

{bj}

for m = 1.

p"-l

= (H1+H2)xW 5 (HI H a ) x pn-1 = ([log2 PlPV P(. - w)

+

+ 1) x

pn-l

holds. Here, assume that the number of products (or sums) is a fixed number p n - l , then the upper bound, U B ( S ) , is the smallest under the condition w = 1, i.e.,

2. sum (MAX or TSUM) term

= (U0 a1 where Sj is the complement of

5

+

f(Zl,b2rb3," ',bn)

UB(S) 2

with respect to Q.

The above product (or sum) terms consist of set literals for xj ( j = 2 , 3 , . .).. and the universal literal for 21. It is clear that each of the (n - 1) set literals can be represented by a universal literal. If the (71 - w) variables are fed to SLGs, f(z1,b 2 , b 3 , . . . , b , ) can be represented with the above four forms. Since f ( X ) has pn-l

12 12 8

Let the array size of the PLA be S . Then,

1. product (MIN or TPRODUCT) term

=

ARRAY

Let the width of the PLA be W . From Theorem 1,

Assume that 2 1 is fed to one of ULGs and . ., b,) is expressed with the truth table shown in Table 3. Then f(z1, b 2 , b 3 , . . ., b,) can be represented by the following product (or sum) term. f ( z 1 ,b z , b 3 , .

where Sj = { b j )

TSUM

the TPRODUCT array

Q"-l.

= (ao a1 . . . = (a0 a1 . * *

I radix = 4 I

Level Array MIN MAX TSUM

t

--

Figure 3: U L G for the TSUM array.

FRODUCT

-

X-

x < 0 0 0 2 >x x x < 0 1 0 0 >x < 0 2 0 0 >x < 1 0 0 0 >x < 2 0 0 0 >x

(pog2

+ P ( n - 1) + 1) x

P-l.

The U B ( S ) is much smaller than the upper bound of the PLA with SLGs, (np+p-1) x (p-l)p"-l in Ref.[3]. Considering the minimal array size for a given pvalued function, the number of products (or sums) in the logic expression takes a value between 1 and pn-'. The following theorem holds between the number of ULGs,

single-variable functions and the sum (or prod-

uct) of such single-variable functions is equal to f ( X ) , the number of such product (or sum) terms is p"-' or less. Q.E.D.

U,

and the array width, W .

[Theorem 21 Consideir the PLA,1 with

VI ULGs and the PLA,2 with 212 ULGs, where w1 < " 2 . Let W,l (or Wv2) denote the smallest width obtained by assigning

165

MIN or TPRODUCT ARRAY

Figure 5: SLG for t h e MIN or T P R O D U C T array.

or MAX

ivariable n P u 4 - 1 x( 1 )

TSUM ARRAY

X

x(3)

fl f2

Figure 6: SLG for the MAX or TSUM array.

Table 3: P r o o f o f Theorem

n-1 variables

L....

Figure 7: Structure of t h e

1.

4 one variable

xn

4 P- 1

..........

0 .... 0 0

-I

pn-’lines

. )f(x1 ,b2,b3,

p-1 .... p-1 p-1

I

PLA w i t h ULGs.

Simulation on Random and Arithmetic Functions

Section 4 compares the array size S of four form PLAs: the MAX-of-TPRODUCT form, the MIN-ofTSUM form, the TSUM-of-TPRODUCT form and the TPRODUCT-of-TSUM form. Experiments are done on randomly generated functions and some arithmetic functions. We developed a heuristic minimization program for MIN-of-TSUM form PLAs[l2] and programs for the others, where we can easily know that the number of product terms on the minimal MAX-ofTPRODUCT form expression of f ( X ) is equal to the number of sum terms on the minimal MIN-of-TSUM form expression of f ( X ) and that the number of product terms on the minimal TSUM-of-TPRODUCT form expression of f ( X ) is equal to the number of sum terms on the minimal TPRODUCT-of-TSUM form expression of f ( X ) . Table 4 shows the simulation results for 10000 randomly generated functions by a pseudo random generator. In it, “Best pattern ” denotes the average of the smallest width a n d size obtained by assigning all the possible number of ULGs and “Size AV” (or “Width AV”) denotes the average size (or width) of the PLA. When the number of ULGs is three (w = 3), “Width AV” is the smallest. Theorem 2 guarantees this fact. When the number of ULGs is one (w = 1), “Width AV” is the largest and H1 is the smallest. Considering Table 4, the height HI can affect the size S stronger than the width W . Thus this result maintains that “Size AV” is the smallest in the case of w = 1.

...

..........

all possible number w1 (or w2) of ULGs for PLA,1 (or PLAv2). Then W,, 2 W,, holds. Proof : After assigning all the possible number w l of ULGs for PLA,1, we assign the number w2 the assignment of ULGs for PLA,2. We assign w 1 ULGs out of v2 ULGs to the same variables that which w 1 ULGs in the PLA,,1 have been assigned to. Then, for the remaining (w2 - w l ) variables, if we implement set literals by (w2 - w1) ULGs, W,, = W,, holds because the expression implemented with the PLAvl is equivalent to that implemented with the PLA,2. On the other hand, for the remaining (212 - 211) variables, if the ULGs are not used for t h e generation of set literals (i.e., if the (“2 - “1) ULGs output one of the p signals 0 , 1 , . . ., and p - l ) , W,, > W,, because ULGs give more information to the first-level array than SLGs. As a result, W,, 2 W,,, holds. Q.E.D. Thus, if w 1 < w2, W,, 2 W,, holds, clearly on the height of HI, Hvl < H v 2is also holds. Therefore, we should find the optimal w to obtain the minimal S for a given pvalued function.

166

Table 4: Results of the random simulation (10000 generated functions).

Next, we compare the size of the four form PLAs to implement of several four-valued arithmetic circuits. Table 5 shows the results. We obtain the results by assigning all the possible number v of ULGs for the PLAs. For every circuit, a PLA with the smallest array size is marked with ”#. Table 5 shows that the sum-of-product form PLAs have the advantage of eliminating the array sizes for 12 circuits. Especially, the MAX-of-TPRODUCT form PLA is the most useful in eliminating the array size among four form PLAs.

5

M. Imme and C. A . Papachristou: “Simplification of MVL functions and implementation via a VLSI array structure”, IEEE Proceedings of the 15th International Symposium on Multiple-valued Logic, pp. 242248 (1985). T. Sasao: “On the optimal design of multiple-valued PLA’s” , IEEE Tratnsactions on Computers, vo1.38, no.4, pp. 582-592 (1989). J. Yurchak and J. T. Butler: ‘‘HAMLET-an expression compiler / optimizer for the implementation of heuristics to minimize multiple-valued programmable logic arrays”, IEEE Proceedings of the 20th International Symposium on Multiple-valued Logic, pp. 14412 (1990). F. J. Pelayo, A. Lloris and J. Ortega: “CMOS currentmode multivalued PLAY’, IEEE Transactions on Circuits and Systems, ~01.38,no.4, pp. 434-441 (1991). K. V. Asari and C. Eswaran: “An optimization technique for the design of multiple-valued PLA’s”, IEEE Transactions on Computers, ~01.43,no.1, pp. 118-122 (1994). K. Lei and Z. G. Vranesic: “On the synthesis of 4valued current mode CMOS circuits”, IEEE Proceedings of the 21st International Symposium on MultipleValued Logic, pp. 147-155 (1991). K. Lei and Z. G. Vranesic: “Towards the realization of 4-valued CMOS circuits”, IEEE Proceedings of the 22nd International Symposium on Multiple-valued Logic, pp. 105-110 (1992). G. W. Dueck: “Direct cover MVL minimization with cost-tables”, IEEE Proceedings of the 22nd International Symposium on Multiple-valued Logic, pp. 58-65 (1992). G. W. Dueck and J. T. Butler: “Multiple-valued logic operations with universal literals”, IEEE Proceedings of the 24th International Symposium on MultipleValued Logic, pp. 73-79 (1994). Y. Hata and K. Yarnato: “Multiple-valued logic functions represented by TSUM, TPRODUCT, NOT and variables”, IEEE Proceedings of the 23th International Symposium on Multiple-valued Logic, pp. 222-227 (1993). T. Hozumi, T. Utsumi, N. Kamiura, Y. Hata and K. Yamato: “Design of MIN-of-TSUM form multiplevalued PLA’s using universal literals”, MultipleValued Logic - An International Journal, (in press).

Conclusions

In this paper, we discussed the most useful PLA with ULGs for eliminating the array size. First, we showed that the size of ULGs depends on the operator in the first-level array. The use of TSUM or TPRODUCT in the first-level array is more suitable for reducing the height of array. Then the four forms such as the MAXof-TPRODUCT form, the MIN-of-TSUM form, the TSUM-of-TPRODUCT form and the TPRODUCT-ofTSUM form are selected as the good solutions. A speculation of the upper bound of the array sizes is derived. The size is smaller than the size of PLA with set literals. We simulated the four form PLAs on randomly generated functions and arithmetic circuits. The results show that the sum-of-product form PLAs have the advantage of eliminating the array sizes for 12 circuits. Especially, the MAX-of-TPRODUCT form PLA is the most useful in eliminating the array size among four form PLAs. Consequently, multiple-valued PLA with universal literals has an advantage to reduce the array size, compared to the PLA with set literals. It remains as future studies to consider about the multi-level logic design for the logic expressions discussed here.

References PI

H.-L. Kuo and K.-Y. Fang: “The multiple-valued proapplication in modular design”, IEEE Proceedings of the 15th International Symposium on Multiple-Valued Logic, pp. 10-18 (1985). grammable logic array and its

167

Table 5: Array size to implement arithmetic functions

I

w43 1 3 1 2 1 1 1 31 558 w44 141 2 I l l 1 1 9 1 2618 number of * 12

168

540*

I

1

I

117

I

2574*

8