New Heterogeneous Multi-Chip Module Integration Technology Using ...

New Heterogeneous Multi-Chip Module Integration Technology Using Self-Assembly Method T. Fukushima, T. Konno, K. Kiyoyama, M. Murugesan, K. Sato, W.-C. Jeong, Y. Ohara, A. Noriki, S. Kanno, Y. Kaiho, H. Kino, K. Makita, R. Kobayashi, C.-K. Yin, K. Inamura, K.-W. Lee, J.-C. Bea, T. Tanaka, and M. Koyanagi Dept. of Bioengineering and Robotics, Tohoku Univ., 6-6-01 Aza Aoba, Aramaki, Aoba-ku, Sendai, 980-8579, Japan. Phone: +81-22-795-6906; Fax: +81-22-795-6907; E-mail: [email protected]

We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 μm were electrically connected by unique lateral interconnections formed crossing over chip edges with large step height. We evaluated fundamental electrical characteristics using daisy chains formed crossing over test chips which were face-up bonded onto the substrates by the self-assembly. We obtained excellent characteristics in these daisy chains. In addition, RF test chips with amplitude shift keying (ASK) demodulator and signal processing circuits were self-assembled onto the substrates and electrically connected by the lateral interconnections. We confirmed that these test chips work well.

brittle thin moving elements on their chip surface for sensing mechanical quantity such as pressure, accelerated velocity, gravity force, and so on. Thus, some MEMS devices are suited for face-up chip bonding without using TSVs. Our chip-on-wafer stacking method using self-assembly is suitable for the face-up chip bonding. In this paper, we describe a new heterogeneous multi-chip self-assembly method using aqueous liquid. In this selfassembly, we employed anisotropically etched Si chips targeting for MEMS such as acceleration sensors and passive devices such as coils. In addition, we developed a new method to form unique lateral interconnections that can provide conformal formation of metal layers crossing over chip edges and electrical interconnections among face-up self-assembled chips. The formation of the 3D lateral inter-connections crossing over thick chips is the technologically challenging. This paper demonstrates the formation of the lateral interconnections over 100-μm thick test chips.

Introduction

Self-assembly technology for LSI and MEMS chips

Recently, heterogeneous system integration involving CMOS, MEMS, optics, and biochips has attracted much attention due to its high functionality and potential applications. Fig. 1(a) shows a conceptual structure of a heterogeneously integrated MEMS-LSI module we have proposed. In order to realize the system module, we have developed new key technologies such as multi-chip fluidic self-assembly, lateral interconnect formation crossing over chips, high-density microbump formation, and passive device fabrication on a chip, as shown in Fig. 1(b). Compared with conventional robotic pick-and-place chip assembly, fluidic self-assembly methodology can dramatically increase production throughput, and additionally, production yield can also significantly increase because known good dies (KGDs) can be used. We have demonstrated for the first time that the self-assembly can be applied for 3D LSI fabrication based on chip-on-wafer stacking with through-Si vias (TSVs) (1), (2). The 3D integration has been of great interests since vertically stacked chips with a number of TSVs can increase packing density and improve LSI performance (3)-(5). By using 3D integration technology based on wafer-on-wafer stacking, we have previously fabricated prototype 3D LSI chips (6)-(9). However, 3D integration is not necessarily versatile configuration for all components. Taking MEMS devices for example, they have

Fig. 2 illustrates batch self-assembly process using a new multi-chip self-assembly machine we have developed for the first time. A multi-chip picking-up holder in the upper chamber can simultaneously transfer more than 500 chips with a size of 5 mm square. First, small volumes of aqueous liquid are coated on hydrophilic bonding areas formed on an 8-inch wafer and then a larger number of KGDs are roughly pre-aligned onto hydrophilic bonding areas on the 8-inch wafer. After that, the KGDs are released onto the bonding areas, and consequently, the many KGDs are quickly and precisely self-assembled onto the bonding areas by surface tension of the liquid. After evaporating the liquid at room temperature under ordinary pressure, these chips are directly and tightly bonded on the hydrophilic areas because these KGDs have hydrophilic SiO2 layer on their backside. Fig. 3 shows distribution of alignment accuracy in our self-assembly. Average alignment accuracy measured in a hundred of self-assembled Si chips was found to be approximately 400 nm. Many parameters such as liquid volume and liquid surface tension affect the alignment accuracy of self-assembly. Fig. 4 shows the dependence of alignment accuracy on chip sizes. Even small Si chips (1 by 1 mm) can be precisely self-assembled onto bonding areas. The liquid concentration scarcely affects the alignment accuracy, whereas the liquid volume strongly affects the alignment

Abstract

accuracy. A very high alignment accuracy of within 100 nm was obtained with a liquid volume of 0.2 μL. In general, Si chips can not be tightly bonded on SiO2 layers formed on polymeric substrates due to its rough surface. CMP processes can afford highly smooth surface of the bonding areas to accomplish direct bonding. The Ra roughness of 4.6 Å significantly reduced to below 1 Å after 1-min CMP, which enable Si chips to tightly bond to the polymeric substrates. Liquid concentration strongly affects on shear bonding strength as shown in Fig. 5. By optimizing the alignment/bonding conditions, multi-chip self-assembly with aqueous liquid can be realized to give high alignment accuracy and high bonding strength. Process sequences for self-assembly of test chips with cavity structure onto substrates are schematically shown in Fig. 6. The test chips with various types of cavities were formed by standard photolithography techniques and anisotropic etching, followed by deep RIE to create precisely defined 2- or 3-mm square chip sizes. The substrates have a number of plateaus having microchannels for liquid evaporation. The photomicrographs of the resulting anisotropically etched chip with various cavities are shown in Fig. 7, where cavity structure seems to hardly affect alignment accuracy. As seen from Fig. 8, the test chips with cavities were precisely aligned and tightly bonded onto the hydrophilic surface of the plateaus having the channels. Fig. 9 schematically illustrates self-assembly of test chips with microbumps onto a polyimide substrate and shows captured frames from the movie of the self-assembly event. The chips are also precisely aligned and bonded upside down through the microbumps by liquid surface tension. Fig. 10 shows fabricated passive components of an inductor and a capacitor. These chips can be also self-assembled onto substrates in a similar manner.

Test chip evaluation with the lateral interconnections Process flows for test chip fabrication using self-assembly and lateral interconnections crossing over high-step LSI chips by Cu electroplating are schematically shown in Fig. 11. 100-μm-thick test chips are self-assembled onto Si substrates, and then, a SiO2 dielectric and Ta/Cu seed layers are deposited on the chips by using Plasma CVD and RF sputter, respectively. After thick photoresist patterning, a Cu metal layer was selectively electroplated, followed by the resist removal. As shown in Fig. 12, conformal Cu lateral interconnections were successfully formed crossing over the test chips along chip sidewall. To evaluate the optimal conditions for the lateral interconnections crossing over thick chips, a test chip structure in Fig. 13(a) was employed. Normal distribution plots for measured lateral interconnection resistances are shown in Fig. 13(b). We confirmed that the lateral interconnections were electrically connected even at the chip edges with a large step height, although the lateral interconnection resistances showed a relatively large distribution. Fig. 14(a) depicts a layout

pattern and a cross-sectional structure of daisy chains which were used for the evaluation of lateral interconnection resistances and via contact resistances. The Cu lateral interconnections are connected through vias by Al wiring in daisy chains. Fig. 14(b) shows the I-V characteristic of the lateral interconnection. We obtained an excellent characteristic with linear relation between the current and the voltage. Fig. 14(c) shows the lateral interconnection chain resistance derived from the linear I-V characteristic. It is obvious that the Cu chain resistance is in proportion to the Cu chain length. Fig. 15 shows a block diagram and a photomicrograph of self-assembled RF test chips with an ASK demodulator and a signal processing circuits. This module was designed for wireless biomedical sensor/stimulation applications. The test chip size is 2.5 by 2.5 mm. These test chips were bonded onto a flexible substrate using our self-assembly method and electrically connected by the lateral interconnections crossing over the chips. Fig. 16 shows measured waveform of the ASK demodulator and signal processing chips. The basic functions of these test chips are to demodulate ASK and clock signal in the Rx input from an antenna so that it reproduces digital control signals (Data, /RxOut) and feeds it to the operation clock (Clk/10) for a stimulation module. The upper signal is RxOut of the demodulator, and the lower is inversed RxOut of the output signal of the processing test chip. With this function test, we confirmed that stable signal processing was performed between the RF test chips electrically connected by the lateral interconnections.

Conclusions We have developed a new heterogeneous integration technology to fabricate highly integrated system modules using fluidic self-assembly and unique lateral interconnect techniques. We obtained chip alignment accuracy of approximately 400 nm by our new multi-chip self-assembly machine. Furthermore, ASK modulator and signal processing LSI chips with the lateral interconnections were successfully fabricated and their basic operation was also confirmed.

Acknowledgments This work was performed as a part of the ‘‘Highly Integrated, Complex MEMS Production Technology Development Project’’ supported by NEDO (New Energy and Industrial Technology Development Organization).

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