Non-recursive Cascaded Integrator-Comb Decimation Filters with Integer Multiple Factors. Youngbeom Jang, Sejung Yang. Dept. of Information Electronics ...
Non-recursive Cascaded Integrator-Comb Decimation Filters with Integer Multiple Factors Youngbeom Jang, Sejung Yang Dept. of Information Electronics Engineering, Ewha Womans University 11- 1 Daehyun-Dong, Seodaemun-Ku, Seoul, Korea e-mail: ybjang@mm. ewha.ac.kr
Abstract In this Ixlper. multi-rate non-recursive architectwe for Cascaa'ed Inte,Q-ator-Comb(CIC) decimation .filters with an a r b i t r q factor is proposed. The CIC filters are widely tsed in high speed wireless comnztrnicution system since they / m e multiplier-less and nztilti-rate law-paver structure. Even conventional non-rectrsive CIC structure is multi-rate, this architectire can be structured only in case of Mth paver-of two decimation fmtor. This paper proposes that non-t-ectrsive CIC jlters with any decimtion factors of product form cur? be stmctired with milti-rate low-paver architectire. Paver- conslimption of the proposed architectwe is cornpaved with that of the conventionul non-recursive architecture.
1. Introduction In application of the wireless communication products, high-speed and low-power decimation filters have been highly need4 and many architectws for those requirements are introduced based on current semiconductor technology. Commercial decimation filter products consist of several kinds of cascaded filters and their characteristics are defined by independent filters. Among those cascaded decimation tilter block, CIC filters generally locate as the first stage. CIC filters are proposed by E. B. Hogenauer in [I] which also includes research for register grow of the recursive structures. CIC decimation filters are highly focussed in these sense: I ) no multiplication, 2) regular structure, 3) low-power architecture through location change with the down sampler. CIC filters.. has the following recursive and non-recursive representation.
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In the above equation, N and k are defined as the decimation factor and the filter order, respectively. As shown in above equation, the CIC filters can be implemented with recursive forms or non-recursive forms. When the non-recursive structure is implemented directly in terms of equation (I), it needs kw-1) additions and UN-I) delays. Also. direct implementation does not allow slower speed operation by stage separation. In order to overcome these. disadvantages. factoring method of the system function was propod.[5][6] Through the location change of the down samplers. decimation filters are separated into multi- stages with multirate processing. Even this tactoring method is eficient. it has constraints that the decimation factor should be power of 2. In order to loosen this constraints. we propose a new architecture. Once decimation factor is factored into x applied. Our integer multiple. our proposed architecture can I proposed non-recursive architecture has multi stages, and each stage operates with different speed.
2. Non-recursive architecture with integer multiple factors In case that the decimation factors are power of 2. the non-recursive CIC filter has the following system function of the form
Since system hnctions are factored, structures can be implemented with cascaded form. Furthermore, location of the down samplers can be exchanged with factors of the system function. It results in multirate processing.
In this section we propose a new architecture for non-recursive CIC filters with integer multiple Pxtors. Let's assume that the decimation factor can be factored into 2 P 3 g 5 R 7 S 1 1 T . - . where 2. 3. 5- 7, I I are the numbers which can not be factored except for itself For elample, decimation factor of 180 is factored into 2. 2. 3, 3, and 5. For notational convenience, we discuss in case that the decimation factor is 2'SQSR as shown in Fig. I .
Through the above step. it is noticed that families of same factors are grouped as shown in Fig. 2(b). In the second step. three individual families are cascaded into P, 0, and R stages, respectively. To do so, the first family of decimation filter with factor of 2' is represented as
H( 2 )
Fig. 1.
Decimation filter and down sampler
in case that decimation factor equals 2 P 3 Q 5 R In the first step, we separate down samplers with 2'. 3', and 5 R , respectively. After then. we try to separate stages into family of 2'. and respectively. The system function of the Fig. 1 can be represented as
sQ,
sR,
TI.P-- I(2) =
{
= HI,,(2)
After the system h c t i o n of H l ( z ) is separated into
Hl,(z)T,,(z2), then the
Since system hction of the T I is a function of z'" in the above quation (3), it can be interchangeable with d o m sampler of 2'. After then the system function of T,
T,,(z') is a h c t i o n of z2,
Sequentially, it can be interchanged with following down sampler of 2. By repeating these process with P times, the first family is separated into P stages as shown in Fig. 3(a). The second and third families can be also separated into multi-stages in exactly same manner as
becomes a function of z as shown in Fig. 2(a). System hnction of T I of the Fig. 2(a) can be represented as
By applying m e method with above equation. the Fig. 2(a) results in Fig. 2(b). Since the system function of T2 is a function of z: and does not include any factor except for 5, we define it as H J z ) .
(b)
Fig. 2. (a)After location change of decimation factor of 2', (b)After location change of decimation factor of 3
As shown in Fig. 3(a)-(c). it i.s noticed that the overall
stage number of P+@R fxtors.
is same as the number of prime
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3. Estimation of power dissipation As an example of the proposed architecture synthesis. we consider the decimation filter with factor +I80 and order k 3 . The N is factored into 2'3'5. As the first step, the system hnction is grouped into three families of H , ( z ) , H z ( z ) and Hs(z) as
(c)
Fig. 3. (a) Stage separation of 2'' family, (b) Stage separation of 3Q family, (c) Stage separation of sR family. In the third step. the filter structure of each stage is derived into a cascaded fashion. In Fig. 3(a)-(c), all individual filters have double subscript. If the prior subscripts are m e . then corresponding filter structures are the same. Consequently, it is sufficient to define structures of Hl,(z), H2,(2) and H31(z).The followings are the representation of those filters which are either in recursive or in non-recursive form. i.e.,
In the second step> these three families of H , ( z ) , H2 (2) and H:,(z) are separated into multi-stages as
In this paper. non-recursive structures are preferred to be realize NI1(z),the required number of the additions is X. Similarly. the number of additions needed to implenicnt I I : l ( z ) and H:,,(z) are 2k and 4k respectively. This implies that the filter having the in the nuinorator in (9) requires (n-l)k term of z-' additions. In addition. the overrlll delav is exactly same as the number of additions. implemented regarding to (9).
STAGE : OPERATION SPEED : ADDITION NUMBER : POWER ESTIMATION:
In this example. overall tilter structure consists of 5 stages
as shown in Fig. 4. If we assume the operation speed of the first stage is 1, then those of the following stages are 1/2. 1/4. 1/12. and 1/36; respectively.
I
2
3
4
I
112
1 I4
1/12
5 1/36
3 3
3
6
1.5
1.5
6 0.5
0.33
I2
Fig. 4. Proposed non-recusive CIC architecture for decimation factor of 180 and filter der of 3.
132
90 80
z E
$
/ O P r o D o s e d architecture
t
70 60
50 40 30
20 10 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DECIMATION FACTORS
Fig. 5. Power estimation of the proposed and conventional non-recursive CIC architectures. Now. for comparison’s sake, we estimate the power dissipation of CIC filters which decimation factor is v q i n g from 2 to 32, and order k is 3. Dynamic power dissipation is expressed as Pd,,u= Pt CL Vid fclk, which is the dominant source in digital CMOS circuits. Here. P, is the probability of the transition, CL is the loading capacitance. and fclk is the clock frequency. To calculate the relative power dissipation, this equation can be modified into
-
pdiao =( ‘&s
-
operotion speecix oren)
(14)
We assume that the weight of area is simply total number of additions of the given stage, and operation speed of the first stage is 1. The area required for the down samplers is neglected since it is relatively small. Fig. 5 shows the comparison of the power estimation between the conventional and the proposed filter structure. For conventional structure. there are two cases. Such that one has decimation fktor tvhich is power of 2, and the other is not. Average power estimation of the one stage structure is 40.6. And those of the hvo. three. and four stage structure are 11.5. 7.3. and 5.8, respectively. Since decimation factors of 2. 3, 5. 7, 11. 13. 19. 23. 29. and 31 are not factored power estimation of the proposed architecture has no advantage with respect to the conventional one.
4. Conclusions An efficient multirate architecture for non-recursive CIC tilter is proposed. It is shown that once decimation factors are represented by the multiplication of prime numbers. our proposed cascaded CIC filter architecture can be applied. Since, in proposed architecture. down samplers locate at each stage, operation speed decreases as stage goes on. According to the simulation results, compared to the conventional structure, our proposed filtering process provides the significant
reduction of power dissipation. As consequence, it can be concluded that the proposed filter structure has great benefit to be applied in high-speed wireless communication systems.
References E. B. Hogenauer, “An economical class of digital filters for decimation and interpolation” IEEE Trans. Acoust., Spec/& Signal Processing, vol. ASSP-29: no. 2. pp. 155-162. April 1981. A Y. Kwentw Z. Jiang and A. N. Willson, Jr., “Application of filter sharpening to cascaded integercomb decimation filters.” lEEE Trans. Signal Processing, vol. 45, no. 2, pp. 457-467. Feb. 1997. H. J. Oh. S. Kim, G. Choi. and Y. H. Lee, “On the use of interpolated second-order polynomials for efficient filter design in programmable downconversion” IEEE Jozirnal on selected weas in commmications, vol. 17. no. 4. pp. 551 - 560: April 1999. H. K. Yang and W. M. Snelgrove. “High speed polyphase CIC decimation filters,” IEEE Intetwatioml Svtiposiiim on Circuits and Svstetns, I’ohitne 2. pp. 229-232. 1996. Y. Gao. L. Jia, and H. Tenhunen “An improved architecture and implementation of cascaded integratorcomb decimation filters,” IEEE lntermtionnl ASIC 1 SOC Confet-encee.pp. 391-395, 1999. Y. Gao. L. Jia, and H. Tenhunen. “A pktial-polyphase VLSl architecture for vely high speed CIC decimation IEEE Raci$c Rim Conference on filte4” cotntnzmicntiotw, conpirters and signal pt-oresing, pp. 3 17-320, 1999.
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