Novel Spectral Methods for Built-In Self-Test in a System ... - CiteSeerX

Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment Ashish Giani∗ Shuo Sheng and Michael S. Hsiao† Vishwani D. Agrawal Intel Corporation Dept. of ECE, Rutgers University Bell Labs Hillsboro, OR 97124 Piscataway, NJ 08854 Murray Hill, NJ 07974 [email protected]

hshuo, [email protected]

Abstract This new method of built-in self-test (BIST) for sequential cores on a system-on-a-chip (SOC) generates test patterns using a real-time program that runs on an embedded processor. Alternatively, the same program can be run on an external low-cost tester. This program generates patterns using circuit-specific spectral information in the form of one or more Hadamard coefficients. The coefficients are extracted from high fault-coverage compacted pattern sets. When an embedded processor is available on SOC, the overhead is negligible. Also, sequential cores are tested in the functional mode, avoiding activation of nonfunctional timing paths. We present experimental results to show that for hard to test circuits, with any given test time, spectral patterns provide significantly higher fault coverage than weighted-random patterns.

I

Introduction

Improvements in VLSI technology in terms of gate density and increased clock speeds have made VLSI testing an integral part of chip design. Technology advances are resulting in higher operating speeds, and test equipment will fall short on keeping pace with this growing speed of circuits, thus preventing “at speed” test and measurement. Consequently, built-in-self-test (BIST) has emerged as a promising solution to the test problem. In addition, the recent trend of core-based system-on-a-chip (SOC) design hampers testability of embedded cores due to limited accessibility. This makes BIST the most suitable methods for testing embedded cores in the SOC environment. The main components of a BIST system are a test pattern generator that applies a sequence of patterns to the circuit under test (CUT), a response compacter that compacts the responses into a signature, and a signature comparator that compares the signature to a faultfree reference value. Due to their low hardware costs, BIST based on random patterns is very attractive. Linear feedback shift registers (LFSRs) are commonly used as ∗ Formerly with Dept. of ECE, Rutgers University, Piscataway, NJ 08854 † Supported in part by an NSF Career Award, under contract CCR-0093042.

[email protected]

pseudo-random test pattern generators in BIST schemes. They have a simple structure and can also be used as output response analyzers, thereby serving a dual purpose [1]. However, this technique generally results in large test sets [2]. Besides, the quality of the LFSR-generated test set depends on the CUT [3]. This is because some signals in the circuit may not be set to specific logic values using pseudo-random vectors, making faults on those signals hard to detect. Weighted random patterns have been found to yield better fault coverage in circuits that contain such random-pattern-resistant faults [4–8]. In these approaches, the probability of obtaining a 0 or a 1 at a particular input is biased towards detecting random pattern resistant faults. Weighting the pseudo-random patterns [7, 9] is done using counter-based schemes [10, 11] or performing bit-fixing (pattern mapping) [12]. The disadvantages are additional area and delay overheads. One way to overcome these drawbacks is to design the LFSR by selecting good seed and feedback polynomial [13–17]. However, test sequences with acceptable test length and fault coverage are obtained at the expense of area overhead required to store seeds. Also, the complexity of computation of the seeds [17] rapidly increases with the number of primary inputs. Efficient hardware pattern generators [6,8] often round-off optimal weights, hence producing patterns that are sub-optimal for certain circuits. In sequential circuits, faults may need a biased internal state in addition to biased input values, making it more difficult to obtain a good set of weights. Deterministic BIST techniques such as stored pattern testing involve the application of specific test vectors, each providing an increase in fault coverage. However, a high cost is associated with the storing of the large number of patterns. Walsh and Rademacher-Walsh function analyses have been proposed in the past [18, 19] only for response compaction. Their present application in vector generation is novel and has significant advantages not perceived before. An embedded controller or processor on an SOC makes it possible for the processing unit to generate patterns to test the rest of the chip [20–24]. This alleviates the need for additional hardware such as LFSRs to test the other embedded cores/peripherals. For testing embedded processors by some proposed methods [20, 21] F random op-

erations and operands are generated to test ALUs within DSP cores. Random test patterns can also be generated by an embedded processor [22, 23]. Deterministic BIST for accumulator-based processors to avoid instructionimposed constraints has also been proposed [24]. In this paper, we propose a new spectrum-based BIST technique for SOC’s with an embedded processor. This spectrum-based testing method generates vectors by using the information provided by each core designer. We analyze the given information of an embedded core to obtain a spectral characteristic for the input test patterns [25,26]. To do this, we view the core as a digital system that is described by input-output signals. A signal in a digital (or analog) circuit is a function of time. Any such function can be represented and reproduced in the time-domain, using its frequency-domain spectrum. A random signal (which is noise-like) contains a very wide spectrum. By properly restricting the spectrum, we can generate signals that are more useful than random signals. However, the determination of the spectrum should be based upon the “usefulness” criterion. In the present work we are concerned with the capability of the input signals of a digital circuit in detecting faults. In studying a signal, what we care most is the predictability of the signal. If the signal is predictable, we can use a portion of it (the past and the current) to represent and reconstruct it in entirety. For digital circuits, Hadamard functions can be used to represent the spectral information. We will determine Hadamard coefficients for input patterns that have a high fault coverage in a given sequential circuit. Using just a few coefficients, a pattern set can be generated, which preserves the characteristics relevant to fault detection, while randomly changing others. Self-test of embedded cores, then, becomes a problem of constructing a set of waveforms, which when applied at the primary inputs of the core, can excite and propagate targeted faults in the core. In order to capture the spectral characteristics of a given signal, a noise-free representation for that signal is desired (wider spectra lead to more unpredictable/random signals). Thus, any embedded noise should be filtered. Static test set compaction [27, 28] reduces the size of the test set by removing any unnecessary vectors while retaining the useful ones. In other words, static compaction filters unwanted noise from the derived test sequence, leaving a cleaner signal (narrower spectrum) to analyze. Applying this idea to generating vectors for BIST, the derived spectral information not only helps to identify embedded spectral information, but also offers a new way of testing sequential circuits by predicting intelligent vectors based on the vectors we have so far. Vectors generated from a selected spectrum have better fault detection characteristics. The remainder of the paper is organized as follows.

Section II gives an overview and motivation for the new spectral BIST. Section III discusses the details of spectral characteristic extraction. Section IV explains the application of such information to BIST. Section V reports the experimental results, and Section VI concludes the paper.

II

Overview and Motivation

Spectral decomposition is the most commonly used technique in signal processing. A signal can be projected onto a set of independent waveforms that have different frequencies. This set of waveforms, each represented as a vector, forms a basis matrix. The projection operation (a post-multiply to the basis matrix) reveals the quantity each basis vector contributes to the original signal. This quantity is called decomposition coefficient. Subsequently, enhancing the important frequencies and suppressing the unimportant ones (“noise”), we expect that we can have a new and higher-quality signal that will help test generation. In choosing the projection matrix, Hadamard transform is a well-known non-sinusoidal orthogonal transform used in signal processing [29]. A Hadamard matrix consist of only 1’s and -1’s, which makes it a good choice for the signals in VLSI testing (1 = logic 1, -1 = logic 0). Each basis in the Hadamard matrix is a distinct sequence that characterizes the switching frequency between 1s and -1s. We will use Hadamard transform for our analysis. Hadamard matrices are square matrices containing only 1s and -1s, and can be generated using the following recurrence relation:   H(k − 1) H(k − 1) H(k) = , k = 1, 2, ..., n, H(k − 1) −H(k − 1) where H(0) = 1 and n = log2 N . For example, with k = 1 and k = 2, above equation yields   1 1 1 1    1 −1 1 −1  1 1  H(1) = , H(2) =   1 1 −1 −1  1 −1 1 −1 −1 1 From this definition of the Hadamard matrix, we can observe that H(n) × H(n)T = nIn , where In is the n × n identity matrix. Given only 1’s and -1’s in the matrices, multiplication can essentially be computed using additions and subtractions. Moreover, the inverse transform of a Hadamard matrix is the same as the forward transform, making reconstruction straight-forward. Each row/column in a Hadamard matrix is a basis vector, carrying a distinct frequency component. Taking H(2) for illustration, the four basis vectors are [1 1 1 1], [1 0 1 0], [1 1 0 0], and [1 0 0 1]. Any bit sequence of length 4 can be represented as a linear combination of these basis vectors. For instance, the vector [1 0 0 0] can be written

Performed by core provider

Append vectors

Vector set (initially random)

Gate-level fault sim. and vector compaction

Extract Hadamard coeff. from compacted vectors

Fault No Generate coverage or max. more iterations? vectors Yes

Replace with compact vectors

Extraction completed Hadamard coefficients

User encoded program to generate BIST vectors using Hadamard coeff.

Performed by embedded CPU on SOC

Figure 1: Extraction and application of Hadanard coeff. as −1×[1, 1, 1, 1]+1×[1, −1, 1, −1]+1×[1, 1, −1, −1]+1× [1, −1, −1, 1]. Therefore, we can project the test sequence to the Hadamard basis components, filter out certain components and do an inverse transform to get the de-noised sequence. Figure 1 presents the overall framework for extracting the spectral characteristics by the core provider. Then, the coefficients are used to generate BIST vectors in the SOC. The coefficient extraction is done iteratively. Initially (iteration 0), the test set simply consists of random vectors. A call to static compaction filters any unnecessary vectors without lowering the fault coverage. Using the Hadamard transform on the compacted vectors, we analyze and identify the predominant Hadamard components at each primary input. We use this information to generate additional test vectors based on the identified spectrum. We may also generate vectors by spanning the likely vector space using only the basis components. This helps to drive the circuit into hard-to-reach states and gives us more information about the characteristics of the CUT. This process is repeated until a preset number of iterations is reached. During this process, the spectral characteristics for all primary inputs of the circuit are collected and stored. The gathered coefficients accompany the core, and are used to generate test sequences during BIST.

III

Spectral Characteristics Extraction

BIST techniques based on LFSRs use weighted random vectors to enhance fault coverage. The drawbacks of these techniques are often insufficient fault coverage, long test sequences and extra hardware. The goal of the present spectrum-based BIST technique is to extract information embedded in the CUT in the form of Hadamard coefficients to create suitable vectors during BIST and overcome the above drawbacks. Because of the way Hadamard coefficients are obtained, the patterns have high fault coverage. Besides, they resemble “functional” patterns and allow the technique to be applied to sequential circuits. In the procedure of Figure 1, the core provider may use the following algorithm:

Algorithm 1: Let ai be the input bit sequence for primary input i. /* coefficient extraction */ for (each primary input i in test set) coefficient vector ci = H × ai for (each value in the coefficient matrix [c0 , ..., cn ]) if (absolute value of coefficient < cutoff) Set the coefficient to 0. else Set the coefficient to 1 or -1, based on its abs value. /* generation of vectors based on coefficients */ for (each primary input i) extension vector ei = modif ied ci × H if (weight > 0) Extend the vector set with value 1 to PI i. else if (weight < 0) Extend the vector set with value -1 to PI i. else if (weight == 0) Randomly extend the vector set with either 1 or -1 To illustrate Algorithm 1, let us consider a subsequence of eight 4-input vectors. We first replace each ’0’ with with a -1: P I0 P I1 P I2 P I3 1 1 1 0 1 0 0 1 replace 0 1 1 0 0 with -1 1 1 0 1 7−→ 1 1 1 1 1 0 0 0 1 1 0 0 1 0 0 1

P I0 P I1 P I2 P I3 1 1 1 -1 1 -1 -1 1 1 1 -1 -1 1 1 -1 1 1 1 1 1 1 -1 -1 -1 1 1 -1 -1 1 -1 -1 1

Next, we perform spectral analysis. Consider the bit stream for primary input P I1 . Multiplying H(3) with the bit stream for P I1 , we obtain its coefficient vector:  1   2   1 1 1 1 1 1 1 1       

1 1 1 1 1 1 1

−1 1 −1 1 −1 1 −1

1 −1 −1 1 1 −1 −1

−1 −1 1 1 −1 −1 1

1 1 1 −1 −1 −1 −1

−1 1 −1 −1 1 −1 1

1 −1 −1 −1 −1 1 1

−1 −1 1 −1 1 1 −1

      

−1 1 1 1 −1 1 −1

      =      

6 −2 2 2 −2 −2 2

      

If the cutoff for coefficients is set to 4, then the coefficient vector ci is modified by replacing every coefficient whose absolute value is less than 4 with 0. Thus, the new c1 becomes [0 1 0 0 0 0 0 0]T . Multiplying the new coefficient [c1 ]T with H(3) yields: [0 1 0 0 0 0 0 0] × H(3) = [1 − 1 1 − 1 1 − 1 1 − 1]

We will extend the test set for P I1 with (1, -1, 1, -1, 1, -1, 1, -1). Here, we have filtered out the higher order

Hadamard components that contribute to randomness in the input bit stream, since bit #4 has been changed from 1 to -1. Now, let us consider a different primary input P I3 . Multiplying H with P I3 yields coefficients shown below:  1   −1   0  1 1 1 1 1 1 1       

1 1 1 1 1 1 1

−1 1 −1 1 −1 1 −1

1 −1 −1 1 1 −1 −1

−1 −1 1 1 −1 −1 1

1 1 1 −1 −1 −1 −1

−1 1 −1 −1 1 −1 1

1 −1 −1 −1 −1 1 1

−1 −1 1 −1 1 1 −1

      

1 −1 1 1 −1 −1 1

      =      

−4 0 4 0 −4 0 −4

      

If the cutoff for coefficients is again 4, then the coefficient vector is changed to [0 −1 0 1 0 −1 0 −1]. Multiplying the new coefficient with H(3) yields the following extension vector: [0 − 1 0 1 0 − 1 0 − 1] × H(3) = [−2 2 − 2 2 2 − 2 − 2 2]

Extending the compacted vector set for P I3 , we obtain scaled vector (-1, 1, -1, 1, 1, -1, -1 1). This is the same as the input sequence, which means that there was no random noise that needed filtering. Similarly, we obtain extended vector sets for P I0 and P I2 as (1, 1, 1, 1, 1, 1, 1, 1) and (1, -1, -1, -1, 1, -1, -1, -1). Thus, we append the following newly generated vectors to the test set: 1 1 1 1 1 1 1 1

1 -1 1 -1 1 -1 1 -1

1 -1 -1 -1 1 -1 -1 -1

-1 1 -1 1 1 -1 -1 1

The coefficients may also be computed with or without overlapping bit streams. Let us consider H(3) without overlapping. Bits 0-7 of a PI are first multiplied with H(3) to get Hadamard coefficients. Then, bits 8-15 are considered, followed by bits 16-23, and so on. When considering overlapping of bits during coefficient extraction, bits 0-7 of a PI are first multiplied by H(3) to get Hadamard coefficients. Then, bits 1-8 are considered, followed by bits 2-9, and so on. Overlapping will identify cases where the inherent temporal correlation is more pronounced [25,26]. We repeat this process a maximum of 10 times, and average the coefficients obtained for the 10 iterations.

IV

Use of Spectral Information for BIST

We now use the Hadamard coefficients obtained to generate vectors for BIST in a System-on-a-chip (SOC) environment. We make the assumption that a SOC contains a central processing unit (CPU). In such a system, the CPU can be used to generate test vectors for other cores/peripherals in the system. Thus, we will not have

to depend on specific hardware such as LFSRs to generate patterns for testing other devices on the chip, but can generate vectors using spectral testing. These vectors are generated based on the spectral information extracted by the core provider. Here, we use the technique described in the previous section to generate the spectral coefficients, since this technique extracts the dominant strain in the input bit stream rapidly. Generation of vectors by spanning the spectral coefficients would lead to the test set having only twice as many vectors as the size of the original test set used to derive the Hadamard coefficients. In order to generate more vectors, we can duplicate some vectors; this is shown in Algorithm 2. H(4) is used in Algorithm 2 and the values of the coefficients range between +16 and -16. Algorithm 2: Assign a cutoff value of 6. Generate a set of vectors from coefficients. Randomly duplicate p vectors during generation of vectors Assign a cutoff value of 8. Generate a set of vectors from coefficients. Randomly duplicate p vectors during generation of vectors Assign a cutoff value of 10. Generate a set of vectors from coefficients. Randomly duplicate p vectors during generation of vectors

In Algorithm 2, we first generate vectors from the coefficients using a cut-off value of 6 for the Hadamard coefficients. While generating vectors, we duplicate an arbitrary number (p) of vectors a few cycles. We repeat this procedure increasing the cut-off value of the Hadamard coefficients to 8 and 10, respectively. Increasing the cutoff value is equivalent to fine-tuning the filter, leading to more refined information about the CUT. The overall application of BIST vectors to each embedded core is illustrated in Figure 2. The CPU takes Hadamard coefficients provided by the core designer (computed using Hadamard transform) and generates corresponding BIST patterns from the coefficients. The embedded CPU repeats this process for every embedded core/peripheral in the SOC.

V

Experimental Results

All experiments were conducted on an Ultra SPARC 10 with 256 MB of RAM for some ISCAS 89 [30] and ITC 99 [31] benchmark circuits, all treated as nonscanned embedded cores in an SOC design. We compare our results obtained from spectral characteristics with the weighted random approach for BIST. In both cases, 70,000 BIST vectors were generated. The results for weighted random patterns are shown in column 3 of Table 1. In this case, ideal weights are used. However, since it is difficult to obtain the exact

Table 1: Coverage of 70,000 weighted-random and spectral patterns for BIST. Circuit s382 s400 s526 s713 s1196 s1238 s1423 s1488 s1494 s5378 b01 b04 b08 b11 b12 Total

Faults detected (highest coverage shown in boldface) Weighted-random patterns Spectral patterns Ideal weights Rounded-off weights H(4) H(5) 329 116 364 364 306 106 384 384 95 94 451 454 476 476 476 476 1233 1228 1237 1236 1276 1270 1282 1279 1319 1167 1414 1413 1442 1410 1444 1444 1451 1418 1453 1453 3127 3083 3596 3521 133 133 133 133 1168 1168 1168 1168 461 438 463 463 937 898 1004 1004 663 636 1621 1615 14416 13641 16490 16407

Total Faults 399 428 555 581 1242 1355 1515 1486 1506 4603 135 1346 489 1089 3102 19831

SOC

CPU (use Hadamard coefficients to generate vectors for BIST)

Core/Peripheral

Core/Peripheral

(tested by BIST vectors generated by the CPU)

(tested by BIST vectors generated by the CPU)

Figure 2: Use of Hadamard coefficients for BIST. weights in hardware without incurring substantial overhead, we round off the obtained weights to the nearest quarter (0.25, 0.5 or 0.75). The results for this technique are shown in column 4 of Table 1. The results for the spectral BIST technique are shown in columns 5 and 6 of Table 1. For each circuit we have selected the matrix either for the overlapping input streams or for non-overlapping streams, depending on whichever provides higher fault coverage. We assume that such a selection can be easily made by the core provider. The Hadamard coeffients are obtained from only 10 iterations of compaction and coefficent extraction (Figure 1). Column 5 gives results for the H(4) matrix, and column 6 for the H(5) matrix.

As shown in the table, in all cases, the results of our technique either surpass or equal the results obtained for the ideal weighted random technique. For some hardto-test circuits such as s5378 and b12, our technique is able to detect significantly more faults than the weighted random BIST approach. For example, our technique detected 1621 faults for b12 while the ideal and roundedoff weighted random patterns detected only 663 and 636 faults, respectively. For a given circuit, the size of the Hadamard matrix used to extract the input spectrum will influence the final fault coverage. This is because different circuits exhibit different spectral characteristics. For instance, in circuit s526, H(5) (length of 32) produced the best result, while for all other circuits, H(4) (length of 16) performed equal or better. The effect of overlapping input streams when computing the spectral coefficients plays a role. Overlapping will benefit fault detection when the embedded temporal correlation of input streams is large [25, 26].

VI

Conclusion

We have presented a novel spectral technique for BIST in the SOC environment. The core provider first computes/analyzes the spectral characteristics for the core using the Hadamard transform. Vector sequences, then, can be represented as a linear combination (indicated by the Hadamard coefficients) of the basis vectors (columns of the Hadamard matrix). These Hadamard coefficients are then used by the embedded processor of the SOC to generate new BIST vectors for the cores/peripherals. Experiments conducted using this technique showed that

higher fault coverages can be obtained when compared to the LFSR-based weighted random pattern generation techniques, without incurring the overhead of additional test hardware. Future work should include a study of the optimal Hadamard matrix for given circuits.

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