OpenAccess @ Synopsys - Si2

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Oct 9, 2012 ... Thanks go to Cadence and all the member companies in the OAC who ... Custom WaveView. IC Compiler ... Saves hours of tedious manual.
OpenAccess @ Synopsys Scott I. Chase Principal Engineer, Custom Design Group October 9, 2012

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Note to Self: Don’t Bury the Lede! • Open Access enables a custom platform which is: – – – –

Open Configurable Customizable Extensible

• Thanks go to Cadence and all the member companies in the OAC who have enabled this shared technology for our mutual benefit.

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• Before 2004 – The earth was without form and empty, with darkness on the face of the depths…

• Late 2004 – Monterey Design Systems acquired. The team joined Synopsys’ Analog & Mixed Signal Group. Copernicus, an internal project to develop a new custom design platform, was launched.

• Spring 2005 – With the realization that openness, interoperability, customizability and the ability to build flows that work were going to be keys to success in this space, Synopsys joined Si2 in order to participate in the OAC. ©Synopsys 2012

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IPL Alliance One PDK Works in Multiple Vendor Environments

Our Newest Members New 40nm iPDK Reference Kit Released

Growing Membership Go to www.IPLNow.com for more information

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Synopsys Participation at the OAC • Si2 Board: John Chilton, SVP Marketing/Strategic Dev. • OAC Board: Scott Chase • OA Change Team over the years: – Fred Sendig – Scott Chase – Eric Leavitt

• • • • •

OA ESG: Scott Chase Constraints WG: Barry Giffel oaDebug WG: Salem Lee Ganzhorn Scripting Languages WG: Christian Delbaere Limits WG: Eric Leavitt

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Contributions in Kind • oaViewer (BG) • oasTcl (CD) • oaCompare (SG) • 20+ patches for bugs

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Custom Designer Unified Solution for Custom Design Open Platform

Front End

Back End

Value Links

OpenAccess

Schematic Editor

Layout Editor

HSPICE

iPDK

Hierarchy Editor

Schematic-Driven Layout

CustomSim

Constraint Editor/Manager

Netlisting Environment

Custom WaveView Custom Router IC Compiler

Connectivity Engine/ Design Navigator tcl Scripting Customization

Simulation & Analysis Environment

SmartDRD Technology Physical Verification Environment

StarRC IC Validator NanoTime

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ICC Compiler  Custom Designer Co-Design Co-Design = cell-based P&R and custom layout tools used on the same design

IC Compiler

Seamless Design Transfer

Custom Designer

• Seamless custom editing at any stage of the IC Compiler implementation • Comprehensive custom editing capabilities • Out-of-the-box solution for easy setup and use

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Analog Design Acceleration SBR Shape Based Analog Router

Batch Router Rich Set Routing Topologies

Helix Analog Placement

Mins / Hrs

Fully constrained

Save weeks of layout time ©Synopsys 2012

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FlexCell building block libraries



Analog circuit porting & re-use

Fast, Model-based Global Optimization

ALX Analog Layout Migration

Hrs / Days 1st placements

Schematic

ADX Analog Circuit Optimization

Automates Migration of Analog IP Layouts

Custom Designer 2012.09 Highlights Accelerates Custom Layout Implementation Automated Wire Striping • Stripes the entire net with auto-via

• Saves hours of tedious manual work

Layout Dependent Effects • LDE parameters automatically extracted • Simulate directly from layout

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Local Interconnect & Cut Poly • Connectivity derived from 2 layers • Enables SDL for advanced nodes

EM/R Checker • Constraint Driven • Fast calculation directly from layout

Challenges – Past • Spring/Summer 2005 -- Adopting OpenAccess • Moving from 2.0 to 2.2 – Incremental tech – New exceptions – figGroups

• Scratch Designs • Front End Interoperability

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Challenges – Current • Multithreading – with or without design-open modes • Advanced Node Constraints – Lag too far behind the leading edge, causing duplicate work, backward compatibility issues.

• String/Name Table Capacity – Big Verilog netlists with long net names

• Design Intents – OA is completely silent on analog design intents, electrical constraints, etc.

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Challenges – Future • Capacity limit of OA – 2m x 2m LCD with sharp electrodes – High dbu/uu, e.g., 10000 – + a few bits to allow for rounding error during floating point pointArray geometry operation

• Performance limits – non-undoable appDefs will help in some cases

• Advanced Node Constraints – Continue to be a challenge, double work, etc. and are growing in number

• 2.5D, 3D

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Click to begin. ©Synopsys 2012

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Scrambled Insertions Eggs

Lasts

Things & Subitize Me Stuff

Odd Man Out

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I am a huge nicely

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Michaela Guiney

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Past mid-august

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Sumit Dasgupta

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Ever top test

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Steve Potter

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I'm valid, lads!

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David Mallis

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Potence is occasional

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OpenAccess Coalition

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Thank You

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