interconnects is to understand the electrical performance of wire bond (the RF interconnect of choice) at and above frequency of interest, and to determine the ...
Parameterized Models for a RF Chip-To-Substrate Interconnect Ingo Doerr1, Lih-Tyng Hwang2, Grit Sommer1, Hermann Oppermann1, Li Li2, Michael Petras2, Sabine Korf1, Faical Sahli1, Tom Myers2, Mel Miller2 and Werner John1 1 Fraunhofer IZM Gustav-Meyer-Allee 25, D-13355 Berlin 2 Motorola, SPS 2100 E. Elliot Road, Tempe, AZ 85284
Abstract Skyrocketing growth in the cellular personal communications services (PCS) sector has fueled the needs for higher density, more functionality, and greater performance on both handset and basestations. Third generation wireless standards, which require hardware upgrades, loom on the horizon. RF component suppliers are scrambling to find solutions at the IC, package, and PCB levels to meet these challenges. RF module packaging is considered as one of the low cost solutions to the future wireless products. One of the critical design needs for RF interconnects is to understand the electrical performance of wire bond (the RF interconnect of choice) at and above frequency of interest, and to determine the performance limit for the wire bond chip-to-substrate interconnect. The availability of design kit or library would result in a substantial reduction in design cycle times. Using wire bond as example, this paper illustrates the developmental stages that turn electromagnetic characteristics of a physical structure into design library. Fullwave simulation using Ansoft HFSS and compact models extraction using optimization tool for wire bond will be shown, followed by in-depth discussions of wire bond parameterized models. Validation of parameterized model by measurement will be presented. Introduction RF module packaging has many advantages: favorable pricing power being the most important one, as opposed to cost-based pricing at the sum of the individual ICs and embedded passives costs. The module packaging can also benefit the system integrators who are less skillful in RF design and skills. This ease of use leads to proliferation of RF module demands. Design tools or libraries for module are one of the critical paths that enable a full adoption of the module technology. In this paper, the parameterized electrical compact (RLC) models of wire bonds (the RF interconnect of choice) are shown. Since interconnects are relatively independent of the substrate of choice, development of interconnect models need not be repeated as substrate of choice changes. Since LTCC allows an easy implementation of different die height (or thickness) using cavity, it is used in wire bond interconnect models development. Using mainly single wire bonds as example, the design tool development methodology is illustrated. First, the design space and Design of Experiment (DOE) for wire bonds are described, followed by Ansoft
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HFSS simulation, feed de-embedding technique, and the optimization routine used to obtain the R, L, C equivalent circuits. Experimental validation, including design of interconnect test die and LTCC test substrate, is also described. Wire Bond Simulation The design space (main independent factors and their ranges) of wire bonds was determined first. Experimental design principles were then practiced to minimize the number of simulation runs. After the DOE was set up, Ansoft’s high frequency structure simulator (HFSS) was employed to obtain the fullwave characteristics of the wire bonds. Since the full wave simulation requires a uniform wave front, port feeds were needed and included in the simulation. The feed was then deembedded to obtain wire(s) only characteristics in Sparameters. R, L, and C of the wire bond compact models were extracted by optimization tool (Serenade from Ansoft) using the wire only S-parameters. Design of Experiment In order to investigate the impacts of geometrical factors on the electrical behavior of a component (wire bond, for example) in an efficient way, an experimental design (DOE) was set up. Having chosen the main factors and their appropriate levels, the DOE runs (in full or fractional factorial, depending on the number of runs) were simulated using Ansoft’s HFSS. Single Wire (Ball-Wedge) The main independent factors of the single wire bond are the span of the wire (Span), the elevation difference between the first and the second bonds (DH), the maximum wire loop height from the first bond (MH) and the type of bonding, e.g. ball-wedge and wedge-wedge. The type of wire bonding determines the location where the maximum loop height occurs. For ball-wedge bonding, it is assumed that the maximum loop height occurs about onethird the span. In Figure 1, the critical parameters of a ballwedge bonding are illustrated. Since the glob top affects the capacitance of the wire bond, the dielectric properties (εr, tanδ) were also entered as critical parameter (see Table 1). In this paper, the wires are made of Au, and the diameter of the wires is set to be 1 mil (25.4 µm).
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Figure 1: Geometry and relevant Parameter of wire bond interconnection Table 1 lists the geometrical parameters, its description and the range, they are allowed to vary in. Parameter MH
Description Max. Loop Height
Ranges
Span of Loop Relative Permittivity of encapsulation
1mm – 3mm 1 (no encapsulation) – 3.5
Die Height
0 µm (recess) – 350µm
100µm –300µm
S εr DH
Electric Loss Tangent of up to 0.01 encapsulation Table 1: Typical RF relevant parameter of single wire bond interconnection Tanδ
Furthermore, a two-level full factorial design with center point was chosen for the wire bonds. For each parameter, two levels within the range interval (see Table 2) were selected and combined with each other. Figure 2 gives an idea how the design space appears geometrically for the inductance L, which depends on MH, S and DH. The star markers (green) represent all combinations of the chosen levels (Num_Levels Num_Parameters = 23 = 8) and form one part of the design space (green box). The dot marker (blue) is the center point and lies in the geometrical middle of the lower and upper range limit. Now, to enlarge the design space, two additional levels (the upper and lower range limit) for each parameter were chosen and combined with the corresponding values of the center point. They are represented by the rhomb markers (red) and form the outer sphere of the design space. Figure 2 on the whole shows very demonstratively the geometry space, which closely related to a parameterized function. Each of the markers describes the geometry for one simulation. In fact, the parameterized function for the single wire bond was based on 8+1+6 = 15 combinations (simulation runs).
Figure 2: Definition of design of experiment Coupled Wire (Ball-Wedge) According to the angle between the two adjacent wires, the coupled wire bond simulations were divided into small angle (angle less than 20 degrees) and large angle (angles of 45°, 90°, 135° and 180°) coupling simulations. Case 1 – Small Angle (Ball-Wedge) The main independent parameters for the small angle case are the pitch of the wires on the die side (CH_PP), the angle between the two wires (alpha) and the spans of the two wires (Loop A, Loop B). Figure 3 illustrates the parameters of a coupled ball-wedge wire bond. Since the glob top affects the capacitive coupling between the two wires, it is also included in the DOE definition as critical parameter. Loop A Chip
Loop B
Port 3
Port 2
CH _PP
Port 4 Port 1 Substrate Substrate
Figure 3: Critical design parameters for coupled ball-wedge wire bonds (small angle)
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Case 2 – Large Angle (Ball-Wedge) Large angle simulation includes the cases in which the angle between two adjacent wires is larger than 45°. Simulation points were chosen to investigate and extrapolate the coupling terms from the small angle arrangement. The main independent parameters are the pitch of the two wires on the die side (CH_PP), the angle between the two wires (sites) and the spans of the two wires (Loop A, Loop B). Parameter
Description
Ranges
Sa
Span of Loop a Span of Loop b Relative Permittivity of encapsulation Angle between wire a and b Electric Loss Tangent of encapsulation Die Pad Pitch
0.75 mm – 2 mm
Sb εr α Tanδ CH_PP
0.75 mm – 2 mm 1 (without encapsulation) – 3.5 0° - 180° up to 0.01 75µm – 300µm
Table 2: Typical RF relevant parameter of coupled wire bond interconnection Table 2 shows the varied parameter for both, small angle and the coupled large angle wire respective ranges. Again, a full factorial design points was chosen for small angle coupled simulation.
Main parasitic characteristic of wire bond is inductance, as it is shown in Figure 9 with frequency dependent magnitude of transmission coefficient. With increasing of span inductance increases as well. Second order geometry parameters are loop height and die height. The encapsulation material influences capacitance of wire to ground.
port1
the coupled bonds with with center wire bond
3D FEM Simulation Ansoft High Frequency Structure Simulator (HFSS), using finite element method, was employed to obtain the full wave characteristics of wire bonds. Since the full wave simulator requires a uniform traveling wave to obtain the scattering parameters (S-parameters) of the physical structures, a section of well developed transmission line section was added to each port. The effect of these transmission line feeds can be later removed from the total effects. The electrical modeling of the wire bonds is based on electromagnetic simulation results. Numerical simulation is able to capture more physical configurations than assembly Other advantages include less sample preparation times, quicker to obtain results. It is, however, necessary to experimentally validate the simulation-based parameterized models. ne of challenges was to generate a relevant loop form. With definition of Span, Loop height and Die height the loop and the effective line length is defined (see Figure 1). By conducting a detailed analysis of bonding machine fabricated loop forms, a macro for automated wire bond model generation was developed. Figure 5 shows a three dimensional loop form in Ansoft’s HFSS simulation. A geometrical analysis illustrates very good agreement between the assembled wire bond and the geometrical model (Figure 4 and Figure 5).
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Figure 4: Cross-section of wire bond between die and substrate, loop form
port2 Figure 5: EM simulation model, loop form De-embedding The goal of de-embedding is to obtain RF interconnect model without the pad parasitics. This leads to an interconnect model independent from chip and substrate technology. EM simulation and RF measurement takes place for the whole structure including feeding pads. Subtraction of pad parasitic can be carried out as explained in Figure 6. Deembedding
of the Wire from Pad
e γ l - Deembedding
e γ l - Deembedding
Square Pads: Chip = 125 x 125 µm Substrate = 225 x 225 µm
[Y deemb ]= [Y Wire and Square Pads ]− [Y OPEN Square Pads ]
Figure 6: De-embedding of wire bond from pads
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SimulateEntire Structure
Simulate without Wire(s)
De-embedded Up to the Square Pads
De-embedded Up to the Square Pads
Convert from S to Y
Convert from Spad to Ypad
Y-Ypad
Convert back to S
Figure 7: An HFSS Simulation for coupled wire bonds In coupled wire bond simulation, Figure 3, the four ports were located on four separated planes to avoid the wave coupling between the feeds. In Figure 7, the procedure to obtain wire(s) only physical characteristics (S-parameters) is illustrated. Please note that the “without wire(s)” simulation has the identical fundamental structures as that of “Entire” structure. That is, the feed structures in the two simulations are remained the same. De-embedding of coupled wire bonds needs considering of coupled pad parasitics. The final S-parameters were expressed in the so-called “touchstone” format. The format can be universally accepted by other simulation and modeling platforms. Model Extraction Using Optimization Compact model extraction takes place. At first a compact model structure which is able to describe wire bond characteristic in needed frequency range and in full design space. Compact modeling leads to an approximation of signal behavior. With the number of elements the usable frequency range is limited. Optimization tool (Serenade Ansoft) was used to obtain the compact models for R, L, and C using the touchstone Sparameters obtained. Single Wire Bond
Figure 8: The compact model for single wire bond: a) inductance only, b) unsymmetrical T model, c) symmetrical T model In the frequency range of interest, 1 GHz to 10 GHz, the resistance varies drastically due to the skin depth. And, the L and C are remained relatively unchanged. Figure 10 shows the dependency of the inductance from geometrical parameters. The main impact of course comes from the span S of the wire and in second order from loop height MH and die height DH. With increasing of MH and DH the loop length increases, therefor the inductance value enlarges as well.
G oal:EM -Sim ulation Sym m etricalT -M odel
L-M odel Unsym m etricalT -M odel
Figure 9: Compact model approximation of 3D full wave calculation, comparison of different compact model structures
The following modeling structures shown in Figure 8 were investigated: single inductance, unsymmetrical T model and symmetrical T model. Figure 9 shows the comparison of compact model approximation for the 3 different models. Modeling of wire with inductance only and unsymmetrical T model shows agreement with 3D EM simulation up to frequency of about 3GHz. Better performance provides the symmetrical T model (see Figure 8). The wire with typical span can be modeled up to 10GHz.
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0.50
Single W ire 3
Mutual Inductance in
2.5
L_W ire in nH
2
M H=250,DH=262.5
1.5
M H=200,DH=175
Span = 2000µm Span = 750µm 0.25
M H=150,DH=262.5 1 M H=250,DH=87.5 M H=150,DH=87.5 0.5 0
0.5
1
1.5 2 S in mm
2.5
3
0.00
3.5
0
30
60
90
A ngelin °
Figure 10: Inductance of wire as function of loop span, loop height and die height Coupled Wire Bonds Figure 11 shows the compact model for coupled wire bonds. The schematic consists of two symmetrical T models and mutual inductance M12 and coupling capacitance CC between. It could be shown that for the transmission paths between ports 1 and 4 and/or ports 2 and 3, the results of single wire modeling can be used. Moreover, this modeling procedure gives the opportunity to use the single wire results and switch on or off the coupling elements, dependent from application requirements. This model describes the electromagnetic simulation results in defined design space up to 10 GHz with an error less than 1%. The dominant coupling effect is the mutual inductance (Figure 12). Fore angle more than 90° the coupling reaches values in order of – 40dB and below. In typical system applications below – 40dB can be neglected (Table 3). These values are very difficult to determine.
Figure 12: Mutual inductance as a function of angle between the wires and the span after compact modeling Pitch in µm 300 300 300 300 300 300 300 300 300 300 300 300
Angle 0 20 45 90 135 180 0 20 45 90 135 180
Span a in mm 0.75 0.75 0.75 0.75 0.75 0.75 2 2 2 2 2 2
Span b in mm 0.75 0.75 0.75 0.75 0.75 0.75 2 2 2 2 2 2
Coupling at 1GHz / dB -31 -33 -35 -38 -46 -65 -26 -31 -35 -41 -42 -61
Table 3: Coupling scattering parameter S13 as a function of angle between the wires Parameterization of Model After the R, L, and C values of the single wire bond were obtained for the entire DOE, as shown in Table 4, the R, L, and C can be expressed as functions of the corresponding independent factors (geometry parameters, see Table 1) by applying appropriate optimization methods. For the example of the single wire bond, following functional dependencies are required: C = f(MH,DH,S,εr) L = f(MH,DH,S) R = f(MH,DH,S)
Figure 11: The Compact Model for Coupled Wire Bond
The most important and challenging part of the parameterization is the creation of a function model that describes the physical impact of the geometry parameters in a physically correct and mathematically effective way. Usually, a polynomial approach is used. As an example, the inductance, L, for a wire bond can be modeled as: L ( MH , DH , S ) = a 0 + a 1 MH + a 2 DH + a 3 S + a 4 MH DH + a 5 MH S + a 6 DH S + a 7 MH DH S
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The coefficients a0, a1,.... are calculated with help of the software JMP which uses the least square method to determine coefficients of linear function models. JMP provides also statistical features, which allow the user to verify and validate the obtained function. One of the critical criteria is to maximize the correlation coefficient, Rsquare, which reflects the correlation between the simulation (or measurement) results and the predicted results using the parameterized function (model). The closer the Rsquare to 1 the better the correlation between Lsimulated and Lpredicted the better the prediction capability of the model. After the parameterized models are validated, they will be ported to a design system.
pads. During set-up the loop forming process was optimized for each DOE type. Hysol FP4451 was dispensed as damming material and Hysol FP4450 for glob top and fully cured at 150°C for 2 hours.
Experimental Validation The E63E-A3 85% BiCMOS test die and LTCC test substrate were used to obtain the electrical characteristics of chip to substrate wire bond interconnects. E63E Test Die To characterize the wire bond interconnects test chips were fabricated on E63E-A3 using 85% BiCMOS technology by MOS16. Die A has both wire bond and flip chip test structures, Die B and C are for wire bond characterization only. Wire bond pads on die A are 70 µm wide 100 µm long on 150 µm pitch. On die B the pads are 50 µm wide 70 µm long on 75 µm pitch. Die C has pads of 70 µm length with variable widths.
Figure 14: Die bond test chip on LTCC Finally, all test vehicles were investigated by ultrasonic microscopy to ensure the completed flow of the epoxy resin. X-ray inspection from top and from the side was used to measure the wire bond loop after completing the assembly process.
Figure 15: X-ray inspection of test vehicle Reverse engineering by cross-sectioning and metallurgical analysis was performed for some electrically investigated test vehicles to compare the actual geometry with the DOE definitions (Figure 15).
Figure 13: E63E-A3 Test Chips (A, B, and C) LTCC Test Substrate LTCC test substrates were fabricated using both Dupont 951 and T2000 (Motorola IP) green tapes including wire bond, flip chip and ceramic test structures. The top layer metal can be either Au, Ag, or AgPd. Fabrication of Test Vehicle Die bonding was performed with a pick & place device using a silver filled epoxy Ablebond 8360. The chips were placed with an accuracy of less than 10 µm relative to the chip and substrate pad positions. The adhesive was precured at 110°C for 30 minutes to minimize bleeding of adhesive (Figure 14). Final curing took place at 175°C for 1 hour. A ball-wedge wire bonder and gold wire of 25 µm diameter was used to connect the die pads with the corresponding substrate
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Test Design – Principle of Measurement Error! Reference source not found. shows the measurement principle. The test chip is wire bonded on both sides of the transmission line. On substrate side, wires are bonded on vias to contact bottom substrate side. The whole structure is under glob top so that measurement to extract the influence of the glob top material is only possible from backside. Assuming both wires are equal, additional measurements are necessary to characterize vias, transmission line and wires separately. Full two port scattering parameter measurements were carried out with vector network analyzer HP8510B in a frequency range from 45 MHz to 26GHz. Measurement setup includes a probe station with two coplanar microwave probes connected to the test ports of HP8510B.
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prime example, is described. Full wave simulator, the Ansoft’s HFSS, was used to obtain the electrical characteristics of the RF interconnect. Optimization was then used to extract the R, L, and C for the wire bonds. Parameterized electrical models of chip-to-substrate wire bond interconnect were obtained using JMP, a statistics tool. The test vehicle used to validate the simulation results, were also designed and shown. The validation results were reported. A very good agreement (less than ±10%) between parameterized model and measured inductance was achieved.
Figure 16: Typical Test Sample Design, Measurement of Single Wires Measurement versus Simulation MH [µm]
S [mm]
DH [µm]
L/2 nH
Predicted Error in % L/2 [nH] 0.48 -0.5
250
0.85
0
0.47
240
2.20
0
0.76
0.50
7
150
2.31
270
0.75
0.64
1.8
250
2.31
270
0.73
0.71
-3
210
2.90
0
0.83
0.74
3.2
190
1.55
0
0.55
0.75
-8.6
200
1.62
270
0.64
0.80
-0.03
Table 4: Comparison of inductance resulting from measurement and simulation (using parameterized model) Table 4 lists the single wire inductance obtained from measurement and simulation (using parameterized model), as function of geometry. In case a test chip is present, a DH of 270µm is used. Otherwise, DH is zero for wires bonded from substrate to substrate. Each structure was assembled several times (minimum 3 times) and measured. The inductance values in Table 4 are averaged over the different measurements. To compare the electromagnetic simulation with the network analyzer measurement results, a geometrical analysis was necessary (Figure 15). It is because the assembled test vehicles are not exactly conformal to the configurations in the DOE. The results in Table 4 show a very good correlation between simulation and measurement. The error lies in the range of ±10%, similar to the normal assembly variations. The parameterization model has no tendency to either over- or under- estimate the measured inductance. Conclusions In this paper, the methodology used to obtain the parameterized electrical models, using wire bond as the
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References [1] “Cadence and Amkor Announce Alliance to Provide System-in-Package -- SiP -- Technology Solutions,” Business Wire, September 4, 2000. [2] Sang-Ki Yun, Hai-Young Lee: "Wideband Crosstalk Analysis of Coupled Bondwires Buried in High-Speed Plastic Packages," IEEE 6th Topical Meeting on Electrical Performance of Electronic Packaging, Page(s): 91 -94 IEEE, 1997 [3] Rolf Sihlbom, Markus Dernevik, Mats Lindgren, J. Piotr Starski, Zonghe Lai, Member, IEEE, Johan Liu, Senior Member, IEEE: "High Frequency Measurements and Simulations on Wire-Bonded Modules on the Sequential Build-Up Boards (SBU's)", IEEE, Vol. 21, NO. 3, September 1998 [4] Howard Patterson: "Analysis of Ground Bond Wire Arrays for RFICS", IEEE, Vol. 44, NO. 4, August 1995 [5] R. Groover, W. K. Shu, S. S. Lee: "Wire Bond Loop Profile Development for Fine Pitch-Long Wire Assembly," IEEE, Vol. 7, NO.3, August 1994 [6] "Wire Bond – Flip Chip – Chip Size Package Verbindungstechniken im Vergleich", Leiterplattentechnik, Bericht vom 3. EITI-Seminar 1997 in Stuttgart, Galvanotechnik, D-88348 Saulgau, 89 (1998) Nr. 1 [7] Christian Schuster, Götz Leonhardt, Wolfgang Fichtner: "Electromagnetic Simulation of Bonding Wires and Comparison with Wide Band Measurements," IEEE, Vol. 23, NO. 1, February 2000 [8] Xiaoning Qi, C. Patrick Yue, Torkel Arnborg, Hyongsok T. Soh, Zhiping Yu, Robert W. Dutton, Hiroyuki Sakai: "A Fast 3D Modeling Approach to Parasitics Extraction of Bonding Wires for RF Circuits," IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on], Volume: 23 Issue: 3, Aug. 2000 Page(s): 480 -488 [9] Norman R. Draper, Harry Smith: “Applied regression Analysis”, Wiley & Sons, 1998 [10] George E. P. Box, William G. Hunter, J. Stuart Hunter: “Statistics for Experiments,” John Wiley & Sons, 1978
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