Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations Bao Liu University of California San Diego La Jolla, CA 92093 Email:
[email protected]
Abstract We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timing analysis (SSTA) for a new level of efficiency-accuracy tradeoff. Our method is based on (1) a multi-point waveform characterization by signal arrival times at multiple voltage thresholds, (2) a parameterized current source gate model for process variations, (3) a parameterized gate performance model for process and signal waveform variations, and (4) Monte Carlo simulation. Our experimental results show that our proposed gate level statistical simulation achieves orders of magnitude of efficiency improvement based on the constructed gate models, while achieving within 3.91% (9.19%) accuracy in average for the means (standard deviations) of signal arrival times at multiple voltage thresholds.
1 Introduction VLSI technology scaling has enabled integration of an increasing number of components on a single chip, continuously driving down the cost of a chip. On the other hand, technology scaling also introduces an increase of process and system runtime variations for VLSI designs. Various process parameters are subject to variations in a manufacturing process. Layout feature widths, e.g., transistor channel length and interconnect width, are given by lithography process and interact with neighboring layout feature dimensions. Layout feature thickness, e.g., transistor gate oxide thickness and interconnect thickness, are results of chemical mechanical polishing (CMP) process, and depend on feature density in the local layout region. Transistor threshold voltage depends on and varies with ion implantation dopant concentration. Besides, temperature and power/ground voltage have significant variations at system runtime. All these variations affect VLSI design performance, and result in significant VLSI design performance variation. To capture such performance variation in VLSI designs, statistical static timing analysis (SSTA) is developed based on the traditional best-case-and-worst-case-based static timing analysis technique. Statistical static timing analysis represents signal arrival time variation in a probability density function (pdf). In block-based SSTA, each timing node has a
pdf for signal arrival time variation, and these pdf’s are propagated in the circuit in a breadth-first order [20]. In path-based SSTA, each timing node has a pdf for signal arrival time variation in each signal propagation path, these pdf’s are propagated in a depth-first order [15]. Path-based SSTA is more accurate, while block-based SSTA is more efficient. SSTA achieves efficiency in handling practical circuits, but faces several accuracy issues. (1) The difference between block-based SSTA and path-based SSTA states that signal arrival times strongly depend on circuit operation mode and input statistics. Any accurate, meaningful statistical timing analysis has to include into consideration circuit operation statistics, e.g., in term of signal probability as in power estimation [14]. (2) Signal arrival times in DSM and nanometer VLSI designs strongly depend on the signal integrity effects, e.g., crosstalk coupling, power/ground supply voltage variations, etc. Any accurate statistical timing analysis has to take these effects into account [8, 9]. (3) Accurate process variation information is vital to achieve accurate statistical timing analysis. Process variations can not be simply assumed Gaussian and need better characterization. Of particular importance are process parameter spatial correlations between components on a chip, which contribute to the majority of performance variation, and need to be characterized and taken into account in statistical timing analysis [10, 17]. Monte Carlo SPICE simulation addresses all these issues and achieves the most accurate and trustable statistical timing analysis. However, it is not possible to be applied for full chip analysis due to its efficiency limitation. In this paper, we propose gate level statistical timing analysis, to bridge the gap between Monte Carlo SPICE simulation, which is accurate but inefficient, and SSTA, which is efficient but inaccurate, for a new level of accuracy-efficiency tradeoff. We believe that this level of statistical analysis is much needed, yet little publication is available on this. We base our analysis method on the latest current source based gate models, which achieve orders of magnitude of accuracy improvement compared with the traditional gate models [3, 7, 11]. We characterize a signal waveform by signal arrival times at multiple voltage thresholds, to accommodate signal waveform complexity and variability in DSM and nanometer VLSI designs. We construct an extended current source gate model which is parameterized for process variations, and a gate performance model for each cell instance which is parameterized for input signal waveform and process variations.
We propose Monte Carlo simulation based on the proposed models. Our experimental results show an average of 3.91% (9.19%) accuracy for the means (standard deviations) of signal arrival times at multiple voltage thresholds achieved with orders of magnitude of efficiency improvement. The rest of the paper is organized as follows. We present background introduction for gate models, process variations and statistical analysis in Section 2, and propose gate level statistical simulation method in Section 3. We present our experimental results in Section 4 and conclude in Section 5.
2 Background 2.1 Statistical Timing Analysis Traditionally process variations are mainly inter-die variations. Inter-die variations are generally caused by equipment non-uniformity and physical effects such as thermal gradients and loading phenomena, which are independent on the chip under manufacturing. Traditional timing analysis captures inter-die variations by finding the best (worst) case scenario in that all components assume their minimum (maximum) possible delays. As technology scales, intra-die variations become increasingly significant. Intra-die variations are further categorized as systematic and random variations. Systematic intra-die variations include lithography effect, which gives metal width and transistor channel length, and chemical mechanical polishing (CMP) effect, which determines metal and transistor gate oxide thickness. These variations depend on neighboring layout feature dimensions or local layout density, and their effects on circuit performance tend to cancel each other, leaving spatial correlation of process parameters as the major contributor to circuit performance variation [10, 17]. An extension of the traditional timing analysis method captures intra-die variations by assuming maximum (minimum) delays for all components in a data propagation path, and assuming minimum (maximum) delays for all components in the clock propagation path for a setup (hold) time check. To estimate timing yield, or the probability for a chip to meet its timing requirements, statistical timing analysis describes possible signal arrival times at a timing node in a probability density function (pdf), and propagate these pdf’s in the circuit. Current statistical timing analysis techniques are mostly based on analytical computation, for example, by applying affine arithmetics [12], probabilistic interval analysis [17], etc. However, any accurate delay calculation cannot base on close form formulas. Recent publications point out that signal propagation delay is strongly affected by multipleinput switching for a gate [1], crosstalk aggressor signal alignment for an interconnect [8, 9], etc. Signal propagation delay is strongly affected by input signal transition time, yet little publication has addressed signal transition time variation. Further, in DSM and nanometer designs, signal waveforms are increasingly complex as a result of increased signal integrity effects. Traditional ramp function (with exponential attenuation [18]) or even Weibull function [2] based characterization methods cannot accurately capture signal waveforms in DSM and nanometer VLSI designs. All these factors
Vi
I(Vi, Vo)
Vo
Cg
R
C1
Vo’
C2
Figure 1. A current source gate model suggest the need to develop more accurate statistical timing analysis techniques, e.g., at the gate level, which is a lower level than the circuit level, with improved efficiency than transistor level SPICE simulation.
2.2 Gate Models Traditional gate delay calculation is based on table lookup for an input signal transition time and load capacitance pair. In DSM domain, on-chip interconnects are modeled as distributed RLC networks. Effective capacitance [4] is proposed to approximate a distributed RLC load interconnect such that the traditional table lookup method for gate delay calculation can still be applied. In this method, the gate model includes a voltage source which gives a ramp voltage, and a constant gate output resistance. Significant inaccuracy is observed in some cases in gate delay and output signal transition time calculation when using this model. A source of inaccuracy is that the increasingly complex signal waveforms in VLSI designs can no longer be approximated in ramp functions. Another fundamental problem is the consistency between gate models and MOSFET physics. A MOSFET is essentially a voltage-controlled current source, e.g., as is presented in the alpha-power law model [19]: VGS < VT 0 P W C α/2 (V −V ) VDS < PV (VGS −VT )α GS T IDS = (1) Le f f PV α W PC (VGS −VT )α V > P (V −V ) DS V GS T Le f f where IDS is the source-drain current, VDS the source-drain voltage, VGS the gate-source voltage, VT the threshold voltage, W the transistor channel width, L the transistor channel length, PC and PV are parameters, α is typically between 1 and 2 to capture nanometer transistor effects. A voltage-controlled current source transistor model implies a voltage-controlled current source gate model. For a simple inverter, a transistor model gives a gate model. This is also true for a complex gate, where an equivalent inverter marcomodel can be constructed for each input combination [13]. Current-based gate models better capture transistor physics and provide significant accuracy improvement compared with voltage-based gate models. A simple current source based gate model includes a 2D lookup table Io (Vi ,Vo ) which gives gate output current for a pair of gate input and output voltages, and a voltagecontrolled capacitor Cg at the gate output (Fig. 1). A transient analysis is applied to compute the gate output voltage, e.g., at each time step, the gate output current is given by the 2-D lookup table, and the gate output voltage variation is computed, e.g., by a nonlinear solver which applies NewtonRaphson or secant iteration [3, 7, 11]. Algorithm 1 describes the transient analysis process for a current-based gate model.
V
Algorithm 1: current Source Gate Model Based Simulation Input waveform Vi (t), lookup table Io (Vi ,Vo ), intrinsic gate capacitance Cg , load interconnect of a RLC network Output: Output waveform Vo (t)
Input:
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Dg 0.5
Dg 1. Reduce the load RLC network, e.g., to a Pi-model 2. For each time step t
0.2
3.
Find Vi (t) and Vo (t)
4.
Find Io (Vi ,Vo ) by table lookup
5.
Compute Vo (t + ∆t)
3 Statistical Gate Modeling and Simulation 3.1 Problem Formulation In this paper, we consider the following problem. Problem 1 (Statistical Gate Modeling and Simulation) Given 1. library cell characterization, 2. input signal waveform variation, and 3. process variations for a gate, construct a gate model for the variations, and compute the gate output signal waveform variation. We propose a statistical gate level simulation method for efficiency improvement over Monte Carlo SPICE simulation. Our method is based on 1. a signal waveform characterization method in the form of signal arrival times at multiple voltage thresholds, 2. an extended current source based gate model which are parameterized for process variations, 3. a gate performance model which is parameterized for process and signal waveform variations, and 4. a Monte Carlo gate level simulation method. Algorithm 2 gives an overview of the proposed statistical gate level simulation method. Algorithm 2: Statistical Gate Level Simulation Input:
Gate gi ’s cell characterization input signal arrival times Dαg i (g j ), i = 0, ..., n process variations εi , i = 0, ...k load interconnect Output: Output signal arrival times Dαg i (gi ), i = 0, ..., n 1. For each library cell 2.
Construct gate model of Io (Vi ,Vo , ε) and Cg (Vi ,Vo , ε)
3. For each cell instance 4.
Construct gate performance model Dαg i (gi ) = f (Dαg i (g j ), ε)
5. For sampled process variation corners 6.
Apply Monte Carlo simulation α
7. Collect output signal Dg i (gi ), i = 0, ..., n
Dg t
Figure 2. A signal waveform represented by signal arrival times at multiple voltage thresholds, e.g., at 20%, 50%, and 80% signal swing range. We present the details of this method in the following sections.
3.2 Signal Waveform Characterization To accommodate the increased signal waveform complexity due to signal integrity effects, and to represent variability in signal waveforms for the following statistical gate level simulation, we characterize an input signal waveform by the signal arrival times Dαg i (gi ) at multiple voltage thresholds αi , i = 0, ..., n, e.g., at the 20%, 50%, and 80% signal swing range (Fig. 2). Interpolation of these characterization points gives an approximation of the signal waveform. Variations (in terms of statistical moments and correlations) of these signal arrival times at multiple voltage thresholds give variation of the signal waveform. These signal arrival times at multiple voltage thresholds are computed and propagated in a circuit, e.g., based on the gate performance model that we propose.
3.3 Parameterized Current Source Gate Models for Process Variations To include the effects of process variations ε = (ε1 , ...εk ) into a current source based gate model, we construct a current source gate model which is parameterized for process variations. We establish functional relationships I(Vi ,Vo , ε) and Cg (Vi ,Vo , ε) between gate model elements, e.g., gate output current or intrinsic gate capacitance, and process variations, by performing deterministic SPICE simulation for sampled process variation corners. Algorithm 3 constructs our proposed parameterized current source gate models. Algorithm 3: Process Variation Parameterized Current Source Gate Model Construction Input: Variational input V˜i (t), process variations εi , i = 1, ...k Output: Io (Vi ,Vo , ε) and Cg (Vi ,Vo , ε) 1. For sampled process variations εi , i = 1, ...k 2.
Apply SPICE simulation for Io and Cg
3. Construct lookup tables for Io (Vi ,Vo , ε) and Cg (Vi ,Vo , ε) 4. (Construct regression polynomials for Io (Vi ,Vo , ε) and Cg (Vi ,Vo , ε))
−4
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x 10
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2 Ids
Ids
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3 −2 2 −4
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Vth
1 1.1
0.9 0.8 1.2
1 Vi
Figure 3. Gate output current Ids as a function of input voltage Vi and output voltage Vo for a 4× inverter in BPTM 90nm technology. We include in the model the effects of the process variations, e.g., transistor threshold voltage Vth and transistor channel length Lgate , which have significant effects on transistor performance, and are independent on each other, e.g., as results of different (doping and lithography) manufacturing processes. The gate output current Ids is approximately a quadratic (or piecewise linear) function of input voltage Vi , output voltage Vo , transistor threshold voltage Vth , and gate channel length Lgate , as is shown in Fig. 3 and Fig. 4, which are results of SPICE simulation for a 4× inverter gate in BPTM (Berkeley Predictive Technology Model) 90nm technology. The proposed parameterized current source gate models can be described in lookup tables, or polynomials if regression is applied, as a direct extension of the current ECSM (Effective Current Source Model) or Liberty cell library characterization format.
3.4 Parameterized Gate Performance Models for Process and Signal Variations For a higher level of abstraction and further efficiency improvement, we construct a gate performance model for a cell instance including the effects of variations in the input signal waveform and the load interconnect. Our gate performance model is constructed based on the parameterized current source gate model and the multiple point signal waveform characterization method. We sample the process variations and the input signal arrival times at multiple voltage thresholds, apply computation based on the parameterized current source gate model, and establish functional relationships between the gate performance, the process variations, and the input signal waveform variation: Dg (gi ) = f (Dg (g j ), ε)
(2)
where gate g j precedes gate gi in a signal propagation path, Dg (gi ) is a vector of signal arrival times Dαg i (gi ) at gate gi for voltage thresholds αi , i = 0, ..., n: Dg (gi ) = (Dgα0 (gi ), ..., Dαg k (gi ))
(3)
These parameterized gate performance models can be applied based on interpolation for instantiations of library cells
Lgate
Figure 4. Gate output current Ids as a function of transistor threshold voltage Vth and transistor channel length Lgate variation ratios with zero input and output voltages Vi = Vo = 0 for a 4× inverter in BPTM 90nm technology. with similar input signal transition waveforms and load capacitances. Algorithm 4 presents the parameterized gate performance model construction method. Algorithm 4: Process and Signal Waveform Parameterized Gate Performance Model Construction Gate gi ’s model of Io (Vi ,Vo , ε) and Cg (Vi ,Vo , ε) input signal Dαg i (g j ), i = 0, ..., n process variations εi , i = 0, ...k load interconnect Output: Output signal Dαg i (gi ), i = 0, ..., n
Input:
1. For samples of process variations εi and input signal Dαg i (g j ) 2.
Apply current source gate model based simulation
3. Construct lookup table for Dαg i (gi ) = f (Dαg i (g j ), ε) 4. (Construct regression polynomials for Dαg i (gi ) = f (Dαg i (g j ), ε))
3.5 Statistical Gate Level Simulation The proposed gate performance models form the basis of our statistical gate level simulation method. We observe that path delay variation in a circuit is primarily affected by correlations of parameters between gates, since the purely random variations cancel each other and leave virtually no effect on path delay variation [16]. Furthermore, process variations (e.g., of transistor threshold voltage and transistor channel length) are invariant during circuit runtime (e.g., at each time step during transient analysis), while signal waveforms are functions of the given process variation corner. For a simple and robust computation method for the correlations between process variations and signal waveforms, we prefer Monte Carlo simulation than analytical statistical moments and correlations based computation. We apply interpolation on the parameterized current source gate model to achieve gate performance for a given process variation corner.
3.6 Efficiency Analysis Our proposed parameterized models based gate level statistical simulation method achieves improved efficiency com-
pared with Monte Carlo SPICE simulation, because the constructed current source gate models and gate performance models provide higher levels of abstraction and more efficient computation. With the processes of model construction and Monte Carlo simulation separated, we reuse previous computation results (e.g., for model construction) for multiple instantiations of the same library cell, and in an iterative timing analysis flow which is needed in the presence of signal integrity (e.g., crosstalk coupling and supply voltage interference) effects. The sampling and simulation process in constructing the parameterized gate models costs runtime as Monte Carlo simulation. This runtime overhead can be reduced by applying model construction efficiency improvement techniques, e.g., adaptive sampling to selectively have more samples for the most frequently occurring variation corners [6]. The model construction sampling can be on-the-fly, i.e., combined with Monte Carlo simulation. In any way, the model construction runtime overhead is amortized in the presence of repeated instantiation of the same library cell with similar input signal transition times and load capacitance, which is usually the case in VLSI designs, and we observe that interpolation and extrapolation of input signal transition time and load capacitance induce little inaccuracy for statistical output signal arrival time computation.
Lgate . Each of the four variations is Gaussian with 3σ = 15%. Table 1 compares our gate performance model based Monte Carlo simulation with Monte Carlo SPICE simulation, and shows that gate performance model based Monte Carlo simulation achieves an average of 3.91% (9.19%) and a maximum 13.26% (19.71%) mismatch for the means (standard deviations) of gate output signal arrival times at 20%, 50%, and 80% voltage swing compared with Monte Carlo SPICE simulation results. We measure the runtimes on a Linux Redhat i686 workstation with a 2.8GHz P4 processor and 512M memory. Constructing parameterized current source gate models takes 0.016s for each of the Vth and Lgate process corners. Constructing parameterized gate performance models takes 0.00066s for each of the Tr , CL , Vth and Lgate variation corners. Gate performance model based Monte Carlo simulation takes 0.0015s for 100 runs. Monte Carlo SPICE simulation takes 0.25s for 100 runs with 1ps transient analysis time step. If we skip gate performance model construction, and apply Monte Carlo simulation based on parameterized current source gate models, it takes 0.066s for 100 runs. We achieve orders of magnitude of efficiency improvement compared with Monte Carlo SPICE simulation, by applying either Monte Carlo simulation based on parameterized current source gate models, or based on parameterized gate performance models.
4 Experiment 5 We validate our proposed parameterized models based gate level statistical simulation by comparing with Monte Carlo SPICE simulation on a list of simple logic gates (4× inverters, 4× 2-input NOR gates, and 8× 2-input NAND gates) in BPTM 90nm technology. We first construct a current source gate model by performing SPICE DC analysis for the gate output current with the gate input voltage and the gate output voltage both sweeping from 0 to 1.0V with a 0.1V step (which suffices for accuracy), and finding an intrinsic gate capacitance Cgo = 2.0 f F which is tuned for best match with SPICE transient analysis gate delay results [3, 7, 11]. For process variations, we construct a parameterized current source gate model by performing SPICE DC sweep analysis for the gate input voltage and the gate output voltage both ranging from 0 to 1V , and the transistor threshold voltages and the transistor channel lengths both ranging from 0.8× to 1.2× of the nominal values defined by BPTM 90nm technology. Figures 3 and 4 show the gate output current Ids as a function of the gate input voltage and the gate output voltage, and as a function of the transistor threshold voltage variation ratio and the transistor channel length variation ratio, respectively. For space efficiency, both functions can be approximated in a quadratic or piecewise linear function by applying regression. For accuracy, we construct lookup tables. We construct a gate performance model based on the parameterized current source gate model, and apply Monte Carlo simulation based on interpolation of the gate performance model. We have four independent process variations for input signal transition time Tr , output load capacitance CL , transistor threshold voltage Vth , and transistor channel length
Conclusion
We propose gate level statistical simulation for accuracy improvement over circuit statistical timing analysis and efficiency improvement over transistor level Monte Carlo SPICE simulation. We propose a multi-point signal waveform characterization method based on signal arrival times at multiple voltage thresholds. We propose parameterized current source gate models for process variations, and parameterized gate performance models for signal and process variations. We prefer Monte Carlo simulation than moments and correlations based statistical computation. Our experimental results show that our proposed gate level statistical simulation method achieves within 3.91% (9.19%) accuracy in average and orders of magnitude of efficiency improvement compared with Monte Carlo SPICE simulation. Our ongoing research includes extension of the proposed method to take an extended set of process, supply voltage, and temperature variations, and implementation of the proposed models and method in a circuit level statistical timing analyzer.
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Table 1. Means (ps) and standard deviations (ps) of gate output signal arrival times at multiple voltage thresholds given by parameterized gate model based statistical simulation (PGM) and Monte Carlo SPICE simulation (SPICE) with their CPU runtimes (sec.) in the presence of four independent variations: input signal transition time Tr , output load capacitance CL variation, transistor threshold voltage Vth , and transistor channel length Lgate . Instance PGM SPICE Name Tr CL D0.2 D0.5 D0.8 D0.2 Dg0.5 D0.8 g g g g g Inv-x4 10.0 20.0 µ 31.46 67.40 119.52 33.57 68.39 118.77 σ 3.89 8.55 15.61 3.67 8.31 14.01 10.0 50.0 µ 59.67 144.55 267.75 63.33 149.13 272.93 σ 8.60 21.25 36.53 8.12 19.64 33.72 10.0 100.0 µ 106.69 273.19 514.81 112.84 283.59 529.77 σ 16.52 41.33 71.37 15.55 38.52 66.53 10.0 200.0 µ 200.90 530.56 1009.01 211.82 552.51 1043.50 σ 32.31 81.49 141.04 30.39 76.26 132.17 Inv-x4 100.0 20.0 µ 123.29 167.29 219.28 125.70 168.55 219.15 σ 10.81 13.71 19.23 9.03 11.51 16.36 100.0 50.0 µ 157.02 242.90 366.10 161.50 247.92 371.73 σ 14.18 24.98 39.99 11.94 22.03 35.76 100.0 100.0 µ 204.02 370.51 612.17 210.90 381.65 627.83 σ 20.70 45.02 74.95 18.32 40.75 68.55 100.0 200.0 µ 297.62 627.37 1105.77 309.48 650.14 1141.10 σ 36.31 85.24 144.66 32.88 78.14 134.21 Nor2-x4 10.0 20.0 µ 53.74 125.71 227.36 58.92 129.10 229.23 σ 6.88 16.64 28.58 6.72 15.37 26.25 10.0 50.0 µ 112.73 282.83 522.93 120.86 292.68 535.03 σ 15.75 38.98 67.45 15.11 36.44 62.84 10.0 100.0 µ 211.11 544.71 1015.73 223.81 565.03 1044.50 σ 30.64 76.33 132.19 29.06 71.50 123.81 10.0 200.0 µ 408.16 1068.66 2001.51 429.56 1109.60 2063.40 σ 60.27 150.89 261.81 56.94 141.62 245.70 Nor2-x4 100.0 20.0 µ 150.02 223.54 325.15 154.76 226.36 326.49 σ 11.92 19.79 31.40 10.31 17.21 27.68 100.0 50.0 µ 208.20 378.34 618.45 216.39 388.20 630.55 σ 19.42 42.21 70.41 17.32 38.09 64.29 100.0 100.0 µ 305.45 639.17 1110.00 318.66 659.87 1139.40 σ 34.07 79.64 135.39 31.07 73.19 125.37 100.0 200.0 µ 501.68 1162.45 2094.93 524.07 1204.10 2157.90 σ 63.81 154.26 264.99 58.88 143.37 247.37 Nand2-x8 10.0 20.0 µ 21.07 39.04 65.18 24.29 42.62 69.27 σ 2.20 4.82 8.03 2.30 4.69 7.67 10.0 50.0 µ 35.05 77.55 139.34 39.28 83.06 146.40 σ 4.53 10.83 18.51 4.53 10.37 17.53 10.0 100.0 µ 58.46 141.76 262.99 64.03 150.32 274.86 σ 8.49 20.89 35.98 8.24 19.81 33.95 10.0 200.0 µ 105.45 270.33 510.35 113.52 284.77 531.67 σ 16.38 40.99 70.96 15.66 38.69 66.77 Nand2-x8 100.0 20.0 µ 104.25 135.72 165.51 108.96 139.69 169.76 σ 9.56 10.84 12.47 8.02 9.30 10.85 100.0 50.0 µ 126.96 176.36 238.34 132.73 182.36 245.74 σ 11.66 15.15 22.16 9.85 13.25 19.83 100.0 100.0 µ 155.01 239.45 360.70 161.86 248.77 373.31 σ 14.24 24.68 39.55 12.11 22.28 36.07 100.0 200.0 µ 202.21 367.23 607.26 211.40 382.65 629.55 σ 20.72 44.69 74.57 18.48 40.99 68.84
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