The sigma delta modulation and the loop filter must be effective enough to change quickly the VCO control in case of frequency hopping and at the same time to.
J. Park, F. Maloberti: "Phase noise improvement in fractional-N synthesizer with 90° phase shift lock"; Proc. of the 2003 Int. Symposium on Circuits and Systems, ISCAS 2003, Bangkok, 25-‐28 May 2003, Vol. 1, pp. 733-‐736. ©20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Phase Noise Improvement in Fractional-N Synthesizer with 90"Phase Shift Lock Joohwan Park 'I), Franco Maloberti 'I.') (1) Department of Electrical Engineering, University of Texas at Dallas, Texas, USA ( 2 ) Department of Electronics, University of Pavia, Italy
ABSTRACT An effective technique for phase noise improvement in a fractional-N synthesizer is described. The method requires using in a 90" phase shift lock a non-linear continuous-time or sampled-data block before the loop filter. Behavioral simulations on a fractional-N synthesizer incorporating different non-linear blocks and a second-order single bit sigma delta modulator show that it is possible to achieve phase noise improvements at medium frequency as good as 17 dB.
1. INTRODUCTION PLL has become widely used in communication circuits. It is used in frequency synthesizers, frequency multipliers, modulators and demodulators. Communication systems require a high level of integration, low power and low cost at the same time. Moreover, the PLL must comply with the frequency hopping requirements and. the low phase noise output in the IF receiver and the upconversion transmitter. The use of a sigma delta modulator in the PLL control obtains a fractional division of the output frequency while the noise associated to phase fluctuations is shaped at high frequency. The circuits using the above-mentioned architecture accomplish high integration and relatively fast settling time. The sigma delta modulation and the loop filter must be effective enough to change quickly the VCO control in case of frequency hopping and at the same time to continuously vary the divider value so that the filter produces a precise control of the VCO when the required frequency is locked. Because of the constant value of thz fraction used, the effectiveness is limited and even with high order modulator some phase noise around the target frequency remains. This work shows how to improve the phase noise of a fractional-N synthesizer in the phase lock mode (achieved its steady state). The technique .exploits the features of a 90' phase shift proposed by the authors in a previous paper [l]. The basic idea is to use a non-linear block before the loop filter. The non-linear response of that block reduces the phase jitter in the lock mode while it maintains the full functionality in the acquisition (i.e. when the PLL is tracking the desired frequency). Section 2 summarizes the operation of the fractional-N PLL and the already proposed 90" phase shift lock. Section 3
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Fig. 1 - Fractional synthesizer with &A modulation compares the conventional and the 90" phase shift solution, the next section describes the proposed method and Section 5 shows simulation results.
2. FRACTIONAL-N SYNTHESIZER The basic building blocks of a synthesizer are the PFD, the low pass filter (LPF), the voltage controlled oscillator (VCO) and the divider (Fig. I). The PFD compares a reference frequency with a feedback signal and generates pulses to control the charge pump. If the divider uses an integer number the output of the LPF, after a transient, is constant. However, in order to obtain fine channel spacing the division factor periodically changes between two (or more) integer numbers (fractional division). The main design issue is the trade-off between channel frequency spacing, settling time, and phase noise. Using a sigma delta to control the divider achieves a good compromise. However, even if the control of the NiN+l divider value is well randomized, the discrete nature of the operation causes some fluctuation (phase noise) in the VCO control. Fig. 2 depicts the situation for an integer-N and a fractionalN synthesizer. In both cases a large ringing of the VCO control characterizes the acquisition. However, after that period (which must be small in frequency hopping applications) the constant divider factor use in integer-N
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synthesizers makes the control flat. In contrast, the control fluctuates continuously in the fractional-N synthesizer thus generating phase noise. The phase noise can he improved with multi-hit sigma delta loops [ 2 ] or, as proposed in [ 3 ] and [4], by the use of multi-loop filters and bandwidth programmable filters. The technique enables reducing the loop bandwidth in the phase lock mode. The method is effective; however, the complexity of the system increases. Moreover, problems associated to the uncertainty in the transition between acquisition and phase lock lead to a longer PLL settling time.
(a) (b) Fig. 5 - Loop filter input for (a)conventional (b)90° phase shift.
3. 0" AND 90' PHASE SHIFT LOCK In a conventional PLL the charge pump injects a positive or negative current into the loop filter. The output of the charge pump is a sequence of pulses that, in the phase lock mode, are very short and randomly positive and negative (Fig. 3). In a 90° phase shift lock the output of the charge pump is integrated over a storing capacitor to generate the input for the loop filter at the end of half of the reference signal period[l]. In order to avoid the uncertainty associated with the rising and falling edge in the generated current, the control of the system is such that the current at the output of the charge pump is a bipolar signal with approximately 50% duty cycle. The signal at the end of the period directly measures the phase shift, as shown in Fig. 4. The 90' phase shift operation permits us to replace the continuous time loop filter with a more practical switched capacitor filter, followed by a smoothing filter. Observe that the output of the conventional charge pump and the voltage across the storing capacitor differ. This is because of the integration and dump over the storing capacitor Cs of the current pulses
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produced by the charge pump and transformed into voltage. The SC loop filter will take care of the additional integration-and-dump in this processing. Fig. 5 compares the signals at the input of the loop filter in cunventional and the 90" solutions. The information in the former case is incorporated in the sign of current pulses and in the pulse duration. The information in the latter is in the sign of the voltage across the storing capacitor and its amplitude. Large pulse durations or large amplitudes mean a significant change of the VCO input. Therefore, those situations likely occur in the acquisition. Short pulses or small amplitudes with signs that reverse randomly cause negligible modifications of the VCO control. Therefore. those circumstances indicate a phase lock state. The above observations are qualitative. However, we can associate a range of the signal at the input of the loop filter to the phase lock mode (lock zone, around zero) and the remaining part to the acquisition (track zone). In order to reduce the phase noise it is necessary to desensitize the VCO control when the loop filter input is in the lock zone and to leave the control unchanged outside. This operation can he easily obtained for the 90" solution only. It just requires using a non-linear block in front of the SC loop filter. This block is named "phase noise limiter". Its function is to attenuate small signals and to leave large signals unchanged. However, as we will see in the next section, special responses in the lock zone will determine different phase noise improvement.
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verified the proposed methodology. For each block of the PLL loop suitable models have been used. The test vehicle is a PLL with 1 MHz input frequency and division factor equal to 128.7234. The sigma-delta modulator used is a second order single-bit architecture [ 5 ] . The switched capacitor loop filter is optimized to minimize the silicon area. The total capacitance is as low as 18.7pF. A conventional counterpart would require an extemal capacitor of 330pF. Consequently, the expected phase noise performances are not optimum. Fig. 9 shows the spectrum of the generated frequency without any PNL. The phase noise is -64.03 dB at 10 KHz, -65.4 dB at 50 KHz and -70.32 dB at 150 KHz. Using the
(b) Case 2 Fig. I -Circuit implementation of PNL responses. the second response of Fig. 6 requires a non-linear block. Fig. 7 shows possible implementations. Lower gains in the lock zone will increase the benefit of the method. However, there is a limit in the gain reduction. The signal at the output of the PNL must be large enough to ensure that the locking is not lost. Observe that action of the sigma delta in the phase lock inode is just moving the voltage at the VCO back and forth around the desired lock value. The noise shaping pushes the associated noise at high frequency. A similar behavior can result from a stronger non-linearity in the phase noise limitel Fig. 8 shows two possible altemative PNL responses. The output of the PNL is positive for positive inputs and viceversa. However, in the lock zone the responses show a sawtooth behavior. Therefore, in the lock zone the sign is preserved but its amplitude is made "uncertain". This would push the output power to high frequency thus favoring a more effective loop filtering. The PNL response of Fig. 8 looks like the output of the residual generator in a multi-bil pipeline ADC. Its implementation will require using circuits similar to the one used in pipeline converters.
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Case 3 is not a good non-linear response: the output in the track zone is lower than the input. The threshold between lock and track zones is not a sharp boundary Circumstances for which the signal is high in the lock mode require an immediate “push b a c k . The strong non-linearity is very effective for reducing the phase noise at medium and high frequency. In order to obtain equivalent performances case 1 and case 2 must use a very low gain (0.2 and 0.1 respectively) in the lock zone.
Table 1 resumes the phase noise improvements for the four cases studied. Clearly the benefits depend on the specific gain and amplitude of the lock zone used. However, the results provide a clear indication of the effectiveness of the method and a rough comparison of different PNL responses. Table I . - Phase Noise Improvements (dBc)
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The use of a non-linear block that desensitizes the charge pump effect for low PDF output significantly improves the phase noise. We have applied the method to a 90’ phase shift lock architecture by using different non-linear responses. The phase noise improvement can he as high as 17 dB while strongly maintaining the locking state.
7. REFERENCES [I] [Z]
Fig. 13 - Frequency spectrum with case 4 PNL PNL of Fig. 6 a) (gain = 0.2) and Fig. 6 b) (0.1 Vin + e’vifl‘hi)leads to the spectra shown in Fig. 10 and Fig. 11. The results with strongly non-linear PNL are shown in Fig. 12 (case 3) and Fig. 13 (case 4). We can observe that 0
The method does not improve the phase noise at very low frequencies (in cases 3 and 4 we have a worsening). Some noise folding due to non-linearity likely compensates for the effect of the attenuation in the lockzone.
[3] [4]
[5]
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J. Park and F. Maloherti, “Use of a 9 0 ~Phase Shift Detector and Sampled-Data Loop Filter in PLL,” IEEE Proc. ISCAS’OZ, vol. 2 , pp.400-403, 2002. W. Rhee, A. Ali and B. Song, “A I.IGHz CMOS FractionalN Frequency Synthesizer with a 3h 3rd-order EA Modulator,” ISSCCDigestof TechnicalPapers, pp. 198-199, 1999. T. Kwan and K. Martin, “An Adaptive Notch-Filter-Based Frequency-Difference Detector and Its Applications,” IEEE Trans.Commu,t.. vol. 43, pp. 2784-2793, 1995. Y. Tang, M. lsmail and S. Bibyk, “A New Fast-settling Gearshift Adaptive PLL to Extcnd Loop Bandwidth Enhancement in Frequency Synthesizers,” IEEE Proc. ISCAS’OZ, vol. 4, pp. 787-790, 2002. P. A i r , J. Sorensen and J. Spiegel, “An Overview of SigmaDelta Converters,” IEEE Signal Processing Magazirte. vol. 13. pp.61-84, 1996.
