PHY. (Manchester). EEPROM. Memory. Controller. GEAR. Timer tx_o rx_i. DALI status_i level_o. LFSR ... Program FADE TIME = 4s. Start fading to OFF yes ... All the process was executed and controlled by a Python script running on the PC.
Dali IP Core
Iberchip
Valinoti Bruno, Melo Rodrigo, Tozzi Leandro, Salomo´n Francisco {valinoti,rmelo,ltozzi,fsalomon}@inti.gob.ar
XXII Workshop
Instituto Nacional de Tecnolog´ıa Industrial Centro de Micro y Nanoelectro´nica
Introduction The analog team of our center developed a LED driver IC. To add value to it as a comercial product, we made a Digital Addressable Lighting Interface IP core. We follow the IEC-62386 standar for a LED Control Gear. DALI is a royalty-free, non proprietary, open protocol, that allows compatibility between products of different manufacturers. It provides a solution to control the lighting of a building in a smart way. A typical network consists in at least one master controller and several slave devices, which are also called gears (ballasts, leds, dimmers, switches, and more), interconnected over a two wire bus. The standard is composed by General Requirements (parts 10x), Particular requirements for Control Gears (parts 20x) and Particular requirements for Control Devices (parts 30x). For a LED driver control gear we used the parts 101, 102 and 207.
Network
Testing Clause 12 of each part introduces the Test Procedures and specifies the complete test sequences that DALI devices should pass. The test consists of an activation phase and a validation phase, in the first stage a command is sent to the DUT, in the second phase the internal state of the device must be checked by query commands. A typical test sequence is presented below:
D0
+
D0
+
DALI CONTROLLER
DALI sensor
D1
LED DRIVER
DALI switch
DALI CONTROLLER
D1
LED DRIVER
D0 D1
+-
Test: Fade running
SEND TWICE BROADCAST RESET
Set the DUT in reset state Answer = xxx1xxxxb?
Wait 300ms + resp
Implementation rx_i
PHY (Manchester)
DALI tx_o
EEPROM Memory Controller
SEND TWICE BROADCAST DAPC(0)
status_i
LFSR Dimmer
Y A5 A4 A3 A2 A1 A0 S D7 D6 D5 D4 D3 D2 D1 D0
D7
D6
D5
D4
D3
D2
D1
D0
• Backward Frames: From masters to slaves, 16 bits long. • Forward Frames: From slaves to masters, 8 bit long. Depending on the ”Y ” bit the message could be broadcast/group or individual addresed.
Program FADE TIME = 4s
Start fading to OFF
Answer = xxx1xxxxb?
SEND TWICE BROADCAST QUERY STATUS
Answer = xxxxx1xxb?
SEND TWICE BROADCAST QUERY STATUS
Read status
yes
Error 6173 “Fade running bit Not cleared after fading”
no
no
Error 6171 “Load switched off inmediately”
Test Done
yes
The test sequences were all described in VHDL and tested with GHDL.
The entire protocol implementation has required, a hierarchical command decoder and coordinator, a Manchester differential codec, a 24-bit LFSR, an EEPROM memory controller and a Dimmer controller as main components. The final design application is for an ASIC, but the core was developed for a Spartan 6 Xilinx FPGA so the non volatile memory has to be made using the FPGA’s BRAM, emulating all the EEPROM timing and functions. Thus, a complete validation of the core design could be made later.
Frames & Addressing
Wait 5s
STORE DTR AS FADE TIME
GEAR Timer
SEND TWICE BROADCAST
Error 6172 “Fade running bit not Set during fading”
yes
SEND BROADCAST DTR(6)
level_o
no
Commands • Arc Power Level Control • Configuration • Query • Special • Application Extended From the part 102 the 171 commands were implemented and from part 207, 20 commands. Originally the part 207 has 25 commands, but due to lack of the required measurement hardware, 5 of those 25 were not implemented.
Validation The core validation was made in a Spartan 6 Xilinx FPGA conected by an USB cable to a PC. The PC runs as a master device sending messages to the gear slave device, the arc power level is sent all the time to the master except when answers are required. All the process was executed and controlled by a Python script running on the PC.
Conclusions The core was developed using standard VHDL’93, both the whole core simulation and unit tests and protocol testbenches were made using GHDL 0.31 and GTKWave 3.3.62, the synthesis and bitstream transferring with Xilinx tools. The usage of standard VHDL 93 allows the design portability between ASIC and FPGA. An IP Core of a DALI Control Gear for a LED Module was made, simulated and validated in hardware accordingly to IEC-62386 standard. No others FPGA implementations were found at the begin of the development. For an ASIC implementation the Non Volatile Memory controller should be modified depending on the kind of memory selected.
