Power Integration Module for Personal Computers

Power Integration Module for Personal Computers By: Alan Elbanhawy Fairchild Semiconductor Abstract: One of the most competitive fields in the DC-DC converter business is the core converter for personal computers where given a reasonable performance cost is the most important factor that determines the success or failure of a given design. Integrated power modules have not proven to be very successful in this niche with the exception of a couple of very specialized examples where the space and performance requirements are much more important than price. At the present time there is a major push for integrated modules for the price sensitive market where both silicon and packaging technologies are culminating in integrated devices that offer an amazing price/performance value proposition namely Driver MOS. Introduction: The most common switching frequencies of core DC-DC converters are in the 200kHz – 1MHz range. Design approaches that lie towards the lower end of this range are very well understood and have been very successful for sometime now while those towards the high end cannot claim the same success since these higher frequencies offer more challenges to the design engineer. Integrated modules like Driver MOS attempt to address this gap by providing a device that has been fully optimized both an the silicon and packaging arenas. This approach allows the design engineer to concentrate his/her efforts more on the system performance and less on the power train discrete component selection and layout. Furthermore this optimization goes further by selecting the right combination of driver and MOSFETs in a way only a semiconductor company can since they have infinite flexibility to fine tune the design of these components without the restrictions of available parts.

Figure 1, Multiphase Synchronous buck converter

Choice of topology: The multiphase synchronous buck converter has been the topology of choice for a number of reasons namely simplicity of design, high efficiency, high frequency operation and ease of control. This very fact necessitates that any design that targets the personal computer (PC) core converters must be adaptable to this very specific topology. The approach we took was to integrate all the MOSFETs and drivers in one package that follows Intel specification of Driver MOS (Driver plus MOSFET) Challenges: The challenges that face any power module design team may be summarized as follows: 1. The design must have the highest efficiency available given the latest silicon technology for both the drives and the MOSFETs 2. The design must have the smallest silicon possible to do the job and no more 3. Package selection where several factors come to play namely parasitic resistors and inductances, footprint, high frequency operation and ultimately cost 4. Because of the minimal spacing between the control MOSFET (HS) and the synchronous rectifier (LS) and the gate driver, the power circuit has very little loop inductance which introduces a whole new set of issues that arise from the switching high currents in such very low inductance environment. To elaborate on this fact a little bit, simulation using physics models clearly shows that the reverse recovery current of the LS MOSFET is dependant on the loop inductance and very excessive reverse recovery currents of may flow during switching causing serious ringing. This issue must be seriously addressed before the rest of the development proceeds. Design Approach: Since the package and footprint was already specified by the Driver MOS specification, the bulk of the development effort concentrated on device selection, placement and wire bonding to minimize the added parasitic resistances that

could rob few precious efficiency percentage points and critically marginalize the module’s performance.

PWM

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Driver Logic

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Figure 4 depicts the efficiency measures done on a two phase implementation with an input voltage of 12 V, an output voltage of 1.3V at a switching frequency of 300 kHz. As can be seen, we were able to achieve 32.5 Ampere per phase at an efficiency of over 80% in still air. The thermal performance was also confirmed by using infrared imaging of the test board at full current. Figure 5 depicts the infrared thermal image of the modules. The image shows that the average temperature of the Driver MOS module is around 115°C well within the safe operating temperature range.

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Figure 2, Driver MOS simplified block diagram

2-Phase DrMOS Power Efficiency

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Pwr Efficiency

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Figure 3, Driver MOS module outlines

Since our goal from the beginning was to offer the best possible price/performance value proposition, the silicon selection concentrated on highest density technology from Fairchild that allows us to find the minimum device sizes for both the high and low side MOSFETs leading to an excellent price/performance combination. The design target was to achieve a 30 Ampere per phase over the applicable switching frequency range of 200 kHz-500 kHz. Laboratory Verifications: Since the target application is a PC core converter, a two phase experimental PCB board was designed using a four layer one ounce approach. The PCB design in my opinion is one of the most important activities that can lead to successful implementation. High frequency and high current layout techniques were implemented to guarantee ultra low parasitic resistances and inductances to achieve both low PCB losses and good EMI performance.

Figure 4, Efficiency

Figure 5, Thermal image

In all modern PCs, an integrated heat sink + fan unit is mounted directly on the CPU to effect direct cooling. The power stage including the Driver MOS module is a direct beneficiary of the air flow from the fan. This air flow is usually in excess of 400FPM enough to cool the module and motherboard and guarantee safe operation and high reliability. Design Challenges: In integrated modules, the distances between the different components are shrunk significantly when

compared the discrete layout. This results in an interconnection scheme with very little parasitic inductances. Some non intuitive results of this is that the reverse recovery current magnitude becomes very large leading to significant ringing if not managed properly. Figure 6, below shows reverse recovery currents as a function of the loop inductance. These results were obtained using a finite element, physics based modeling software.

0.00E+00 6.60E-

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-1.00E+01 -1.50E+01 -2.00E+01

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Figure 6, Reverse recovery current as a function of loop inductance

Conclusion: 1. Integration of power trains in single modules is becoming a very viable alternative to discrete implementation as it offers very optimized component, package and layout solution 2. The very small space that these module occupy coupled with their high current handling capabilities results in several challenges that need to be addressed prior to design finalization and adoption 3. Integration is expected to the way of the near future References: [1] A. Elbanhawy, "Effect of Parasitic Inductance on switching performance" in Proc. PCIM Europe 2003, pp.251-255 [2] A. Elbanhawy, "Effect of Parasitic inductance on switching performance of Synchronous Buck Converter" in Proc. Intel Technology Symposium 2003 [3] A. Elbanhawy, “Mathematical Treatment for HS MOSFET Turn Off" in Proc. PEDS 2003 [4] A. Elbanhawy, "A quantum Leap in Semiconductor packaging" in Proc. PCIM China, pp. 60-64

[5] A. Elbanhawy, “The Road to 200 Amps at one Volt VRM” in Proc. PCIM Europe 2004, pp. 54-58 [6] A. Elbanhawy and W. Newberry, “Packaging Parasitic Resistance Frequency Effects” Power Electronics Conference USA 2004 PCIM San Francisco” [7] A. Elbanhawy “Are traditional packages suitable for the new generation of DC-DC converter” in Proc. IPEMC China 2004