practical insights on selecting the right processor for your application
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practical insights on selecting the right processor for your application
solution. ⢠Certification â DO178B, Sil3. ⢠Examples in use in space missions. ⢠RTEMS, VxWorks, uC/Osii, eCOS, Linux (RTAI and Xluna). Operating Systems ...
PRACTICAL INSIGHTS ON SELECTING THE RIGHT PROCESSOR FOR YOUR APPLICATION
It is a bit more complicated than
• • • •
Need a More Structured Approach – 10,000 Ft view Mission Requirements Operating Environment Component Availability Experience and Heritage
Harsh Environment – Getting There Launch • Acoustic Loading • Vibration • Random and Sine • Shock • Depressurisation – Venting • Electro Magnetic Interference
Harsh Environment – Operating there Operation • Temperature • Radiation • Reliability • Long Operating life • Electro Magnetic Interference
What are some of the Processors are Available Processor
Architecture
MIPS
Comments
LEON 3 FT ASIC Dual
SPARC V8
200
100 MHz
LEON 3 FT AISC Single
SPARC V8
75
66 MHz
LEON 3 FT FPGA RTAX
SPARC V8
20
25 MHz
RAD 750
Power PC
400
200 MHz
PC 7448
Power PC
3000
1267 MHz
ARM7-TDMI
ARM7
36
40 MHz Cubesat Not Rad Hard
Mongoose-V
MIPS R3000
8
10 - 15 MHz
Redundancy Architecture
Performance
Power Management
PCB Mounting
Processor Selection
Radiation
Operating Systems
Communication IF’s
Debugging Tools
Performance • Key Driver for achieving mission requirements • Million Instructions Per Second • Number of Instructions per Clock Cycle – Scalar / Vector / Superscalar • Floating Point Unit • Multicore • Hardware Acceleration / Peripherals • Direct Memory Access • Memory Bandwidth
Power Management • Drives the thermal management of the payload – Conversion losses • How many voltage rails are required – this complicates the power architecture - increasing losses and decreasing MTBF, Weight etc. • Does the processor have low power modes • Can we reduce the core frequency if desired – Dynamic Power Management • Voltage scaling
Communication IF’s
• How our equipment communicates externally • On Chip Peripherals for communication • Simple UART, SPI, I2C, Ethernet, PCIe • DMA Provided to reduce load on processor • Is the bandwidth sufficient for the application requirements
Operating Systems • Operating system enables scheduling of processes and processor resources • Application dependant • Hard Real Time • Soft Real Time • Do we need an operating system – Can it be achieved using a bare metal solution • Certification – DO178B, Sil3 • Examples in use in space missions • RTEMS, VxWorks, uC/Osii, eCOS, Linux (RTAI and Xluna)
Debugging Tools • Development Environment • Can we debug at the system level • Can we examine the processor state without impacting programme execution • Can we profile the application • Can we trace where the processor has been • Is it possible to analyse communication protocols on communication interfaces
PCB Mounting • • • •
Often the most over looked aspect Is it BGA, CGA or QFP Impacts reliability – BGA balls fail, Column Crack, How it mounts has a large impact on how we perform thermal management. • Number of IO required • Is the mounting method currently qualified for your manufacturing facility
Radiation Tolerance • Is the device latch up immune • Can it experience SEUs • What is the maximum Total Ionising Dose • Does the processor contain fault tolerant circuits e.g ECC / EDAC to correct for faults • Is there a watchdog provided for lock ups – often ths needs to be independent.
Redundancy Architecture
• Is Redundancy required ? • Inter or Intra module • Hot or Cold spared • Cost and Weight driver • Redundancy approach for SW • External / internal watchdog provided for SEFI
SW Techniques • For Space Applications there are some mitigation strategies we can follow • Redundancy at the Instruction level • Redundancy at task level • Redundancy at application level • ESA Handbook – Techniques for Radiation Effects Mitigation in ASICs and FPGAs is provides a good understanding for all engineers – does include a section on processors.
HW Design Cost
Component Cost
SW Design Costs
Technical Risks
Processor Selection
Programme Risks
Schedule
Design Reuse
Heritage & TRL
Costs • Goal is meeting mission requirements within the available budget. • Number of Cost drivers • Bill of Materials • Engineering Life Cycle costs – design reviews • Design / Verification / Integration costs for HW and SW • Certification programmes
Risks – Technical and Programmatic
• Any Programme will have a number of risks technical and programmatic • Technical risks relate to engineering aspects i.e. Quality • Programmatic relate to cost and timescale • Process • Identify candidate risks • Identify applicable standards, laws, agreements and company policies • Analyse Risks / Plan Risk Management / Evaluate • Risk Profile and Risk Strategy will result
Schedule • Not necessarily the domain of the project manager but also the Work Package Manager. • All projects want to deliver • On Schedule, On Cost, On Quality • Schedule will define the engineering and programmatic milestones – enables progress to be tracked • Crucially it will enable past performance to be used as an indicator of future performance • If you are slipping 6 months in 12 months for example, without addressing the issues via a recovery programme future performance will continue to slip 6 months in 12.
Heritage & TRL • Does the processor have any heritage in the application. Reduces risk of implementation or qualification issues • Technology Readiness Level • Determines the readiness level of the technology to be used in your application • ESA have 9 levels from concept to proven and used on a mission. • TRL development plan – shows the path taken to prove the system to the required level.
Design Reuse
• Enables faster time to market • Requires a development rules to enable reuse • Increases quality as it is used across several projects • Enables the estimation of new projects to be undertaken easier •
Conclusion • Technical and Programmatic considerations have been presented • Criteria's use depends upon your application • Thank you for listening Questions ?