APEMC 2015
Predicting EMI Induced Delay Errors in Integrated Circuits: Sensitivity to the Velocity Saturation Index ' ' # #l Xu Gao , Chunchun Sui , Sarneer Hernrnady , Joey Rivera , Lisa Andivahis+, # #2 David Pornrnerenke , and Daryl Beetner # EMC
Laboratory, Missouri University of Science and Technology Rolla, MO, USA '
[email protected], '
[email protected] *
TechFlow Scientific,
Albuquerque,lVA{, USA +
Defense Threat Reduction Agency, Albuquerque,lVA{, USA
Abstract- Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, such as might occur during an electrical fast transient (EFT). A delay model was proposed in [I] which can be used to predict the variations in the delays through logic circuits caused by electromagnetic induced noise in the power supply voltage. This model is relatively simple and requires few parameters, giving it the potential to be used even when the IC is a "black box" and little information is available about the inner circuits. While design information might be approximated through testing, critical process characteristics may not be available which are needed for accurate results. The parameter of greatest concern is the velocity saturation index, since this parameter can exponentially increase the impact of power supply noise on delay. This paper describes an investigation of the sensitivity of the delay model in [I] to the velocity saturation index. Resnlts indicate that the estimated delay, found while treating much of the circuit as a black box, is largely insensitive to the velocity saturation index. This result suggests that this model can be used effectively for prediction of electromagnetically-induced delay errors, even when limited process or circuit information is known. 1.
INTRODUCTION
The power supply voltage of integrated circuits (ICs) shrinks each year. This shrinking supply voltage causes shrinking noise margins, meaning that even small fluctuations in the power supply can cause failures in the IC. While several recent studies have focussed on predicting the level of voltage fluctuation in an IC caused by an external electromagnetic event [2][3], methods are needed to better predict when failures will occur as a result of these fluctuations. A common reason for IC failure is that a change in the power supply voltage causes a change in the propagation delay through internal logic or the clock tree, resulting in a clock edge arriving at a register before valid data, so that an incorrect logic value is stored at the register [4]. Accurate delay models are needed to predict if electromagnetically-induced power supply fluctuations will cause timing errors inside the IC. Delay models for logic gates are available in the literature to help predict maximum clock speed in the presence of simultaneous switching noise on the on-die power supply
978-1-4799-6670-7/15/$31.00
Copyright
2015
IEEE
[5], [6]. These models are extended in the [1] to predict variations in the propagation delay through a logic circuit as a result of electromagnetic noise, in this case an EFT, applied to the power supply. The model in [1] works has been shown to work well when using complete information about the circuit under test. In many cases, however, one would like to apply this model to off-the-shelfICs where the user has limited information about the inner circuit or even the process parameters. The main process parameter of concern in the velocity saturation index, since a change in this parameter can exponentially change the relationship between delay and the power supply voltage. Other parameters can be estimated more easily experimentally. In this paper, the delay model proposed in [1] is investigated to demonstrate its sensitivity to the velocity saturation index. A study of the estimated delays through a ring inverter was conducted while varying the value of the saturation index used in the model. Results demonstrate that errors in the value of the velocity saturation index are compensated for by estimates of other model parameters found experimentally based on the assumed velocity saturation index. The relative insensitivity of the delay model to the estimated velocity saturation index suggests the model can be used effectively even when this parameter is unknown. II. DELAY MODEL A delay model for generic logic circuits was proposed in [1] and validated experimentally on a ring oscillator. As shown in this paper, the propagation delay through a logic circuit is given by: V2dd V2 dd M . (1) tpLH' tpHL =M n · ) a p+ l (V -Vh ) a,+l + P (V V + n t dd th.p dd where Vdd is the power supply voltage, V,h.n and V,h,p are the threshold voltages for the NFET and PFET, respectively, an and a are the velocity saturation indices for the NFET p and PFET, respectively, which vary from 1 to 2, and and the
102
M
p
Mn
are Uf1known constants which are independent of
power
supply
voltage
but
depend
instead
on
APEMC 2015
characteristics of the logic design itself like the size of the FETs, number of gates, and other properties. Because Mn and M are independent of the power p supply voltage, they can be calculated by measuring the periods of the oscillator, r; and T2, at two different power supply voltages, Vdd.1 and Vdd•2 . Mn and by solving the equation:
[Nl N2
where
M
p
can be found
Vdd Injection port
Ou�tpu�t �__���ut���
(2)
Oscilloscope rt fo�nit�o'�Po4
Test board Fig. 2. Test setup.
(3) III. SENSITIVITY TO THE VELOCITY SATURATION INDEX
and Pi
=
2 Vdd.i
a +1 .
(Vdd•i + V,h. P ) Note that the value of the velocity saturation is required to solve for parameters Mn and M . P
p
The delay model in (1) was validated through experiments on a test IC implemented in 0.5 micron technology. A ring oscillator with 11 inverters was implemented in the test IC, as shown in Fig. 1. The frequency of oscillation was measured while applying EFTs to the power supply input.
The delay model in (1) requires knowledge of the velocity saturation index, denoted by an and a . These p parameters range from 1 to 2 and can be calculated from IV curves for the NFET and PFET. Their values, however, are difficult to extract when there is no knowledge of the inner workings of the IC and no test structures available specifically for this testing. This scenario can occur when one attempts to model an off-the-shelf IC, with no information about the process used to manufacture the IC. Since values of an and a may be difficult to obtain, the p sensitivity of the model to their values was investigated. The error in the estimated frequency of the ring oscillator in Fig. 1 was found will varying the values of an and a . Values p of Mn and M were found for each value of the velocity p
Fig. 1. A ring oscillator.
Fig. 2 shows the test setup. An EFT generator was connected to the IC Vdd pin through a 40 dB attenuator and a 33 nF capacitor. The 40 dB attenuator was used to avoid physical damage to the Ie. A 4.7 nF off-chip decoupling capacitor was mounted near to the Vdd pin of the test IC to minimize switching noise from the IC itself. A DC power supply was connected to the Vdd pin through a ferrite and inductor to decouple the power supply from the EFT test. The Vdd pin and the output of the ring oscillator were monitored using a 1 kohm resistive probe. EFTs were injected into the IC while measuring the frequency of the ring oscillator. The measured frequency was compared to the frequency predicted by the delay model in (1). The values of process parameters (e.g. V,h.n,
V,h.p, an' and ap) were found from simulation models of the FETs and values of Mn and M were found from p simulations of the inverters. Predicted results closely matched those found through measurements, demonstrating the accuracy of the model. The maximum relative error between simulations and measurements among EFT injections was approximately 1% [1].
saturation index, as given in (2) and (3). Fig. 3 shows the resulting modelling error and Fig. 4 shows the estimated frequency of the oscillator during an EFT found using three different values of an and a as examples. Fig. 3 shows p the maximum and absolute relative error in frequency, defined as: max. relative frequency error
=
(4)
max I Measured freq - Calculated freq I Measured freq and max. abs. frequency error
=
max I Measured freq - Calculated freq I
(Hz)
(5)
The top 2 plots in Fig. 3 show the errors in full scale. The bottom two figures show the errors over a small scale in order to better show variations where errors are small. Most values of an and a generate relatively small values of p error. Large errors only happen along a narrow line. Most values of an and a generate relative errors below a few p percent.
103
APEMC 2015
2
Maximum Relative Frequency Error
Maximum Absolute Frequency Error
2
1.8
1.8
"- 1.6 ",I "
