process variability and device mismatch - CiteSeerX

1/4

PROCESS VARIABILITY AND DEVICE MISMATCH Manolis T. Terrovitis and Costas J. Spanos Department of Electrical Engineering & Computer Sciences University of California, Berkeley CA 94720 office: (510) 643-6776, home: (510) 635-1882, fax: (510) 642-2739 e-mail: [email protected]

Abstract

D y

The types of process variation causing device mismatch are investigated. A set of test structures intended to examine a broad range of device and mismatch causes has been fabricated. Some sample results obtained by statistical processing of electrical measurements are presented.

1.0

Introduction

Mismatch is defined as the difference in the value of a device parameter among identically designed devices. There are certain kinds of process parameter variation whose combined effect causes device mismatch.

L

A1

A2

W

W x

Figure 1

A pair of identically designed devices

cause mismatch on parallel devices, while they do on devices with perpendicular orientation. If the devices are directional, such as the MOS transistors, mismatch can be caused in parallel devices by currents flowing in opposite directions.

The first kind of variation is related to the specific layout geometry and is caused by other structures surrounding the devices. Lithographic and etch rate effects such as ‘microloading’ are some causes. Dummy devices are used to create a similar environment for devices that we desire to be matched. The necessary number and size of the dummy devices are investigated below.

2.0

The second kind of variation is large gradients. In a well controlled production line, significant part of this kind is repeatable, with systematic components in the die and the wafer. The die components are attributed mainly to non-uniform behavior of the stepper across the stepper field. The wafer components are due to processing imperfections during operations that affect the entire surface of the wafer, such as non uniform photoresist deposition, nonuniform implantation, and temperature or gas concentration variation across the surface during oxidation. Close spacing and common centroid geometry are used to minimize the effect of the large gradients of variation.

In general, a device parameter P can be expressed as a function of the effective values of n process parameters q , q ,... q , which are physical quanti1 2 n ties, such as dimensions and implanted ion concentrations (1) P = f ( q , q , ..q ) . 1 2 n Effective values are defined as the lumped values of the process parameters that when used in the model equation (1) give the correct value for the device parameter, which in reality depends on the value of the process parameters at every point in the area of the device. Since the variation of a process parameter in the area of the device is generally small compared to its average value, it is reasonable to consider that the effective value is equal to the average.

The third kind is local random fluctuations of the process parameters that resemble spatial white noise. Some examples are the thickness variation in a poly1poly2 capacitor because of the granular nature of polysilicon, the randomly varying number of implanted ions per unit area, and the edge roughness. Making the devices large minimizes this kind of variation. Finally, the relative orientation among the devices can affect matching. The physical properties of the material and the processing characteristic can depend on direction. Misalignment effects do not

Mismatch Theory

The local random fluctuations and the large gradients of variation have been successfully modeled before [1]-[4]. A derivation of a model exists in [1] for MOS transistors, but the method and the results can be applied to any kind of device. It will be outlined here, in order to investigate how this model could be extended to include deep submicron devices.

The process parameters q , q ,... q are physi1 2 n cal quantities defined by different mechanisms and can usually be considered uncorrelated. In this case the mismatch variance of the device parameter P between the two identically designed devices in distance D depicted in Figure 1, is given by σ

∂f  2 2 ∂f  2 2 2 . σ =  + ...+    σ ∆P ∂ q 1 ∆q 1 ∂ q n ∆q n

(2)

2/4 We now assume that the local random fluctuation part of the value of a process parameter is a wide sense stationary spatial random process with autocorrelation distance much smaller than the device dimensions. The autocorrelation function can be considered an impulse function, and the variance of the difference of the effective values of the process parameter between the two devices is found to be inversely proportional to the area of the devices WL. Assuming that the large gradient part of the variation of the process parameter can be considered linear in the area of the device pair, the difference in its value is proportional to the distance; therefore its variance is proportional to the square of the distance. Combining the above results we obtain 2 S 2 2 2 l, q σ = ----------- + D S g, q , ∆q WL

(3)

2

where S l, q will be called the area coefficient and 2 S g, q the distance coefficient. These parameters are constant for a specific technology. This notation will be used below. Of particular interest is the case at which a device parameter P does not depend on the dimensions, and the process parameters on which it does depend are uncorrelated. Then the partial derivatives of (2) do not depend on W or L and a relation of the form (3), also holds for the device parameter: 2 S 2 2 2 l, P σ = ----------- + D S g, P . ∆P WL

(4)

If the process parameter q is one of the dimensions, for example W, similar analysis in one dimension provides σ

2 S 2 2 2 l, W = ------------- + D S g, W . ∆W L

(5)

Substituting W for L in the above equation gives the variance for ∆L. Applying the above methodology to specific kinds of devices we obtain expressions for their mismatch. For resistors, for instance, we have 2 2 2     σ S S 1  2 ∆R l, W   2 g, W 2 ----------- = --------- S + ------------- + S + ---------------  D . (6) WL  l, R s 2 W   g, R s 2  R W    

Similar expressions can be derived for capacitors, and the threshold voltage, current factor, and body effect coefficient of MOS transistors. In all cases, for relatively large W and L, these expressions have the form of equation (4). If a device parameter is directly or inversely proportional to the device dimensions, such as the resistance, the capacitance, and the MOS transistor current coefficient, relation (6) shows that for small dimen-

1.2

1.2

0.8

I ( W, D ) D = 2W 1 1 ---------------------σ 0.8 D = 1.5W

0.6

0.6

0.4

0.4

0.2

0.2

I(W) 1 -----------σ

D = W

0 0

0.5

Figure 2

1

1.5

2

2.5

3 d x -----W

0

0

0.5

1

1.5

2

2.5

3 d x -----W

(b) (a) (a) I(W), and (b) I1(W,D) of quantity in (8).

sions, the terms proportional to 1/W2 and 1/L2 make mismatch worse than is predicted by equation (4). On the other hand, relaxing the assumption that the autocorrelation distance of the random local variation is much smaller than the device dimensions leads to the result that the part of process parameter mismatch caused by local random fluctuations becomes better than that predicted by the first term of equation (3). The physical interpretation of this is that the devices are so small that the process parameters cannot have large fluctuations within them. In addition, if the distance between the devices is also comparable to the autocorrelation distance, the matching is improved further since the values of the process parameter in the two devices are positively correlated. A two dimesional Gaussian function  2 2 2 x y R ( x, y ) = σ exp –  ------ + ------   2 2 dx dy

,

(7)

is a reasonable substitution for the impulse autocorrelation function. It has been suggested in [3] also, and it leads to tractable analytical calculations. Different autocorrelation distances are used for the x and y directions to preserve generality. The part of mismatch caused by local random fluctuations is then given by 2I ( L ) [ I ( W ) – I ( W, D ) ] 1

(8)

where I(W) and I1(W,D) are depicted in Figure 2. I(L) versus dy/L is similar to I(W) versus dx/W. At this point we do not have sufficient information about the autocorrelation distance of any process parameters, and we are not able to predict if saturation actually appears in the mismatch of the smallest devices that can be fabricated today. Experimental data are needed to support the validity of the model. Although a device parameter is independent of W and L when these dimensions are relatively large, it may depend on them when they are small. A typical example is the threshold voltage of a MOS transistor. In this case dimension mismatch increases the device parameter mismatch. Knowledge of the partial derivatives of the device parameter with respect to the

3/4 dimensions - which will be a function of the dimensions - is needed in order to use (2). The rest of the partial derivatives that appear in (2) could also be functions of the dimensions. For example, in order to predict threshold voltage mismatch behavior of submicron devices, we could introduce into (2) two new terms, one for each dimension, using the slope of the experimentally obtained curves of the threshold voltage versus W and L. The partial derivatives with respect to the rest of the parameters could be arbitrarily assumed independent of the dimensions as a first approximation, and we could use the model for long dimensions to estimate their effect. Experimental mismatch measurements of threshold voltage of submicron devices are needed to verify the result.

(a)

(b) Figure 4

Structures for the mismatch model coefficients (a) Area coefficient, and (b) Distance coefficient.

3.0

Test Structures

We designed a set of test structures in order to quantify the different kinds of variability. They have been fabricated in the UC Berkeley Microfabrication Laboratory on 4-inch wafers. There are 52 die in the wafer and each structure is repeated 3 times in the die. The minimum linewidth allowed by the design rules was 2µm. Four different groups of devices have been designed. The first group aims at investigating the proximity effects. It includes arrays of polysilicon, n and p diffusion resistors, 4x4 two dimensional arrays of NMOS and PMOS transistors, and 5x5 two dimensional arrays of poly1-poly2 capacitors. The necessary number and size of dummy devices are examined. A polysilicon resistor array is shown in Figure 3 (a) and a capacitor array in Figure 3 (b). Dummy capacitors with different sizes have been appended at the edges of the array.

(a)

The second group is devoted to measuring the two coefficients of the mismatch variance model of equation (4). We used structures dedicated to the measurement of each coefficient. Arrays of pairs of small devices with minimum distance between the devices were used for the area coefficient in order to minimize the large gradient variation effect and emphasize the effect of the local variability. For transistors and resistors, one of the two dimensions was kept constant among the pairs. Arrays of large devices in long distances were used for the distance coefficients, to minimize the local variability effect and reveal the large gradient dependence. We designed structures for the measurement of the mismatch model coefficients for polysilicon, n-type, and p-type diffusion resistors, NMOS and PMOS transistors, and poly1-poly2 capacitors. A set of structures for MOS transistors is depicted in Figure 4. The third group is intended to examine the effect of orientation on mismatch. We designed pairs of vertical poly and n-type and p-type diffusion resistors, and NMOS and PMOS transistors. The corresponding pairs with devices of the same size and parallel orientation exist also in the die as part of other structures. Finally, the forth group includes simple subcircuits to examine how device mismatch translates into circuit performance. Four differential pairs with different input and load transistor sizes, and one simple OPAMP have been designed in order to verify that the measured input offset agrees with what circuit analysis predicts when the mismatch variance from the extracted model is used for the transistor pairs.

4.0

Figure 3

(b) (a) Polysilicon resistor array, and (b) Two dimensional capacitor array.

Sample Results

We present here some sample results from our measurements. The profile of the polysilicon array of resistors depicted in Figure 3(a) is shown in Figure 5 (a). Since only the variation within the array is of

Table 2: Model coefficients for resistors.

open area

Type

coef

Value

Units

R2

poly

area

2.53e-2

(µm)2

0.97 0.93 0.41

0

0

0

0

50

100

100

150

100 (Ω)

100 (Ω)

200

4/4

-100

-100

-100

-50

-100

stripe of p-diffusion for substrate bias

(a)

Figure 5

n-diff

(b)

Profile of resistor arrays made of p-diff

(a) polysilicon (average value 6,108Ω), and (b) n-diffusion (average value 3,159Ω).

interest here, the average within the array has been subtracted from the values of the resistors. The superposition of the remaining quantities for all the arrays in the wafer is shown. The black dot represents the median, the rectangle around it shows the upper and lower quartile, and the whiskers include all the data that are not outliers. Figure 5(b) shows the profile of a similar array of diffusion resistors. It is worth noticing that the resistor that is next to the open area exhibits large variance. Figure 6 shows the measurements for the area and distance coefficient for threshold voltage of PMOS transistors from the structures depicted in Figure 4. In Figure 6 (b) the measurements represent variance of mismatch of the pairs formed by the leftmost transistor and each one of the rest of the transistors of Figure 4 (b). Table 1: Model coefficients for PMOS transistors par.

coef

Value (A)

Value (B)

Units

R2 (A)

R2 (B)

VT

area

9.46e-4

1.16e-3

V2(µm)2

0.95

0.93

dist

1.30e-11

9.63e-12

V2(µm)-2

0.97

0.99

β rel.

area

9.33e-3

5.12e-3

(µm)2

0.97

0.96

dist

5.79e-12

6.20e-12

(µm)-2

0.43

0.45

γ

area

2.32e-4

1.68e-4

V(µm)2

0.93

0.94

-2

0.13

0.81

dist

3.13e-13

3.07e-13

V(µm)

Table 1 shows the extracted coefficients for PMOS transistor threshold voltage, current factor, and 2 2 ( mV ) ∆V T

* •

σ

2 2 ( mV ) ∆V T

22 ss2

0.00002

42 ss12

6*10^-6

σ

4*10^-6

0.00003

52

* *

*

* 0 •

0.0

0.10

0.10

width

0.15

0.15 1 1 -----  --------  W  µm 

0

100000

(b) Distance coefficient.

0.56

area

1.60e-3

(µm)2

0.03

dist

3.37e-10

(µm)-2

0.96

Future Work

References [1] M. J. Pelgrom et al, “Matching Properties of MOS Transis[2]

5002 300000

dist2

400000

8002 D2(µm2) 500000

600000

[3]

(b)

Measured std. deviation of Mismatch for (a) Area coefficient, and

(µm)-2

The authors are thankful to Dr. Augustin Ochoa, formerly with ABB HAFO Inc. for many useful suggestions. This work has been supported by ABB HAFO Inc. and the University of California MICRO program.

*

200000

9.69e-11

•

•

0

dist

Acknowledgments

0 0.05

0.05

(a) Figure 6

•

(µm)2

The theory predicts that when the device dimensions become too small there are certain mechanisms that improve matching and others that make it worse. Interesting results can be obtained if the experiment is repeated in a fabrication line capable of creating submicron devices. Actual measurements from devices with one or both of the dimensions very small would further illuminate the mismatch behavior.

0

0.0

•

0

* *

12

•

2.04e-3

The large number of different structures that we designed did not allow a dense grid of each structure on the die. By concentrating our research on one kind of devices we will be able to distribute many identical structures on the die. This will allow, for example, to calculate a set of mismatch model coefficients from each die, and then plot wafer maps of the values of the coefficients. Similarly, we could calculate a set of mismatch model coefficients from all the structures across the wafer located on the same position in the die and plot die maps of the coefficients. Analysis of variance can be used to examine the importance of the effect of the position in the die or in the wafer.

•

2*10^-6

0.00001

22

5.0

•

•

•

1.06e-8

area

body effect coefficient from two sets of structures, A and B. Table 2 presents the extracted coefficients for resistor relative mismatch, ∆R/R.

*

*

* •

*

dist

(µm)-2

[4]

tors”, IEEE JSSC, Vol. 24, No. 5, pp. 1433-1439, Oct. 1989. K. R. Lakshmikumar et al, “Characterization and Modeling of Mismatch in MOS transistors for Precision Analog Design”, IEEE JSSC, Vol. sc-21, No. 6, pp. 1057-1066, Dec. 1986. J. B. Shyu et al, “Random Errors in MOS Capacitors”, IEEE JSSC, Vol. sc-17, No. 6, pp. 1070-1076, Dec. 1982. J. B. Shyu et al, “Random error effects in Matched MOS Capacitors and Current Sources”, IEEE JSSC, Vol. sc-19, No.6, pp. 948-955, Dec. 1984.