Pulse Jitter and Timing Errors in RSFQ Circuits - CiteSeerX

Pulse Jitter and Timing Errors in RSFQ Circuits Alexander V. Rylyakov and Konstantin K. Likharev

Department of Physics and Astronomy, State University of New York, Stony Brook, NY 11794{3800, USA

Abstract| We have carried out measurements of bit error rate (BER) of Rapid Single-Flux-Quantum (RSFQ) XOR gates with various nominal dc power supply voltages (from 0.1 V to 1.0 mV), operating at speeds up to 25 GHz. (For these gates, implemented using HYPRES' standard, 3:5-m; 10 A=m2 Nbtrilayer process, this speed is close to maximum.) A special on-chip RSFQ test circuit allowed ?high-speed measurements of BER in the range from 10 9 to 10?13 to be carried out. As a result of these experiments, a new type of thermal- uctuation-induced digital errors in RSFQ circuits has been identi ed. These \timing" errors arise at high speed due to time jitter of data and clock pulses. We have developed a simple theory of these errors which allows a fair description of the experimental data. The theory shows that in some cases the timing errors may be an important factor limiting speed performance of RSFQ circuitry. Nevertheless, our XOR gates could operate at 25 GHz with BER below 10?13 at the standard temperature (4.2 K) at any dc power supply voltage in our range. For the lowest voltage (0.1 Volt) the calculated static power dissipation in the gate was as low as 23 nanowatts, lower than the unavoidable dynamic dissipation (43 nanowatts). I. Introduction

The problem of uctuation-induced digital errors in RSFQ circuits [1] has been the subject of earlier research. After the initial bit error rate (BER) measurements aimed mostly at demonstrating record numbers [2], [3], more detailed theoretical and experimental studies were undertaken [4]{[8]. As a result, two dierent types of digital errors have been identi ed (see, e.g., Sec. IV of Ref. [6]). First, errors may occur during the passive storage of data in quantizing loops of RSFQ cells, see Fig. 1(a). If the static current I circulating in the loop is close to the critical current IC of a Josephson junction, thermal uctuations can induce a 2 phase ip of the junction phase and thus switch the loop into the neighboring ux state. A theory of such transitions was developed and con rmed in numerous experiments well before the advent of RSFQ { see, e.g., Chapter 3 of Ref. [9]. It is important that the range Is of the dc current dierence (IC ? I ) where these

uctuations are substantial scales as (IC2 IT )1=3 , where the Manuscript received September 16, 1998. A. Rylyakov, 516-632-8060, fax 516-632-8774, sasha@rsfq1. physics.sunysb.edu, http://rsfq1.physics.sunysb.edu/sasha/. The work was supported in part by DoD's University Research Initiative via AFOSR

parameter IT = 2ekB T=h characterizes thermal uctuations [9] (at 4.2 K, IT = 0:17A). For the typical value IC = 200A, Is is close to 1.8 A. We will refer to these events as \storage" errors. (They were sometimes called \static" errors in contrast to the \dynamic" errors which will be described next, but that terminology was confusing, since all uctuation-induced errors are essentially dynamic phenomena.)

Ix

Φ0

(a)

(b)

I x(t)

(c)

Fig. 1. Three situations producing digital errors in RSFQ cells: (a) - storage, (b) - decision, and (c)- races.

Second, switching errors may be produced in another major component of RSFQ circuits, the two-junction comparator (Fig. 1(b)) when an applied SFQ pulse forces one of the junctions to ip, depending on the value of the input current Ix . If this current is close to a threshold value It , there is a nite probability that the wrong junction

ips and a digital error is produced. The scale of the difference (Ix ? It ) where \decision" errors are important scales as Id = (IC IT )1=2 , i.e. is much larger than that of the storage errors (in our example, Id = 14 A). This conclusion has been con rmed by experiments [4]{[6] and Monte-Carlo simulations [7], [8]. The goal of this work has been to show that when an RSFQ circuit operates at high speed, it may exhibit one more type of random error. These errors arise when the transient process Ix (t) induced by the previous SFQ pulse (say, a data signal which is switching Ix to another level) remains un nished by the arrival of another pulse (say, clock) at the comparator, Fig.1(c). Due to thermal noise in previous components of the circuit, the transient waveform Ix (t) uctuates, and as a result, the probability of

ipping the wrong junction is increased. In some cases (though not always!), the rate of such errors may be simply expressed via r.m.s. jitter t of the time interval between data and clock pulses arriving at the interferometer. This is why we will refer to them as \timing" errors.

DC/SFQ

AIN

stage 4 ain

SIG comparator

clkin

1

T 19

BOUT SFQ/DC

CLKIN

Q4

stage 1

stage 2 D3

XOR 3

D 3

SFQ/DC

D 4

CLKIN_X CLK

stage 3 D4

XOR 4

SFQ/DC

SFQ/DC

DC/SFQ

T

clkgen

D 5

D2 XOR 1

D 2

Q3

stage 0 D1

XOR 2

D 1

D0

SFQ/DC

AIN_X

SFQ/DC

SFQ/DC

SFQ/DC

SFQ/DC

A1

Q2

Q1

CLK2

Fig. 3. Block diagram of the experiment. 1/f V

1/f max R1 LXA

R2 LXB

JXA2

A

CLOCK JXB2

JXA1

JXB1

DATA

JXO2

CLOCK

τ

B

LXO

JXC

JXO1

XOR

Fig. 2. Equivalent circuit of the XOR cell. Nominal parameter values are as follows: dc bias currents (A): V=R1 = 140, V=R2 = 85; critical currents (A): JXA1 = JXB1 = 162, JXA2 = 187, JXB2 = 174, JXC = JXO1 = 276; inductances (pH ): LXA = 3:3, LXB = 4:1, LXO = 1:4.

II. Design of the Experiment

In this experiment we have studied rare errors of a XOR RSFQ gate (Fig. 2) which was rst proposed in [1]. This gate was studied experimentally at low frequency [10], and then used as a key component of a digital autocorrelator design [11]. The gate operates as follows: if a data pulse arrives at input A, it induces a 2 phase leap in junction JXA1 (\switches" it), i.e. inserts a ux quantum into the left quantizing loop JXA1-JXA2-LXA-LXO-JXO2-JXO1. The operation of input B, controlling the right quantizing loop, is similar. When there are no input pulses, both quantizing loops are empty and the persistent current through junction JX01 is low, the following clock pulse \CLOCK" switches junction JXC, and there is no output pulse across the junction JXO1 (operation 0  0 = 0). If only one data pulse has arrived, the persistent current through JX01 is high, and the clock switches JX01, providing an output SFQ pulse across it (operation 10 = 1). The slowest operation of the gate is 1  1 = 0. It is performed when single ux quanta have been inserted into both quantizing loops. In this case the total current through junction JXO2 exceeds its critical value and the

Fig. 4. Timing of the XOR cell.

junction is switched, clearing both loops. This process starts as soon as both A and B are in, and has to be completed before the arrival of the clock signal. In the case of correct operation, when the clock pulse arrives, it nds the gate in the same state as in the case of zero inputs, with low current in JX01. In this case, again, the clock switches JXC and no output pulse is developed across JX01. This is exactly the operation which is most prone to timing errors. Figure 3 shows a block diagram of the on-chip, highspeed test circuit. It is based on a modi ed version of the autocorrelator delay line [11]. Its main feature is the 4+1stage circular shift register with input signal \ain" going through 10 D ip- ops D5 ; D4 :::D?4 . The ip- ops were clocked by the \clkin" signal. Four XOR gates under test, each having a separate dc power supply line, have been built into every stage of the shift register. XORs 4, 3, 2 and 1 had nominal dc bias voltages of V0 = 1; 0:5; 0:2 and 0:1 mV , respectively; their dc bias resistors were scaled accordingly to supply similar dc bias currents to each gate. The system provides the following sequence of events in each XOR every clock cycle: the clock pulse arriving from the previous stage (say, stage 4) resets the XOR gate (XOR3 in our example) and the resulting pulse, if any, is read out into the output SFQ-DC converter (\Q3"). The same clock pulse also triggers the readout from the upper D ip- op of the same shift register stage (D4 ) into the upper input of the XOR, and from the lower D ip- op of the next stage (D?2 ) to the lower input of the XOR. Both input signals enter the gate virtually simultaneously.

p = N Nerrors

clock periods

= NNerrors
f
1
t ; tries

(1)

−9.5

10 GHz 15 GHz 20 GHz 22 GHz 25 GHz

−10.5 −11.5 −12.5

1 mV

−13.5 0.5 Bit error rate

The delay  of these data pulses relative to the clock is independent of the clock frequency (Fig. 4) and nominally equal to 20 ps. The rest of the hardware shown in Fig. 3 was used for low- and high-frequency testing of the circuit. The experimental procedure was as follows. First, the fabricated circuit was tested at low frequencies, with XOR gates supplied with all possible input pulse combinations, and the parameter window (in the space of individual XOR gates supply voltages) where all the gates operated correctly was determined { see the vertical lines in Fig. 5. Then a dc current \CLK" was applied to the high-speed on-chip generator \clkgen" built around an overdamped Josephson junction (IC = 0:2 mA; RN = 0:08 ). The waveform generated by the junction was then shaped into separate SFQ pulses, and their frequency was divided by four. The speed of the resulting clock could be varied from approximately 30 MHz to 30 GHz, and monitored via the dc voltage across the generator junction. ( In addition, an array of 20 T ip- op cells was used to divide the6 frequency of the clock signals by a factor of 220  = 10 and to monitor the clock frequency digitally in the kHz range). Theoretically estimated jitter at the clock output was below 0:1 ps (much larger uctuations could be accumulated in the JTLs leading from the generator to XOR, see Sec. III below). Next, the input comparator was biased (with dc current \SIG") at approximately 350 A, well above the comparator threshold, so that the complete continuous clock pulse train was passed to the delay line input (\ain" = \clkin" in Fig. 3), ensuring that each XOR is fed by two input pulses each clock cycle (operation 1  1 = 0). When each XOR gate was biased into the middle of its window at any clock frequency below 25 GHz no output signals were observed from the output monitors \Q1"...\Q4". This could be expected, because according to our analysis (see below), BER in this case should be well below the level of 10?15 which we could register during a typical experimental run. However, if either the clock frequency was increased, or one of the XOR gates was moved closer to the edge of its operating region, the output monitor of this particular gate could register random switching events, indicating a measurable error rate. Using the built-in Lisp interpreter of our Octopux setup [12] we wrote a simple program which measured the initial states of all four XOR monitors, and then waited for a xed period of time
t (typically, from 30 to 300 ms). Following that, Octopux compared new states of the monitors to the old ones. This procedure was repeated many (typically, from 103 to 104 ) times. The waiting period
t and the number of repetitions Ntries were chosen so that, on one hand, the total number of observed errors Nerrors was large p enough to reduce suciently its relative variance (1= N errors  1) and, on the other hand, small enough to be sure that the probability of any monitor switching twice within the same waiting period was negligible (Nerrors  Ntries ). The bit error rate of the comparator is then determined from the evident formula

1.0

1.5

2.0

2.5

1.0

1.5

2.0

2.5

1.0

1.5

2.0

2.5

1.0

1.5 Normalized bias voltage

2.0

2.5

−9.5 −10.5 −11.5 −12.5

0.5 mV

−13.5 0.5 −9.5 −10.5 −11.5 −12.5

0.2 mV

−13.5 0.5 −9.5 −10.5 −11.5 −12.5 −13.5 0.5

0.1 mV

Fig. 5. Semi-log plot of the bit error rate (in powers of 10) versus bias voltage (normalized to the nominal value) for 11 = 0 operation, for several values of the clock frequency and nominal dc power supply voltage. Vertical lines show the low-frequency-measured boundaries of the correct operation region: solid lines for the 1  1 operation, while dashed lines for the complete testing sequence.

where f is the clock speed. We estimate the overall accuracy of such measurements at better than 10% (for p ranging from 10?9 to 10?13). In view of the very rapid (exponential) dependence of p on parameters (see Fig. 5), this accuracy was sucient for our purposes. III. Experimental results and comparison with theory

Figure 5 shows the results of a typical high-speed error-rate experiment (design \USB 297", HYPRES wafer \w2842g"). It shows very clearly that the BER behavior near the upper and lower margin is very dierent. The position and slope of the upper margin is virtually independent of frequency for all 4 XORs. The interpretation of this fact is simple: when the gate is close to the upper margin, the current Ix through inductance LXO is high and the Josephson phase of junction JXO2 moves very fast when performing the 1  1 = 0 operation. So, when the clock pulse arrives it hits a reliably empty cell. On the other hand, the current Ix also controls the comparator JXC-JXO1 and its high value brings us closer to the threshold, and this proximity is responsible for the rare errors we see. In order to prove that, we have carried out a similar set of high-speed experiments for the 0  0 operation (when dc current \SIG" is low and there are no

@ ln1=2 (1=p)=@ = @ (Ipx ? It )=@  13: (3) 2
Ix The measured values of the slope @ ln1=2 (1=p)=@ at the

upper margin were 11  2 for all values of nominal dc supply voltage and all clock speeds within our range, indicating a very comfortable agreement with theory. The positions and slopes of the lower dc bias margins have been found to be, on the contrary, quite sensitive to the clock speed (Fig. 5). A picture of the processes occurring in an underbiased XOR, suggested by computer simulation, is as follows: when the Josephson phase  of the junction JXO2 (Fig. 2) passes over the maximum of the washboard potential energy pro le (  =2 [9]), at low bias it moves so slowly that the switching is not completely nished before the clock pulse arrives. Thermal

uctuations provide the uncertainty (jitter) of the junction switching time and thus induce timing errors even below the maximum deterministic value fmax of clock frequency. Let us see what timing error rate should result from these uctuations. Let us assume that the uctuations lead only to the time jitter of the current Ix (t); rather than to a the cardinal change of its waveform, and that the usual Gaussian statistics is applicable. In this case the probability of the current exceeding the threshold value It by the time t of the clock pulse arrival is described by the p error function of the argument (t ? tmin )=( 2
t), where t is the r.m.s. jitter, and tmin is the deterministic time threshold de ned by the equation Ix (tmin ) = It in the absence of uctuations. Since t ? tmin = 1=f ? 1=fmax (Fig. 4), using the same asymptotic behavior of the error function as above, we get the following expression for timing BER (valid at p  1):

ln1=2 (1=p) = 1=fp? 1=fmax : 2
t

(4)

8

7

1/2

6

5

( ln(1/p) )

\ain" inputs, see Fig. 3). Both the position and slopes of the upper margin in this case were found to be very similar to the 1  1 case, thus con rming our hypothesis. Therefore, we may expect that the upper dc margin BER curve should be well described by the theory of comparator decision errors [4], [6]. According to this theory, BER should obey the usual Gaussian distribution p = 21
[1 ? erf ( pIx ? It )]; (2) 2
Ix where Ix ? It is the deviation of current Ix from its threshold value It , while Ix is the r.m.s. width of the switching ?1 gray area. (Note that parameter p
Ix  (dp=dIx ) jp=0:5 used in Refs. [4], [6] equals 2
Ix .) Taking into account the observed 30% surplus of the critical current density over the nominal value in this particular sample, we may use Eq. (6) of Ref. [6] to estimate the thermal uctuation-determined gray area width as Ix = 3:3A. In our circuit, the dierence Ix ? It is linearly proportional to the variation of the normalized dc bias voltage @  @V=V0 . From PSCAN simulations we have found that @ (Ix ? It )=@ = 62:5A. Now, using the well-known asymptotic behavior of the error function at p  1, we get

4 1.1 1.3

3

1.4 2

1

0

30

40

50

60

70

1/f, ps

Fig. 6. ln1=2 (1=p) versus 1=f for a V0 = 1 mV XOR cell at 4 dierent values of the normalized dc bias voltage V=V0 . Points show the data, while the lines are the best t according to Eq.(4)

Linear t of the data (in accordance with Eq. (4) ) results in the same value of fmax = 28 GHz in a considerable range of the ratio V=V0 , while the tting values of t are substantially dierent within this range (Fig. 6). For example, at V0 = 1 mV , t equals 3:3  0:3; 1:5  0:2 and 1:4  0:2 ps for   V=V0 = 1:1; 1:3 and 1:4; respectively; fmax falls while t grows close to the lower margin. The tting value of fmax agrees well with results of PSCAN simulation. The tting values of t are also quite reasonable. Indeed, let us start with a very crude estimate. Near the minimum slope of the washboard potential U = (h=2e)(?Ic cos  ? I (t)) the eective spring constant k = (1=2)@ 2U=@2 is low [9]. This means that

uctuations of the Josephson phase  obey the simple diusion equation. As a result, the r.m.s. jitter of the switching time may be estimated from Einstein's diusion formula p

 t = _ 2 t : max

(5)

Here  IT =IC  10?3 is the relative intensity of thermal uctuations, t is the average switching time and _ max is phase velocity of the junction at the peak of the SFQ pulse. In Eq. (5), time is measured in the standard normalized units of !c?1  0 =2Ic R [9] used in PSCAN and other2 RSFQ simulation tools; for the HYPRES' 10 A=m technology this unit is very close to 1 ps. For example, at 20 GHz operation with  = 0:745, PSCAN simulations give t = 14 and _ max = 0:3. From Eq. (5) we arrive at the estimate t = 0:6 ps. This is in the same ballpark as the experimental value, but still not very close to it. A more realistic estimate of t can be obtained from the linearized equations of motion for the Josephson phase in the presence of thermal uctuations. Let (t) be the deterministic trajectory of the phase and (t) its small uctuation due to the uctuation current source

IC  (t). Then, for a strongly overdamped Josephson junction ( c = 0), we have the following linear dierential equation for (t) (in the same normalized units as above): _ + [cos((t)) + ext ] =  (t) : (6) Here ext = (2Leff Ic =0 )?1 , where Leff is the eective shunting inductance due to the circuit environment of the switching junction. (This environment includes the neighboring Josephson junctions; since they are not being switched at the same instant as the junction under consideration, the approximation of constant ext seems quite reasonable.) The correlation function of the thermal

uctuations is given by [9]:

h (t) (t0 )i = 2 (t ? t0 ):

(7)

Combining Eqs. (6) and (7) we get the following expression for the phase uctuation variance:

h2 (t)i = 2

Z t

?1

dt0 expf?2

Zt

t

0

d [cos(( )) + ext ]g: (8)

The environmental inductance ext may be found using a uctuation-free simulator (e.g., PSCAN) by injection of a small current @I into the junction under question and measuring the resulting small phase dierence @ across it, in the stationary state of the circuit ( = 0 ). From this simulation, ext may be found as @ (I=Ic )=@ ? cos(0 ), since the external inductance does not depend much on whether this particular junction is being switched or not. Using this method, for our case of 20 GHz operation at  = 1:0 we have found ext = 0:21 p and t  h2 (t)i=_ max = 2:1 ps (cf. the experimental value of 1.4 ps). This is quite a reasonable agreement, taking into account that in our experiment the junctions were critically damped ( c = 1), rather than overdamped ( c  1) as in the simple theory behind Eq. (8). In fact, the shorter transient tail (i.e., a narrower frequency bandwidth) of a critically damped junction should suppress jitter to some extent. Some contribution to the observed jitter could arise from thermal uctuations in junctions of the D ip- ops and JTLs of the shift register. Our estimates (using the theory outlined in the next section) give 0:6 ps for the r.m.s. of this jitter. Since2 for independent jitter sources their variances  = (t) (rather than r.m.s. values t) add, that contribution does not aect our results substantially. Notice that the reduction of the nominal dc power supply voltage V0 gradually increases the rate of timing errors (Fig. 5). This behavior can be understood as follows: as the clock frequency grows, the average voltage hV i across the cell grows proportionally (2:07V=GHz), so that dc current decreases proportionally to V0 ? hV i. This is equivalent to moving towards the lower margin. Nevertheless, even the cell with the lowest V0 (and hence the lowest static power consumption in the bias resistors), could operate with BER well below 10?13 at frequency as high as 25 GHz, i.e. quite close to the estimated fmax = 28 GHz. By the way, the static power dissipation of the gate, calculated from PSCAN using experimental parameters, was as

100

100

10

10

t, δt

t, δ t

1

0.1

0.01 0.0

1

0.1

0.2

0.4

I/Ic

(a)

0.6

0.8

1.0

0.01 1.0

1.2

1.4

I/Ic

1.6

1.8

2.0

(b)

Fig. 7. Average switching time delay t (solid lines) and switching time jitter t (dashed lines) as calculated for two basic RSFQ components: (a) a balanced comparator dc biased with current I and switched by a sharp phase step (t) = 2(t), and (b) a single junction pre-biased with dc current I0 and switched with an additional sharp current step
I = (I ? I0 )(t). (Three curves in (b) correspond to I0 =IC = 0:1; 0:7 and 0:9, time is measured in the units of !c?1 , = 10?3 .)

low as 23 nanowatts. This is even lower than the unavoidable dynamic power consumption in switching Josephson junctions (43 nanowatts at 25 GHz). IV. General Analysis

In order to get a better understanding of the importance of timing errors of RSFQ circuits, we have used Eq. (8) to carry out the analytical calculation of jitter for simple models of two major components of these circuits: (a) a single, current-switched Josephson junction, and (b) a phase-switched comparator (cf. Fig. 1). In both cases, we have assumed that the external signals change instantly (on the scale of !c?1 ). Figure 7 shows the results of this calculation for a typical critical current IC = 170A 3at the standard operation temperature T = 4:2K ( = 10 ). In the case of a single junction, the results are only weakly dependent on the initial value I0 of the current. The dependence on the switching current \overdrive" (I ? IC ) is much stronger. For a relatively high overdrive, I = 1:5IC (typical for Josephson junction transmission lines) the switching time delay t is close to 3!c?1, while in typical RSFQ gates the eective (average) value of I is closer to 1:2IC , and the switching time to 8!c?1. The r.m.s. jitter t of the switching time for these cases is close to 0:06!c?1, and 0:4!c?1, respectively. In a phase-driven comparator, both t and t are lower unless I is very low; one should not forget, however, that their implementation requires a high-IC driver [4] which would introduce its own delay and jitter, similar to those calculated for a single junction. Now let us compare the timing errors due to pulse jitter and decision errors (as stated above, storage errors are typically much smaller). This can be readily done for a comparator with a relatively low value of the measured current I (strictly speaking, for I  IC , though the result

Parameter value storage errors N

(a)

(b) decision errors

timing errors

1/f max

Clock period

Fig. 8. Parameter window of correct operation of (a) a single RSFQ gate and (b) an RSFQ circuit with N switching junctions in the critical timing loop (schematically). Solid lines: noiseless parameter margins; dashed lines: low-BER boundaries in the presence of thermal noise.

should be valid with reasonable accuracy while I < 0:5IC ; i.e. in all the practically interesting range). In this case, the theory developed by T. Filippov (see, e.g., Ref. [4]) gives the Gauss-distributed decision error probability with the following r.m.s. value: (I )2 = 2IT IC = 2Id2 : (9) From this and Fig. 7 we see that I=IC  t=t: This means that at moderate clock frequency (of the order of, but not too close to fmax) the timing and decision errors are comparable { see Fig. 8. In this case the timing errors may be considered not as a separate eect, but as frequency-dependent decision errors. The situation is dierent, and timing errors are of crucial importance, in two cases: 1. A gate has not been optimized for speed, and at least one of its junctions is switched rather slowly (the eective overdrive I ? I0 is small). Junction JX02 in our XOR gate is a good example, making this cell not very suitable for high-frequency applications (though very convenient for our experiments). 2. An RSFQ circuit has long timing loops, where the time jitter accumulates in N  1psequentially switched junctions. In this case t grows as N; and timing errors may dominate in a broad range of clock frequencies { see the dotted line (b) in Fig. 8. V. Discussion

We believe that our experiments with XOR gates gave a convincing evidence that our general concept of timing errors is correct. Encouraged by this new understanding, our group has carried out preliminary estimates of these errors in other RSFQ circuits, including Josephson transmission lines, some clocked gates (\elementary cells"), and whole functional units such as bit-parallel integer adders with Kogge-Stone carry-lookahead architecture [13], [14]. These preliminary results show that for the standard LTS RSFQ circuit parameters, the timing errors are not

too damaging. In simple circuits such as ip- ops, where all the switching events occur in comparators, timing errors may be considered as an increase of the decision errors very close to the deterministic maximum frequency (Fig. 8), so that the practical speed reduction is small. On the contrary, in RSFQ circuits with long timing loops with a large number of sequentially switched junctions (e.g., large segments of Josephson transmission lines), SFQ pulse jitter and the resulting timing errors may be a serious factor limiting the speed performance. These loops may be reduced considerably with an appropriate timing scheme choice [13], [14]. Nevertheless, the calculation or at least an estimate of the timing error rate, including the eects of the random spread of circuit parameters, should become a part of any serious RSFQ circuit design. Acknowledgments

We would like to thank P. Bunyk, T. Filippov, P. Litskevitch, S. Polonsky and V. Semenov for numerous stimulating discussions, A. Kirichenko, P. Shevchenko and D. Zinoviev for software support, and Yu. Polyakov for help with experiments. References [1] K. Likharev and V. Semenov, \RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz clockfrequency digital systems," IEEE Trans. Appl. Supercond., vol. 1, pp. 3{28, March 1991. [2] S. Polonsky et al., \New RSFQ circuits," IEEE Trans. Appl. Supercond., vol. 3, pp. 2566{2577, March 1993. [3] Q. Herr and M. Feldman, \Error rate of a superconducting circuit," Appl. Phys. Lett., vol. 69, pp. 694{695, July 1996. [4] T. Filippov, V. Semenov, and K. Likharev, \Signal resolution of RSFQ comparators," IEEE Trans. Applied Superconductivity, vol. 5, pp. 2240{2243, March 1995. [5] B. Oelze, B. Ruck, M. Roth, R. Doemel, M. Siegel, A. Y. Kidiyarova-Shevchenko, T. V. Filippov, M. Y. Kupriyanov, G. Hildebrandt, H. Toepfer, F. H. Uhlmann, and W. Prusseit, \Rapid single- ux-quantum balanced comparator based on high-Tc bicrystal junctions," Appl. Phys. Lett., vol. 68, pp. 2732{2734, May 1996. [6] V. Semenov, T. Filippov, Y. Polyakov, and K. Likharev, \SFQ balanced comparators at a nite sampling rate," IEEE Trans. Applied Superconductivity, vol. 7, pp. 3617{3620, June 1997. [7] J. Satchel, \Stochastic simulation of SFQ logic," IEEE Trans. Applied Superconductivity, vol. 7, pp. 3315{3318, June 1997. [8] M. Jerey, P. Y. Xie, S. R. Whiteley, and T. V. Duzer, \Monte Carlo and thermal noise analysis of ultra-high-speed high temperature superconductor digital circuits." This conference. [9] K. Likharev, Dynamics of Josephson Junctions and Circuits. New York: Gordon & Breach, 1986. [10] S. Polonsky, J. Lin, and A. Rylyakov, \RSFQ arithmetic blocks for DSP applications," IEEE Trans. Appl. Supercond., vol. 5, pp. 2823{26, June 1995. [11] A. Rylyakov, D. Likharev, and Y. Polyakov, \A fully integrated 16-channel RSFQ autocorrelator operating at 11 GHz." This conference, report EKB-04. [12] D. Zinoviev and Y. Polyakov, \Octopux: An advanced automated setup for testing superconductor circuits," IEEE Trans. Appl. Supercond., vol. 7, pp. 3240{3243, June 1997. [13] P. Bunyk and P. Litskevitch, \Case study in RSFQ design: Fast pipelined 32-bit adder." This conference, report ELC-03. [14] Y. Kameda, S. Polonsky, N. Maezawa, and T. Nanya, \Selftimed parallel adders based on DI RSFQ primitives." This conference, report EOD-04.