Rapid single flux quantum random access memory - IEEE Xplore

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY,VOL. 5 , NO. 2, J U N E 1995

Rapid Single Flux Quantum Random Access Memory S.V. Polonsky, A. F. Kirichenko, V. K. Semenov, andK. K. Likhafev, State University of New York,Stony Brook, NY 11794-3800.

Absjracf -A new design concept for the Josephson-j~ction random access memory (RAM) has been developed. In contrast to PmOuS RABb based 011 Sin%e flux quanhaon in Our System READ and operations employ ballistic transfer of SFQ pulses along bit untr (either Josephson transmission lines, or passive supercondudog microstrip line, or their combination). The basic memory alls are the s i n g l e junction $QUIDS, connected serially by the bit lines and inductively coupled to word Unes. READ and WRlTE operations are performed by sending SFQ palses in appropriate directions along bit lines, and dc " e n t a of appropriate polarity into word lines. This approach allows design of very dense memories with I& Josephson jUnetions per bit, memory cell area smaller than SOX2 (where X is the minimum feature size), and the critical parameter ma* well above 390%. In this paper we present the general s t r u e t p r e of the RSFQ RAM, as well as design and results of testing of the basic memo cell and decoder circuitry wing Hypres' 3.5-pm, I-kA/cm'NbMiryer technology.

n.RSFQMEMoRYCoNCEPT Figure 1 shows the conceptual structure ofthe suggested RAM. The memory cells are the single-Josephson-junction SQUIDS; each of them can store a bit of data in the form of presendabsence of a single quantum of magnetic flux trapped in the SQUID. The idea to use this amplest quantum interference device as a memory cell was proposed long ago [16].The main problem with this idea was that the change of the flux state of the SQUID does not result in any dc signal of finite power, but only in the appeamnce of a very short (picosecond) SFQ voltage pulse V(t)with the quantized area IV(0dt = O0= W2e 2 mV-ps. (1) Until the advent of the RSFQ concept [17]it was not clear how these pulses might be picked up and p r d In RSFQ circuits, the SFQ pulses are the only carriers of digital bits, and may be readily used for reading the information from (and writing information to) the singlejunctionSQUID cells. In our present design, the cells are galvanically connected in series by bit lines (horizontal lines in Fig. 1) and are inductively coupled to word lines (vertical lines). The loop shaped bit lines may be implemented as either the Josephson transmission lines (JIZ), or passive superconductor microstrip lines (SML), or a combination of the above. Word lines are SMLs terminated by the impedance matching resistors. An SFQ voltage pulse propagating along the bit line does not change the state of the cells which are not properly biased by the dc current flowing along the corresponding word line. The pulse traveling in the WRITE direction (Fig. 1) is trapped by a memory cell biased ("selected") by the word current of a certain polarity, thus implementing WRITE operation. On the other hand, when such a pulse is transmitted in the READ direction through a memory cell biased by the word current of the opposite polarity, it annihilates with the flux quantum stored in this cell. If the cell was empty (no flux quantum stored), the pulse propagates through the cell and arrives to the output D of the RAM. Thus presendabsence of an SFQ pulse at this output represents the state of the memory cell, implementing the destructive READ operation.

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I. INTRODUCTION During the past few years there has been a surge of interest in ultrafast digital Josephson junction devices based on the RSFQ logidmemory family (see, e.g., the review [l]and the reoent works [2-71).For many prospective RSFQ systems, in particular general-purpose microprocessors [8], a fist and dense random access memory (RAM) is a must. A number of superconductor memory concepts have been developed over the last two decades see, e.g., Refs. 9, 10 and references therein. Some of these memories have been implemented experimentally, and exhibited high speed performance (subnanosecond cycle periods [lo]). These memories store digital bits in the form of single quanta of magnetic flux (SFQ), i.e. exactly in the same form as the RSFQ circuits do. However, transfer of information in the memories was performed in the form of dc voltage, rather than in the SFQ form. This approach has several drawbacks, most importantly a relatively low density of the memories: in order to convert the SFQ representation to dc voltage representation, each memory cell typically needs at least 4 Josephson junctions and a tfansformer. As a result, the area of even the most advanced memory cells developed using this approach is as large as 200 lithographic squares [191. The objective of this paper is to introduce a novel superconductor SFQ RAM, which uses single flux quanta both for storage and retrieval of data, has only 2 (or, as an option, even less) Josephson junctions per cell, and thus

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allows very dense designs. We will describe the basic conof the memory, and present results of experimental testing of its main a m p " n t s : the basic memory cell and a maincellofthewr(-t&).

1051-8223/95$04.00 0 1995 IEEE

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IMPEDANCE U A T F U N R

Selection of the bit and word lines for R E A D ” E operation is performed by address SFQ pulses arriving at the input bus ADDR These pulses control the state of SFQDC converters (“drivers”) loaded with passive transmission lines. The lines are inductively coupled to singlebit cells (“switches”)ofthe bit and word deooders, +vely. Each line ofthe decoders is composed ofa unique combination of RSFQ switches SO and S1. Switch SO passes SFQ pulses only if there is no current in the cmesponding control line (i.e. if the corresponding address bit is set to ”0”). On the other hand, switch S1 transmits SFQ pulses only if the control current is finite (the address bit is set to “1”). For any address there is only one line in the decoder, capable of passing the SFQ pulses that arrive at the bit (wrd) decoder from the inputs BS (WS). Selection between READ and WRlTE is performed by an SFQ pulse arrivingat the input Ww. This pulse controls the state of an SFQ/DC converter (‘WW driver”). The driver, firstly, controls the bit line demultiplexors (”R/W DEMUX“) which direct pulse BS into selected bit line. It also controls the word line curtent drivers and thus the polarity of the current in word lines. During the WRlTE cycle, the pulse BS is injected into the upper wire of the selected bit line. Passing along the loop shaped line, it reaches the wrd-selected m e m q cell and is

absorbed in it (simultane~~~ly changing its state). During the READ cycle, the SFQ pulp is injected into the lower wire of the line. Passing around the loop, it is either absorbed in the mard-selected memory cell (READ “l”),or transmitted to the other end of the loop line, chauneled into the general output line D and passed to the memory chip output (READ

T? One can see that in addition to the potentially high density, the memory has an importqnt advantage to be inputloutput compatiile with the RSFQ l a c circuits. Its potential drawbackisthedestructivetypeofreadout.

m.MEIvIORYCELL A. Operation

Figure 2 shows the equivalent circuit of the basic memory cell. It consists of a segment of the Josephson transmission line (iunction n,inductance LT, current bias Ib) and a singlejunction SQUID (iunction JM,inductance LM). The SQUID is inductively wupled to the word line (inductance LC).

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Fig 2. Eqwvalent cirait ofthe menmy cell.f s i p den& (anditimal) Fig 3. Miuqhdograph of a part of the experimantal circuit, &owing 3 positive polarity of the Joseph phase d r q s &QDSS juudim. O p t h i z d menory cells siaing mthe same bit line. parametezs: JhI=n=0.25 mA, m . 1 6 mA, LM=8.5 pH, LTd.6 pH, A M 4 . 5 FO.

In a stationary case (no SFQ pulses around) the cell may be in one of two possible flux states (binary "0" or "1"). They differ by the direction of the persistent current Ip=@d2-LM, circulating in the SQUID loop. In the state "0" the current flows counterclockwise, creating an additional (In Fig. 2, positive) phase drop (about d4) across the Josephson junction JM. If the cell is not selected, the WRITEREAD SFQ pulses propagate along the bit line without a€Fecting the state of SQUIDS. In order to increase operating margins of the circuit, we additionally "unselect" such cells by passing the word line current IW in such direction that it prevents JM from switching (IWN if the SFQ pulses propagate in the READ direction, and IWo 1->1 0->o 1->o 0->o

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A3 Fig 5. Equivalent chwas of witdm SO md S1. Parametas f a SO (SI) are: M . 2 4 (0.3) mA, JS14.24 (0.22) mA, JS2=0.24 (0.37) mA, n 9 . 1 9 (0.24) Fig 4. h - h q u m c y logic tedng ofthe menay cell, carrespmding to the mA, l T 4 . 1 5 (0.2) mA, I s o . 2 5 (0.25) mA, LT14.74 (0.74) pH, LT2=3.1 o p d m mode sequence 5-7-8-241 Vable 1). sigpal W (R) is m input d (4.0)pH,Ls1=1.3 (0.9)pH,Ls2=1.4 (1.26)pH,M=l.O (0.76)pH. WRlTEi (READ) DClSFQ The raisingedge afthe sispal carrespmds to smding m SFQ pulse mto the bit line. sigpals Al, A2, A3 the The equivalent circuit of switch S1 is the same as that of currmts mthe ward lines ofthe cmqmding cells (Fig 3). sigpal W M (RM) ism outputhmSFQlDCma&aiugthe (READ) end ofthe bit line. SO, but its parameters are chosen to satisfy the opposite relations : Any edge ofthis si& curqmdsto detedian ofmSFQpulse. 0.0

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B. Testing We have successfullyverilkd the operation of memory cell (Fig. 4) using program Octopus [12] for automated As a result, SFQ pulses can propagate through S1 only measurements. Experimental margins for dc bias voltage when address bit is "1". We have simulated and optimized SO and S1 cells. For were about i20??, in good agreement with computet simulation results. both cells the margins on dc supply voltage are about f35%. The SFQ pulse propagation delay is approximately 10 ps per Iv. DECODER cell. To verify the operation of SO, S1 cells experimentally, we A. @eration have designed a 16 bit decoder shown in Fig. 6-7. It has an input terminal (corresponding to either BS or WS in Fig. l), The RSFQ switch SO (Fig. 5) consists of a hejunction four address lines AO-A3, and sixteen outputs 00-015. The SQUID (junctions JS1 and JS2, inductances LSl and LS2, area of decoder is 1.5x0.3 nun2. At the nominal operating current bias IS), buffer junction JB, and the transmission point (2.6 mv) it dissipates power of 0.07 mW. junction JT, which is used to match the cell with its (similar) neighbors (Fig. 1). The SQUID is inductively coupled to the control inductance Lc. The absence of current ICthrough this inductance corresponds to address bit "O", while a positive current ICcorresponds to address "1". The parameters ofthe SQUID are chosen such that its effective critical current Je satisfiesthe following relations:

The circuit operation is very similar to that of the memory cell. If the address is "O", an SFQ pulse arriving at the transmissionjunction JT propagates through junction JS1 to the output terminal. If the address bit is "la,then this pulse switches the M e r junction JB,so that no SFQ pulse arrives Fig 6. Miamphdogaph d a f i q m a t ofthe 1:16 decoderwith .witdmSO md at the circuit output. s1.

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B. Testing

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v. CONCLUSIONAND DISCUSSION.

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Fig 8. Law-fkqmcy cpexdm of 1:16 demder m q m d i n g tothe addres sequence oooO,OOO1, .... 1111. The raising edge ofthe signal DATA trigga DC/SFQ convater, sending an SFQ pulse mto the decoder. Signals AO-A3 drive address lines ofthe decoder.Any edge of signals014l15 m q m d s to an SFQ pulse d&&d by SFQ m d m [2], cumeded to the cuts of the

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We have performed low-frequency testing of this circuit. All outputs of decoder except one (i.e. 15 of 16) have been found to operate correctly (Fig. 7) within f20% margin of the dc supply voltage. The possible reason of failure of one output is a microshort in its SFQ/DC converter (rather than in the switches).

We have introduced the concept of RSFQ random access memory which uses single flux quanta both for data storage and retrieval. The basic building blocks of this system (the memory cell and decoder) have been designed, optimized, and tested. Our immediate future plans are to design and test a complete 1 Kb RsFQ RAM. The performance of our RAM can be drastically increased if an advanced fabrication process with high-j, Josephson junctions could be used for its implementation. For example, 0.5x0.5 p2 and critical Josephson junctions with area current density 100 W c m 2(see the preliminary experiments [15]) would not require external shunt resistors, which consume a considerable fraction of the memory cell area [ 141. Using the set of parameters presented in Section 111, the area of such a memory cell can be estimated as 5x5 $. Thus the area of 1 Mbit memory cell array would be of the order of 5x5 mm2 while the power dissipation could be well below 1 W. The READNRITE SFQ pulse propagation delay would be about ps per memory cell. Neglecting possible time

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overhead in decoders and vmrd line drivers, viw can crudely estimate the access time of such a 1Mb memory 88 1 ns.

The authors d d like to thank D.P. Schneider and Yu.k Polyakov for experimental support, and P.N.Shevchenko for software suppart.

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