Melissa Smith, Clemson University, USA. Hayden So, University of Hong Kong, China. Neil Steiner, University of Southern California ISI, USA. Christof Teuscher ...
2013 IEEE 27th International Symposium on Parallel & Distributed Processing Workshops and PhD Forum
Reconfigurable Architectures Workshop (RAW) This book presents the proceedings of the 20th Reconfigurable Architectures Workshop (RAW 2013) held in Boston, USA, on May 20-21, 2013. RAW 2013 is associated with the 27th Annual International Parallel & Distributed Processing Symposium (IPDPS 2013) and is sponsored by the IEEE Computer Society's Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and ongoing research on both theoretical and practical advances in Reconfigurable Computing. In the last few years, we have seen a steady growth in exciting developments and applications in the field of Reconfigurable Computing. Many of these new developments are reported in these proceedings, in topics that include algorithms, architectures, tools, systems and applications. The technical program committee, which includes experts from the academia and industry around the world, has put together an excellent and stimulating program. The papers presented in these proceedings were selected from among 39 submissions. The technical program includes five regular sessions, two poster sessions, two invited talks and a panel discussion. We would like to express our sincere thanks to all those who have contributed to the success of the workshop. In particular, we would like to thank all the members of the program committee and reviewers for their valuable time and effort in the review process, and to provide constructive feedback to the authors. We also acknowledge the support of the IPDPS organizing committee and IEEE Computer Society in producing these proceedings. Finally, we thank all authors who contributed to this workshop, for submitting their manuscript and sharing their latest research results with the RAW community. We hope that you will find in these proceedings a valuable source of information for your future work. Juergen Becker Ramachandran Vaidyanathan Peter Athanas Marco Santambrogio René Cumplido Oliver Sander
Organizing Committee Workshop Chairs: Jürgen Becker, Karlsruhe Institute of Technology, Germany Ramachandran Vaidyanathan, Louisiana State University, USA Program Chair: Peter Athanas, Virginia Tech., USA Program Vice-Chairs: Architectures and Algorithms: Marco Santambrogio, Politecnico di Milano, Italy Reconfigurable Systems & Applications: René Cumplido, INAOE, México Software & Tools: Oliver Sander, Karlsruhe Institute of Technology, Germany Steering Chair: Viktor K. Prasanna, University of Southern California, USA Steering Committee: Jürgen Becker, Karlsruhe Institute of Technology, Germany Viktor K. Prasanna, University of Southern California, USA Ramachandran Vaidyanathan, Louisiana State University, USA Publicity Co-Chairs: Americas: Ramachandran Vaidyanathan, Louisiana State University, USA René Cumplido, INAOE, México Europe, Asia: Reiner Hartenstein, Kaiserslautern University of Technology, Germany Pascal Benoit, LIRMM, Montpellier, France
978-0-7695-4979-8/13 $26.00 © 2013 IEEE DOI 10.1109/IPDPSW.2013.282
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Program Committee Hideharu Amano, Keo University, Japan Jason Anderson, University of Toronto, Canada Hugo Andrade, National Instruments, Berkeley, USA David Andrews, University of Arkansas, USA Armando Astarloa, University of the Basque Country, Spain Zachary Baker, Los Alamos National Laboratory, USA Jason Bakos, University of South Carolina, USA Pascal Benoit, University of Montpellier, France Neil Bergmann, University of Queensland, Australia Koen Bertels, TU Delft, The Netherlands Christophe Bobda, University of Arkansas, USA Joao M. P. Cardoso , University of Porto, Portugal Ray Cheung, University of California, Los Angeles, USA Eduardo De La Torre, Universidad Politenica de Madrid, Spain Oliver Diessel, University of Newcastle, Australia Pedro Diniz, USC Information Sciences Institute, USA Carl Ebeling, Altera, USA Hatem El-Boghdadi, Cairo University, Egypt Ahmet Erdogan, University of Edinburgh, UK Suhaib Fahmy, Nanyang Technological University, Singapore Jorge Finochietto, University of Cordoba, Argentina Tannous Frangieh, GE Research, USA Diana Goehringer, Fraunhofer IOSB, Germany Guy Gogniat, Bretagne-Sud University, France Yajun Ha, National University of Singapore, Singapore Pao-Ann Hsiung, National Chung Cheng University, Taiwan Michael Heubner, Ruhr-University of Bochum, Germany Weirong Jiang, Xilinx, USA Krzysztof Kepa, Virginia Tech, USA Andreas Koch, TU Darmstadt, Germany Herman Lam, University of Florida, USA Yuchun Ma, Tsinghua University, China Gabriel Marchesan Almeida, Karlsruhe Institute of Technology, Germany Liam Marnane, University College Cork, Irelend Seda Ogrenci Memik, Northwestern University, USA Christian Pilato, Politecnico di Milano, Italy Marco Platzner, University of Paderborn, Germany Christian Plessl, University of Paderborn, Germany Vincenzo Rana, EPFL, Switzerland Kentaro Sano, Tohoku University, Japan Ron Sass, University of North Carolina-Charlotte, USA Gerard Smit, University of Twente, The Netherlands Melissa Smith, Clemson University, USA Hayden So, University of Hong Kong, China Neil Steiner, University of Southern California ISI, USA Christof Teuscher, Portland State University, USA Lionel Torres, University of Montpellier, France Jerry Trahan, Louisiana State University, USA Ranga Vemuri, University of Cincinnati, USA Vivek Venugopal, United Technologies, USA Steve Wilton, University of British Columbia, Canada Roger Woods, Queen's University of Belfast, UK
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RAW 2013 Keynote 1 Unleashing Software Developers into the World of Reconfigurable Computing/Logic Jaime Cummins, CEO, Pico Computing Abstract: Today reconfigurable is the world of a small set of Hardware engineers. It is too alien and challenging for Software engineers to participate. What is needed to open the world to Software developers, and how this changes everything, enabling a new golden era of reconfigurable computing and applications? About the Speaker: Jaime Cummins is the CEO of Pico Computing focused on delivering HPC from embedded to Super Computer class using reconfigurable computing hardware and techniques. Prior to Pico he founded Edison Labs an independent R&D company developing advanced mobile phone apps, and conducted research in new semiconductor hardware and products. He was also the co-founder and CEO of Element CXI and QuickSilver Technology companies developing new adaptive semiconductor devices focused on heterogeneous processing, new forms of programmable logic/computing, instantaneous re-configuration and high degrees of reliability and robustness. In his career he was also the General Manager of Reconfigurable Logic at Xilinx, Director of Engineering for Interactive TV and broadband Communications at Pacific Bell, and Director of the Macintosh Operating System group for Apple Computer. He received a BA in Logic from the University of California and attended the Graduate School of Engineering and Computer Science at California State University, Sacramento.
RAW 2013 Keynote 2 The All Programmable SOC FPGA at the Heart of Embedded Systems Ivo Bolsens, Senior Vice President and CTO, Xilinx Abstract: Today’s FPGAs have become ‘All Programmable SOC Platforms’ that integrate in one single device multicore CPU’s, programmable DSP functions, programmable IO and programmable logic, all immersed in a rich and configurable interconnect network. These programmable platform FPGA’s allow for the implementation of heterogeneous multi-core architectures that combine traditional CPU’s with application-specific processing cores and dedicated data transfer and storage functions. This is enabled by tools that guide designers during the partitioning and mapping of high-level specifications onto a combination of software running on embedded processors and hardware implemented in programmable logic. FPGAs are well placed to continue to benefit from Moore’s law. Advances in process scaling will be augmented with new circuit and architectural improvements along with innovations in system-in-package technology to solve IO challenges and integrate heterogeneous technologies. These innovations will allow designers to build higher performance and lower power systems that optimally exploit the programmable FGPA architecture. As FPGA platforms continue to deliver more performance at lower cost and lower power, they are becoming the heart of embedded applications such as complex packet processing for networks with line rates of 400+ Gbps; high performance digital signal processing in novel wireless baseband and radio functions; and future video and image processing systems. About the Speaker: Ivo Bolsens is senior vice president and chief technology officer (CTO), with responsibility for advanced technology development, Xilinx research laboratories (XRL) and Xilinx university program (XUP). Bolsens came to Xilinx in June 2001 from the Belgium-based research center IMEC, where he was vice president of information and communication systems. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals. He also headed the research on design technology for high-level synthesis of DSP hardware, HW/SW co-design and system-on-chip design. Bolsens holds a PhD in applied science and an MSEE from the Catholic University of Leuven in Belgium.
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