Jul 23, 2008 - (75) Inventors: Jon M. Huppenthal, Colorado Springs, .... Conformal Electronic Systems, University of Ark
USO0RE42035E
(19) United States (12) Reissued Patent Huppenthal et a1. (54)
(10) Patent Number: US RE42,035 E (45) Date of Reissued Patent: Jan. 18, 2011
RECONFIGURABLE PROCESSOR MODULE
6,051,887 A 6,072,234 A
COMPRISING HYBRID STACKED INTEGRATED CIRCUIT DIE ELEMENTS
*
4/2000
Hubbard ................... .. 257/777
*
6/2000
Camien et a1. ............ .. 257/686
6,092,174 A
7/2000 Roussakov
6,313,522 B1 * 11/2001
6,337,579 B1
(75) Inventors: Jon M. Huppenthal, Colorado Springs, CO (U S); D. James Guzy, Glenbrook,
NV (U S) (73) Assignee: Arbor Company LLP, Glenbrook, NV
(Us)
6,449,170 B1 *
9/2002
6,452,259 B2
9/2002 Akiyama
Nguyen et a1. ............ .. 361/778
6,781,226 B2 * 6,991,947 B1 *
8/2004 1/2006
Huppenthalet a1. ....... .. 257/686 Gheewala .. 438/15
7,082,591 B2 *
7/2006
Carlson ............. ..
7,126,214 B2 * 10/2006 Huppenthalet a1. 7,183,643 B2 * 2/2007 7,282,951 B2 * 10/2007
(21) Appl.No.: 12/178,511 (22) Filed:
Akram et a1. ............. .. 257/686
1/2002 Mochida
716/16
257/686
Gibson et a1. ....... .. 257/723 Huppenthalet a1. ......... .. 326/41
FOREIGN PATENT DOCUMENTS
Jul. 23, 2008 JP
08-268189
4/1998
Related US. Patent Documents OTHER PUBLICATIONS
Reissue of:
(64) Patent No.: Issued: Appl. No.:
6,627,985 Sep. 30, 2003 10/012,057
Filed:
Dec. 5, 2001
(51)
(52)
English Translation of O?ice Action received in JP 551682/ 2003 Which claims priority to US. patent no. 6,627,985, Which is the reissue U.S. Appl. No. 12/178,511.
(Continued)
Int. Cl. H01L 23/02 H05K 7/06
(2006.01) (2006.01)
US. Cl. ...................... .. 257/686; 257/685; 257/209;
257/529; 257/700; 257/530; 257/922; 361/767; 361/783; 361/778; 326/51 (58)
Field of Classi?cation Search ................ .. 257/686,
257/685, 209, 529, 700, 530, 922, 724, 778; 326/38411, 51; 361/778, 767, 783, 719, 744, 361/760, 784, 792, 803 See application ?le for complete search history. (56)
References Cited U.S. PATENT DOCUMENTS
5,585,675 A 5,652,904 A
12/1996 Knopf 7/1997 Trimberger
5,793,115 A
*
5,838,060 A
* 11/1998
8/1998 Zavracky et a1. .......... .. 257/777 Comer
5,953,588 A
*
Camien et a1. ............ .. 438/106
9/1999
Primary ExamineriVibol Tan (74) Attorney, Agent, or Firmiwilliam J. Kubida; Peter J. MeZa; Hogan Lovells US LLP
(57)
ABSTRACT
A recon?gurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module With
recon?gurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or ?eld
programmable gate array (“FPG ”) die elements and inter connecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed alloWs for a signi?cant acceleration in the sharing of data between the microprocessor and the FPGA element While advanta
geously increasing ?nal assembly yield and concomitantly reducing ?nal assembly cost.
......... ..
38 Claims, 4 Drawing Sheets
coancr
‘6M7, PGINTS
US RE42,035 E Page 2
OTHER PUBLICATIONS
NeW Process Forms Die Interconnects by Vertical Wafer
HintZke, Jeff, Probing Thin Wafers Requires Dedicated
neWs8.html, ChipScale RevieW, Jan?Feb. 2000, Oct. 18,
Measures, http://eletroglas.WWW.com/products/White%20 Paper/HintZke Thin Paper,html, Eletroglas, Inc. Aug. 21, 2001, pp. 1*6.*
Lammers, David, AMD, LSI Logic Will put processor, ?ash
in
single
package,
http://WWW.csdmag.com/story/
OEG20001023S0039, EE Times, Aug. 21, 2001, pp. 1*2.*
MultiiAdaptive Processing (MAPTM), http://WWWsrccomp. com/products map.htm, SRC Computers, Inc. Aug. 22, 2001, pp. 1*2.*
System Architecture, http://WWW.srccomp.com/products. htm, SRC Computers, Inc., Aug. 22, 2001, pp. 1*2.*
Con?gurations, SRC Expandable Node, http://WWW.src comp.com/products con?gs.htm, SRC Computers, Inc. Aug. 22, 2001, p. 1.*
Young, Jedediah 1., Malshe, Ajay P., BroWn, W.D., Lenihan, Timothy, Albert, Douglas, OZguZ, Volkan, Thermal Model ing and Mechanical Analysis of Very Thin Silicon Chips for Conformal Electronic Systems, University of Arkansas, Fay etteville, AR, pp. 1*8., No date.*
Stacking,
http://WWW.chipscalerevieW.com/0001/tech
2001, pp. 1*3.*
Savastiouk, Sergey, Siniaguine, Oleg, Francis, David, Thin ning Wafers for Flip Chip Applications, http:// WWW.iii1.com/hdiarticle.html, International Interconnection Intelligence, Oct. 18, 2001, pp. 1*13.*
Savastiouk, Sergey, Siniaguine, Oleg, KorcZynski, Ed, Ultraithin Bumped and Stacked WLP using ThruiSilicon
Vias, http://WWW.ectc.net/advance program/abstracts2000/ s15p1.html, TruiSi Technologies, Inc., Oct. 18, 2001, p. 1.* Savastiouk, Sergey, NeW Process Forms Die Interconnects
by Vertical Wafer Stacking, http://WWW.trusi.com/ article9.htm, ChipScale RevieW, Oct. 18, 2001, pp. 1*2.* Savastiouk, Sergey, Moore’s Lawithe Z dimension, http:// WWW.trusi.com/article7.htm, SolidState Technology, Oct. 18, 2001, pp. 1*2.*
ThroughiSilicon V1as, http://WWW.trusi.com/throughsili convias.htm., TruiSi Technologies, Oct. 18, 2001, p. 1.* * cited by examiner
US. Patent
Jan. 18, 2011
US RE42,035 E
Sheet 1 0f 4
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Jan. 18, 2011
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US RE42,035 E
Sheet 2 0f 4
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