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Reliability of a Silicon Stacked Module for 3-D SiP Microsystem Seung Wook Yoon, Samuel Yak Long Lim, Akella G. K. Viswanath, Serene Thew, Tai Chong Chai, and Vaidyanathan Kripesh
Abstract—Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO2 deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test ( 40 125 C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper. Index Terms—Solder joint reliability, three-dimensional (3-D) silicon micro module, pb-free solder.
I. INTRODUCTION
I
N THE fast-paced world of electronic products, the development of more functional density in silicon wafers and packages is a definite trend. Miniaturization trends demands not only per unit area reduction but also per unit volume reduction, which is of course driven by major market factors such as portable computing, mobile commerce (m-commerce), wireless LANs connecting servers, PCs, and other portable products. Real estate efficiency is very important in terms of performance and cost. High-density packaging has become an important drive in the emergence of multifunctional portable electronics, i.e., digital/functional convergence ages. For example, handheld and network applications are becoming more sophisticated and powerful in their functions, component counts tend to increase due to larger system-scale and memory capacity.
Fig. 1. (a) Schematics of 3-D stacked module using silicon carriers and (b) assembled silicon stacked module with glass cap.
In this background, the 3-D packaging technology has become a key technology for meeting the needs of integration, compactness and lightness. And 3-D-SiP market is expected to have compound annual growth rate (CAGR) of 55.6% for 2002–2007, which is far exceeding the growth rates of other packaging sector [1]. SiP technologies of future would call for integration of heterogeneous chips (e.g., silicon, GaAs, Si-Ge chips) with multiple functionalities [e.g., digital, radio frequency (RF), optical, micro-electro-mechanical systems (MEMS)], and structural insulated panels (SiP) interposer shall provide good electrical and thermal performances, with a mechanically stable structures and testable features. Silicon stacked module, using Si with through hole interconnects as intermediate carriers, where known good dice can be either flip chip attached or wire bonded to assemble functional carriers. Each stack can be stacked over the other to form 3-D stacked modules, as shown in Fig. 1. The carrier wafer is functionally tested on the wafer level, thus increasing the total assembly module yield. In this paper, the solder joint reliability of flip chip on the silicon carrier is discussed. II. EXPERIMENTAL DETAILS
Manuscript received August 28, 2006; revised March 19, 2007; May 28, 2007. This work was recommended for publication by Associate Editor S. Sitaraman upon evaluation of the reviewers comments. S. W. Yoon, S. Y. L. Lim, S. Thew, T. C. Chai, and V. Kripesh are with the Institute of Microelectronics (IME), Singapore Science Park II, Singapore 117685. A. G. K. Viswanath is with the Institute of High Performance Computing (IHPC), Singapore Science Park II, Singapore 117528 ( e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TADVP.2007.914971
A. Mechanical Simulation Results To investigate the solder joint reliability, finite element method (FEM) was carried out and 3-D octagon model was constructed, as shown in Fig. 2. In case of solder, elastic-plastic-creep constitutive model is used for Pb free Sn–Ag–Cu solder joints [2], [3]. Material properties used in these simulation works are listed in Table I. The solder joint life time was calculated based on the energy based model [4].
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Fig. 2. Octagonal FEM modeling of silicon stacked module.
TABLE I MATERIAL PROPERTIES USED IN MECHANICAL SIMULATION
B. Test Vehicle Fabrication 1) Flip Chip Test Vehicle Fabrication: Four different flip chip test vehicles were fabricated with 250-, 200-, and 150- m pitches. The test vehicles details are shown in Table II. A 7-in soda-lime mask was fabricated to carryout the process on a contact aligner. A n-type 8-in silicon wafer with resistivity 10–50 was used for the experimental evaluation and thin blanket silicon oxide was deposited on the wafer by plasma enhanced chemical vapor deposition (PECVD). A 1- m Al layer was deposited by physical vapor deposition (PVD) sputtering and it was patterned in such way to mimic the device I/O pads. A thin layer of SiO passivation covering the I/O pads were deposited with an over lap of 10 m on each side. After SiO passivation, the wafers were sent for under bump metallurgy (UBM) deposition. A proven electroless Ni immersion gold (ENIG) UBM was deposited by electroless plating method. The solder bumping on the test wafer were carried out by dry film paste printing process. The wafer was laminated with a photoimagable dry film (Asahi Sunfort dryfilm YPQ-50) using a hot roll laminator. The PET film cover the photo-imagable surface was peeled off and exposed with broad band UV light using a bump mask. The dry film was further developed using a sodium bicarbonate solution. The pad opening is decided based on the volume of the solder required. Dry films were used with a thickness of 50 m thickness. After the exposure of the dry film, solder paste is squeezed into the hole using a polyurethane squeeze. The excess paste is removed and wafer is reflowed in eight zone IR convection furnace as per the reflow profile suggested by the vendor with a peak dwell time of 90 s and reflow temperature of 260 C for Sn-4Ag-0.5Cu
solder. The dry film stripped and removed using a stripper of sodium hydro-oxide solution. After the dry film is stripped, the test wafer was reflowed under nitrogen atmosphere of less than 20 PPM oxygen level. The peak temperature was 260 C and the dwell time above 240 C was about 42 s. The reflowed test wafer was cleaned under a semi-aqueous cleaning process with a solvent cleaner, followed by deionized (DI) wafer spray and Nitrogen air blow. Flux residue on the test wafer was removed completely. The bumped test vehicle wafers as described earlier was thinned to 100 m by mechanical backgrinding (BG) and slurry polishing by OKAMOTO so as to flip chip attach it onto the silicon carrier with a low profile height. A suitable BG tape for 75- m bump height was selected followed by BG tape lamination process optimization and BG process parameters optimization for 100 m ultra thinning. Fig. 3 shows the micrographs of four different bumped flip chip test vehicles. 2) Silicon Carrier Fabrication: Deep reactive ion etching (DRIE) process was used in forming 200 m diameter through via holes in a 8-in silicon wafer of 400 m thickness. The process started with depositing oxide on the top of the wafer. This oxide serves as an etch stop layer during the through hole via process. A thick photo resist is deposited on the wafer for good selectivity during the etch process. The photo resist is patterned using a mask aligner. The wafer is etched using DRIE method. After etching the photo resist is stripped and cleaned using a photoresist strip solution. The oxide is etched away to expose the through silicon via. To isolate the through hole via from the wafer substrate an insulation layer and a barrier layer is deposited. The insulation layer used is a PECVD
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TABLE II FLIP CHIP TEST VEHICLES SPECIFICATIONS
Fig. 3. Micrographs of flip chip test vehicles: (a) 250-pitch; (b), (c) 200-m pitch; and (d) 150-m pitch.
Fig. 4. Schematics of silicon carrier fabrication process. (a) Wafer via formation and Cu via plating. (b) Multilayer process of SiO2 dielectrics and metal route. (c) Solder bump formation.
oxide and barrier layer is silicon nitride. Silicon nitride acts as a barrier layer for preventing the filler metal (Copper) from diffusing into silicon wafer while silicon oxide would serve as a dielectric isolation layer. Through silicon via wafer formed was bonded to another wafer, handler wafer for electro plating process. Through silicon via wafer was then bonded to the handler wafer either by polymer bonding or dryfilm bonding method. After electroplating the vias, the handler wafer needed to be separated so that the electroplated through hole via wafer could be used for silicon carriers. After separation, multilayer process was carried out for three silicon oxide dielectrics layer was deposited and two metal layers were prepared for interconnection. PECVD SiO was deposited up to 1 m thickness and patterned by dry etching process and 1 K Ti/10 K Cu was deposited by PVD, patterned and wet-etched to make metal route. Final metal pad for UBM was 1 K Ti/3 K Ni/7 K Cu/1 K Au. Finally, solder ball was attached on the UBM pad. Fig. 4 represents the process flow for silicon carrier fabrication and Fig. 5 showed the layout design of each of the three silicon carriers. 3) PCB Board Design and Fabrication: Printed circuit board (PCB) substrate was fabricated for temperature cycle
(TC) and drop test evaluations. JESD22-B111 defines a preferred test board construction, dimensions and material that represents those typically used in hand held electronic products, which uses built-up multilayer technology with microvias [5]. The overall test board size is 132 mm 77 mm and it is designed to meet all the recommended dimensions of the JESD standard with the exception of using the built-up multilayer structural and materials set. Features such as plated through holes, nonsonder mask defined (NSMD) pad design, solder mask clearance and line width, etc., are in accordance with the JESD standard. Based on JESD22-B111 standards design, the PCB design was carried out and PCB was fabricated by two layer board, as shown in Fig. 6. 4) Assembly: Ultra thin reliability dice are flip chip attached onto the silicon carrier with through hole interconnects using conventional flip chip attach process. Flip chip attach is done in an automatic flip chip bonder (Karl Süss FC150) where the chip in the waffle pack is picked up by a pick up tool followed by prealign, flux dip, align with silicon carrier and a bonding process. Once the flip chip is placed onto the silicon carrier, the carrier is reflowed in a reflow oven. After carrier stacking, glass cap was attached on the top of silicon carriers with epoxy, as
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Fig. 5. Design of each carrier substrates: (a) first layer silicon carrier; (b) second layer silicon carrier; and (c) third layer silicon carrier.
Fig. 6. (a) PCB substrate and (b) layout desing of PCB for TC and droptest.
Fig. 7. Pictures of silicon stacked module test vehicles after board level assembly.
shown in Fig. 1(b). Final tests vehicles were assembled on PCB, as shown in Fig. 7. C. Reliability Tests Each flip chip and stack assembly is checked for electrical continuity by probing the daisy chain from top of the silicon carrier. Fig. 8 showed the schematics of daisychain interconnections between through via and each carriers, as well as flip chip daisychains. Table III summarized the each daisychains details for flip chip device and carrier interconnections. Solder joint reliability test vehicles were placed on the TC chamber ( C, 2 cycles/h) and daisy chain resistance was monitored. The drop test was carried out for silicon stacked module on PCB board as same as TC test. The drop testing was performed on commercial shock tester AVEX SM 110-MP with both the
Fig. 8. Schematics of daisychain interconnections in silicon stacked module.
anvil and test specimen supporting carriage made of cast aluminum. An aluminum base plate with standoffs (6 mm OD/3.2 mm ID, 10 mm height) for supporting the test board is rigidly mounted to the top of the carriage. A half sine generator pad
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TABLE III DAISYCHAIN INTERCONNECTION SCHEME FOR INTERCONNECTS RELIABILITY TEST
Fig. 9. Pictures of (a) drop impact test vehicle setup and (b) 0.5 ms half sine pulse for drop impact test condition.
TABLE IV CALCULATED SOLDER JOINT RELIABILITY OF T/C TESTS
is employed between the anvil and carriage to generate the desired impact (e.g., 1500 G) and pulse duration (e.g., 0.5 ms) through the pneumatic pressure driving system of AVEX machine. The applied shock pulse to the test board is monitored by accelerometer mounted near at the supporting post of the test board. Fig. 9(a) showed the test samples attached on drop impact tester For the purpose of the test, the JESD recommended Condition B (e.g., 1500 G, 0.5 ms duration, and half-sine pulse) was adopted, as shown in Fig. 9(b). The resistance was measured as event detector with connected oscilloscope and resistance measurement tools up to 30 drops. III. RESULTS A. Mechanical Simulation Results The results showed that there was no significant stress in the solder interconnects between silicon carriers. The most critical solder ball was the outer most solder ball in first silicon carrier (bottom silicon carrier attached on PCB). According to this
study, board level solder joint life time was calculated less than 500 cycles without underfill. But after underfill, the solder joint life time was increased four times, that is, 2197 cycles. And in case of flip chip solder joint attached on silicon substrate, calculated characteristic solder joint life time was around 10 000 TC cycles for all flip chip devices. Table IV shows the results of solder joint life time for flip chip solder joints and board level solder joint. B. Solder Joint Reliability Test 1) Board Level Solder Joint Reliability Test: Solder joint reliability test vehicles were placed on the T/C chamber ( C, 2 cycles/h) and daisy chain resistance was monitored in every 100 cycles up to 500 cycles. After 500 cycles, failure was found and failure analysis was carried out as shown in Fig. 10. Crack was found at the silicon carrier side. This is good agreement with mechanical simulation results of Table IV. After underfill dispensing, T/C test was performed
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Fig. 10. Micrographs of board level solder joint failure after 500 T/C cycles without underfill. Fig. 13. Plot of resistance measurement with T/C cycles of flip chip-to-silicon carrier solder joint reliability test.
Fig. 11. SEM micrograph of board level solder joint after 1000 T/C cycles with underfill.
Fig. 14. Micrographs of flip chip-to-silicon carrier solder joint after 3000 T/C cycles without underfill: (a) 250 m pitch; (b) 200 m pitch, and (c) 150 m pitch.
values even after 5000 cycles. In initial stage, the resistance increase was detected but thereafter there was no more increase in values. It may due to the contact resistance of probing pad or probe tip at initial measurement. After 3000 cycles, micro-polishing of solder joint cross-section was carried out in order to investigate the microstructures and potential failure at solder joint. As shown in Fig. 14, no crack or failure was found for all three different flip chip test vehicles attached on silicon carriers. C. Drop Test Reliability Test
Fig. 12. Plot of accumulated solder joint failure of silicon carrier with T/C cycles solder joint reliability test.
again and no failure was found up to 1000 T/C cycles. Fig. 11 showed the micrograph of solder joints with underfill after 1000 T/C cycles. It showed the quite sound interconnections in Cu via as well as solder joint after T/C tests. Fig. 12 shows the accumulated solder joint life time failure after T/C tests for underfilled and no underflled silicon stacked modules. 2) Flip Chip-To-Si Carrier Solder Joint Reliability Test: Solder joint reliability test vehicles were placed on the T/C chamber and daisy chain resistance was monitored in every 200 cycles up to 3000 cycles. After 3000 cycles, the resistance was measured in 500 cycles up to total 5000 cycles. Fig. 13 showed the resistance changes with TC cycles and relatively stable
Silicon stacked module level solder joint was monitored with daisy chain interconnections connected to oscilloscope and in situ resistance measuring unit. Five silicon stacked modules were assembled for this test. Two groups of samples were prepared, one was with underfill and the other was without underfill. In case of last group, without underfill, all samples could not pass the five drops and failure was found at the board level solder joint interconnects, especially pad delamination from PCB was major failure mode in this study as shown in Fig. 15. After failure analysis, there were no disconnection found at the other interconnects among silicon carriers, Cu vias or flip chip-to-silicon carrier interconnects. To improve the reliability, underfill was applied to the PCB assembled test vehicles (only for first silicon carriers attached on PCB). After underfill encapsulation, all samples successfully pass the drop impact reliability test up to 30 drops. IV. CONCLUSION To investigate the solder joint reliability of 3-D silicon stacked module, 3-D FEM works and solder joint reliability
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[2] J. H. L. Pang et al., “Bulk solder & solder joint properties for lead free solder alloy,” presented at the 53rd Electron. Compon. Technol. Conf., New Orleans, LA, 2003. [3] B. S. Xiong et al., “Creep and fatigue characterization of Pb free solder,” presented at the 54th Electron. Compon. Technol. Conf., Las Vegas, NV, 2004. [4] X. Wu, “Computational parametric analyzes on the solder joint reliability of bottom leaded plastic (BLP) package,” IEEE Trans. Adv. Packag., vol. 25, no. 4, pp. 514–521, Nov. 2002. [5] Board level drop test method of components for handheld electronic products, JEDEC Standard JESD22-B111, Jul. 2003.
Fig. 15. Micrographs of failure analysis after drop impact test without underfill. (a) PCB side. (b) Silicon substrate side.
tests were carried out. In case of PCB board level reliability, characteristic solder joint reliability was 531 TC cycles without underfill. Failure was found at the solder joint in silicon carrier side due to more stress from thermal mismatch between solder and silicon carrier . Addition of underfill to the silicon stacked module, there was no failure after 1000 TC cycles. The characteristic life time was 1824 TC cycles. These results were in good agreement with those of solder joint FEM simulation. In flip chip-to-silicon carrier solder joint reliability, it showed robust solder joint reliability up to 5000 T/C cycles without underfill. This is due to no global mismatch between flip chip and substrate because of both materials of silicon even though there is still local mismatch between solder and silicon. After JEDEC standard drop impact test, the failure was not detected after 30 drops for three different pitch flip chip-to-silicon carrier and underfilled silicon stacked modules with module interconnection (intersilicon substrate) and board level interconnects. For silicon stacked module, flip chip solder joint on silicon carrier, Cu via interconnects and inter-silicon carriers were robust but board level reliability of solder joint and drop impact test was still not good enough for real application without underfill. So underfill encapsulation plays quite important role in improving board level reliability for 3-D silicon stacked module with through silicon via interconnects.
Seung Wook Yoon received the Ph.D. degree in materials science and engineering from KAIST, Daejeon, Korea, in 1998. He is Action Deputy Lab Director of MMC (Microsystem, Module and Components) Laboratory, Institute of Microelectronics (IME), Singapore. He has been at IME for six years (or since 2002) with his major interest fields are Cu/low-k/ultra low-k packaging, TSV (trough silicon via) technology, 3-D silicon technology, wafer level integration and microsystem packaging. Prior to joining IME, he was MTS (Member of Technical Staff) position for Advanced Electronic Packaging and Module Development at Hynix Semiconductor from 1998. He has over 70 journal papers and conference papers and several U.S. patents on microelectronic materials and microsystem packaging.
Samuel Yak Long Lim received the degree in mechanical and manufacturing (honours) from the University of South Australia, Adelaide, Australia, and the diploma in mechatronics from Temasek Polytechnic, Singapore. He is a Laboratory Officer in Institute of Microelectronics (IME) under the Microsystems, Modules and Components Laboratory. His main interest is in developing low cost packaging processes.
Akella G. K. Viswanath received the M.S. degree in mechanical engineering from the National University of Singapore. He is currently working toward the M.B.A. degree in India. He worked as a Research Officer with Institute of High Performance Computing, A*STAR, Singapore, for two years. His research interests are in the areas of thermomechanical analysis, reliability modeling and analysis, and nonlinear processes analysis. He has authored or coauthored more than five research publications in electronic packaging journals and confer-
ACKNOWLEDGMENT This work is the result of a project initiated by the IME EPRC7 (Electronic Package Research Consortium VII)—Project 1: Silicon stacked module, the members of which are ASM Technology Singapore Pte. Ltd., Asperation Oy, Atotech S.E.A. Ltd., Honeywell Singapore Pte. Ltd., Hewlett-Packard Singapore Pte. Ltd., Infineon Technologies Asia Pacific Pte. Ltd., Motorola Malaysia Sdn Bhd, Philips Semiconductors ATO, United Test And Assembly Center Ltd. and MSPI (Microsystem packaging Initiative, Institute of microelectronics, Institute of Materials Research and Engineering, Institute of High Performance Computing Singapore Institute of Manufacturing Technology). REFERENCES [1] M. Marshall, “Semiconductor End-use market drivers,” presented at the 3-D Architectures Semiconductor Integration Packag. Conf., San Jose, CA, Apr. 13–15, 2004.
ences.
Serene Thew is a Laboratory Officer in Institute of Microelectronics (IME) under the Microsystems, Modules and Components Laboratory. Her main interest is in packaging and board level reliability tests and failure analysis for microsystem including WLP, TSV, and photonic packaging.
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Tai Chong Chai is a Member, Technical Staff in Microsystems, Modules and Components lab in Institute of Microelectronics. He has worked on area of packaging development, reliability, and failure analysis for 18 years. Recently, his focus is flip chip packaging for Cu low K chip and TSV technology.
Vaidyanathan Kripesh received the Ph.D. degree from Max-Planck Institute, Stuttgart, Germany. He has a wide experience in packaging industry for the last 18 years. Presently, he is a Senior Member of Technical Staff at Institute of Microelectronics, Singapore heading a group of researchers in 3-D-stacked module, wafer level packaging and guided self assembly processes. He holds a Adjunct faculty position at National University of Singapore (NUS), where he is teaching Microelectronics packaging for graduate students. He is also providing short course at leading conferences such as EPTC, etc., and also to in-house staffs in flip chip packaging. He has 15 international patents and more than 75 publication to his credit. He is also the President on International Microelectronics Packaging Society (IMAPS), Singapore chapter. He has delivered more than 28 invited talks and chaired various international conferences.
