Registers & Counters - Electrical and Computer Engineering
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Registers & Counters - Electrical and Computer Engineering
5. 9. BCD Ripple Counter. ▫. Counter must reset itself after counting the terminal
count. 10. Synchronous Counters. ▫. A common clock is applied to all flip-flops.
ECE 223 Digital Circuits and Systems
Registers & Counters M. Sachdev Dept. of Electrical & Computer Engineering University of Waterloo
1
Registers
Register is a group of flip-flops
n-bit register has n flip-flops Can hold n bits of binary data Register may also contain combinational logic
2
1
Register with Parallel Load
Specific control signal to load n-bit data
Load =0, register retains the data Load = 1, register accepts new data
3
Shift Register
Capable of shifting data in one or both directions
Clock controls the shift operation
Figure shows a simple shift register with left to right data shifting capability
4
2
Serial Data Transfer
Serial mode Æ Data is transferred one bit at a time
5
Serial Addition
Parallel adders
Faster, cost more logic
Serial adders
Slower n-bit addition Æ n clock cycles Less hardware
6
3
Universal Shift Register Mode Control S1
S0
Operation
0
0
No change
0
1
Shift right
1
0
Shift left
1
1
Para load
7
Ripple (Asynchronous) Counter
Counts the binary sequence
Negative edge triggered Output of one flipflop Æ Clock to the next Clock skew adds up
8
4
BCD Ripple Counter
Counter must reset itself after counting the terminal count
9
Synchronous Counters
A common clock is applied to all flip-flops
Clock skew does not add up Faster than ripple counters
Synchronous counters can be designed using sequential circuit procedure Synchronous binary counter
10
5
Up-Down Binary Counter Can count up (0000 Æ 1111) or down (1111 Æ 0000) binary sequence
11
Synchronous BCD Counter
Design a synchronous BCD counter with T flip-flops Present State
Out
Next State
Flip-flop inputs
Q8
Q4
Q2
Q1
Q8
Q4
Q2
Q1
y
TQ8
TQ4
TQ2
TQ1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
1
1
1
0
1
0
0
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
12
6
Binary Counter with Parallel Load
13
BCD Counter & Modulo-N Counter
Home work - Suppose we want to design a counter with 1,2,3,4,5,6,7,8,9 sequence (mod-9 counter)? 14
7
Counter with Unused States
A circuit with n flip-flops has 2n states
We may have to design a counter with a given sequence (unused states) Unused states may be treated as don’t care or assigned specific next state Outside noise may cause the counter to enter unused state Must ensure counter eventually goes to the valid state
