Return Via Connections for Extending Signal Link Path Bandwidth of Via Transitions Xin Chang(1), Bruce Archambeault(2), Matteo Cocchini(1), Francesco De Paulis(1), Vysakh Sivarajan(1), Yaojiang Zhang(1), Jun Fan(1), Samuel Connor(2), Antonio Orlandi(3) and Jim Drewniak(1) (1)
Missouri University of Science and Technology, Rolla, Missouri, USA, Email: xcp46,mcfk9, fd8b4, vshdc, jfan,
[email protected] (2) IBM, Research Triangle Park, North Carolina, USA Email: barch,
[email protected] (3) University of L’Aquila, L’Aquila, Italy Email:
[email protected]
Abstract – This paper discusses a fast and accurate way to assess the impact of signal vias where the return current must change reference planes, including the effect of a return current via placed various distances from the signal via. The equivalent circuit includes capacitance of the via anti-pad as well as cavity effects.
This analysis will then be extended to show an example for a thick backplane PCB with both through-hole vias and via stub structures.
Keywords – EMI, Signal integrity, via, cavity resonance
The results in this paper are simulated using a combination of simple circuit analysis and the cavity resonance technique [1]. Figure 1 (a) shows a typical via structure and a single cavity between two planes. While signal current can easily pass through the low impedance via barrel, as shown in Figure 1(b), the return current path constructed by the plate pair behaviors as a parallel plate capacitor at lower frequency and cavity resonances at high frequency. On the other hand, two parasitic capacitors (called antipad capacitances herein) are used to model the displacement currents between the via barrel and top/bottom plates. Thus, the via-plate interaction is modeled by two capacitances between each plane and the via, as well as an impedance of the plane pair which is modeled with a cavity resonance method [2-4].
I. INTRODUCTION Printed circuit boards (PCBs) use vias to route signals on different layers in order to allow large numbers of traces to be routed with a minimum number of layers in the PCB. These vias can have significant impact on both the signal quality and the EMI performance of the PCB. When a high speed signal changes from one PCB layer to another using a via, the return current on the nearest plane that is associated with the signal while on the initial layer must (somehow) transfer to the nearest plane to the new layer. If no intentional return current vias are provided, the return current must spread over some area to use the capacitive displacement current between the plane pairs. This may cause serious noise coupling between adjacent vias or strong radiation from the edges of power/ground planes. This paper will discuss the impact on the signal quality and the EMI performance of high-speed signal vias as the return via is closer/further away from the intentional signal via. Initially, the analysis will show the effects of the return via when the signal via transitions from one reference plane to the adjacent reference plane (a single plane pair).
978-1-4244-2737-6/08/$25.00 ©2008 IEEE
II. SIMULATION METHOD
Repeating the S type circuit model for a via in a single plate pair given in Fig. 1 (b), a cascaded circuit model is set up to model any number of plane pairs, as shown in Figure 2. Each plane pair creates a cavity, and the impedance Zpp seen at the via location for that size cavity is then inserted into the equivalent circuit as also shown in Figure 2. Two microstrip lines are used to represent one stripline in order to connect to via’s circuit model. The example in Figure 2 shows a specific entry (P1) and exit (P2) layer for the signal trace, but this
approach can be easily adapted to any stackup configuration.
of planes. These configurations are shown in Figure 4.
Figure 1: Typical via structure and equivalent circuit.
Figure 4(a) shows the configuration where both vias are not connected to either plane, as would occur if the via on the right side is a (different) signal via, but potentially serving as a return current via. Figure 4(b) shows the case when the return via is connected to both planes, for example, in the case where both planes are ‘ground’ and the current return via is a ‘ground’ via. Figure 4(c) shows yet another case where the potential return via is only connected to one plane. This configuration could occur for example in the case where the upper plane is a power plane, and the lower plane is a ‘ground’ plane.
In many practical designs, decoupling capacitors or return current via (sometimes called a ‘ground’ via) are used to reduce the impedance of return current path. Figure 3 shows an example of the physical configuration and the equivalent circuit. Note that the ‘bottom’ portion of the equivalent circuit (that models the return current via) has the shorting circuits to represent the shorting via linking to the planes. If the via does not physically connect to a particular plane, that connection is simply replaced by an antipad capacitance. The Zpp blocks in the equivalent circuit are two-by-two impedance matrices for the corresponding plane pair. A tool has been developed at the UMR/MST EMC Laboratory to automatically generate and connect this type of the equivalent circuits based on via geometry input. The tool can handle multiple plane pair with hundreds of vias that could be configured differently. The antipad capacitances as well as the impedance matrices of the multiple plane pair are automatically calculated, and all the circuit elements are then connected. The Sparameters, as well as other network parameters, are obtained among the specified I/O ports. And then, optional link path and crosstalk analyses can be performed. III. SINGLE PLANE PAIR ANALYSIS Before the complete stackup is analyzed, it is prudent to first understand the effects of the distance between the current-return and the signal vias as well as the effects of the return vias that are not connected to the planes. There are three configurations with a single set
The first set of simulations show the impact of the distance between the signal via and the full GND return via (Figure 4(b)). Figure 5 shows the S21 transfer function on the signal transitioning from the upper reference plane to the lower reference plane. When there is no local GND return via, the signal loss falls off rapidly above 1 GHz. However, if a GND return via is placed 50 mils away from the signal via, the signal loss is reduced significantly and the usefulness of the via in this signal path is greatly extended to higher frequencies. At data rates above a few Gb/s, loss through the entire link path is very important, and is usually dominated by the dielectric loss. One to two dB of additional signal loss due to each via is likely to cause end-to-end link failure. Note in Figure 5 that when the GND return via is further than 100 mils distant from the signal via, resonances associated with the distance between the vias become important at frequencies above approximately 6 GHz. These resonances can have a negative impact on the signal integrity (e.g. eye opening), depending on the data rate and the harmonics of the signal. These resonance effects can have even greater impact than simple signal loss on the quality of the received signal.
Figure 2: Signal via extended to multiple plane pair crossing with equivalent circuit.
Figure 3: Signal via extended to multiple plane pair crossing with return via and with equivalent circuit.
The impact of the potential return via was analyzed to show how the intentional signal is impacted with the various possible return current vias shown in Figure 4. Figure 6 shows that if the potential return via is not connected to the plane at both ends, as in figure 4(a) and 4(c), the signal loss is identical to the case with no local return via.
(a)
(b)
(c) Figure 4: Possible return current via configurations.
Figure 5: Transfer function for via transition though one plane pair with return via at various distances
Figure 6: Impact on signal transfer function for return vias not connected to one or more planes
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Frequency [GHz] Figure 7: Signal transfer function for multi-plane transition for various return via and signal via stub configurations
IV. MULTIPLE PLANE PAIR ANALYSIS Most high-speed PCBs have more than only one pair of planes, and often have many layers and planes in the overall stackup. Figure 3 shows an example of such a stackup. In this configuration, the layers where the signal enters and exits the via, and therefore the length of the remaining via stub, can greatly impact the signal transition. In the following example 10 identical pair of planes are used and the stackup is similar to the configuration shown in Figure 3. Figure 7 shows the analysis results for three different configurations: (1) Signal via with no via stub (via through all 11 planes), (2) Signal via with a long via stub (via through only one plane), and (3) Signal via with a medium size via stub (via from top to halfway through the board). In each case, a GND via is also placed 50 mils from the signal via, and in each configuration, the close GND via improves the through signal performance V. EMI IMPACT The main focus of this paper has been on the impact to the signal quality by placing GND return vias close (or further) from the signal via. The location of the GND return via also
impacts the amount of EMI noise between the planes as a result of the signal passing through the signal via. Figure 8 shows how the nearby GND via can help reduce the amount of noise between the planes due to the via transition. This example shows the transfer function between the signal via and the noise between the upper pair of planes for the through via (no via stub) configuration. The reduction of the noise between the planes is as much as 10 dB between the no nearby r eturn via, and the GND via at 50 mils distance from the signal via VI. SUMMARY This work has shown a number of examples of the impact of a GND current return via on both signal quality and on EMI noise launched between planes in high-speed PCBs. While each specific configuration must be analyzed for the specific performance, the examples show the importance of insuring there is a GND return via close to all high-speed nets, and that the GND return via must be very close to the signal via to have the desired impact. The described method allows rapid analysis of various ‘what-if’ scenarios without the need for time consuming analysis with traditional fullwave simulation tools.
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Frequency [GHz] Figure 8 Transfer function showing amount of noise injected between planes for various return via configurations
REFERENCES [1] C. Schuster, Y.H. Kwark, G. Selli, and P. Muthana, “Developing a physical model for vias,” Proceedings IEC Design Conference2006, Santa Clara, CA, February 2006. [2] Y.T. Lo, W. Solomon, and W.F. Richards, “Theory and experiment in microstrip antennas,” IEEE Transactions on Antenna and Propagation, vol. AP-7, no.2, 37-145, March 1979.
[3] G.T. Lei, R.W. Techentin, P.R. Hayes, D.J. Schwab, and B.K. Gilbert, “Wave model solution to the ground/power plane noise problem,” IEEE Transactions on Instrumentation and Measurement,” Vol.47, No.5, May 1995, pp. 300-303 [4] C. Wang, J. Mao, G. Selli, S. Luan, L. Zhang, J. Fan, D.J. Pommerenke, R.E. Dubroff, and J.L. Drewniak, “An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductance,” IEEE Transactions on Advanced Packaging, Vol. 29., No.2, May 2006, pp. 336-342
