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Universiti _Sains Malaysia 1996

The Universiti Sains Malaysia is not responsible as a body for the facts and opinions expressed by authors in this publication.

ISBN No. 983 99203 0-8,1-6,2-4

Published by: SCHOOL OF ELECfRICAL AND ELECTRONIC ENGINEERING

UNIVERSITY SAINS MALAYSIA SRI ISKANDAR, 31750 TRONOH, PERAK, MALAYSIA

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1\_0WIJI. '96 TI-lE STUDY OF THE BEHA YIOR OF POLYNOMIAL SEEDS ON THE EFFECTIVENESS OF A COMBINED LFSR/SR AND SA PSEUDO-EXHAUSTIVE TESTING SCHEME IN THE BIST ENVIRONMENT Afaq Ahmad* D~po'f:}.'Y(ttt:~

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Theorem 2: In a combined w-bit LFSR and (n-w)-bit SR pseudo-exhaustive test scheme if the

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length of the generated test-sequence is 2w-1 then choosing any of the test-vector as combined seeds for LFSRJSR cannot change the level of the probability of aliasing errors. Proof: The claim of the theorem is obvious and thus trivial when one considers the aliasing problem in the 'error domain' . In that domain 'rotating' or ' reordering ' of the test-vectors amounts to padding the error polynomial with leading or trailing zeros . Conclusion The results of the simulation study reveals that in general the change in the seeds

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LFSRISR in LFSRJSR based pseudo-exhaustive testing technique does not have any impact upon the frequency of the aliasing errors. Thus. in this case the Multiple Compression scheme is not helpful in reducing the aliasing errors. This finding is also supported by an analytical model. References 1. MUEHLDROF, E.I. and SA VKAR, A.D ., 'LSI logic testing an overview· . IEEE Transactions on Computers. vol. C-30. no. I. I981. pp . l-17 . BUEHLER. M. G .. and SIEVERS. M. W.. 'Off-line built-in testing techniques for VLSI circuits·. 1 IEEE Computer, vol. I 5, no.6, 1982, pp.69-82 . . 3. ABADIR. M. S., and REGHBATI, H. K.. 'LSI testing techniques '. IEEE Micro. vo1.3 . no . I. 1983 . pp .34-51 .

. J. . WILLIAMS. T. W .. ' VLSI testing' . IEEE Computer. vol.l7, no . I 0. !984. pp.l26-13o.

5. BIERMAN. H.. ·vLSI test gear keeps with chip advances· . Special Report (April.19 . 19X4 )Electronics. pp . l25-128 . 6. BENNETTS, R. G., ' Design of testable logic circuits', Addision Wesley Publishing Company (London), 1984. 7. MCCLUSKEY . E.J.. ' Built-in self-test techniques', IEEE Design & Test of Computers. vo1.2. IHJ. 2. 1985. pp.21-28 . S. AHMAD. A., ·on a design approach for reducing aliasing errors and achieving higher testability goals in LFSR based testing of combinational circuits', Ph .D. Thesis. University of Roorkee. India. 1990. 9. SMITH , J. E., 'Measure of effectiveness of fault in signature analysis'. IEEE Transactions on Computers, voi.C-29, no.6, 1980, pp.Sl 0-514 . IO .AGRAWAL. V. K .• ' Increased effectiveness of built-in testing by output data modification·. Di!.!est of the (3th Int'l Symposium on Fault-Tolerant Computing (FTCS-13). (IEEE Computer Societ; Press), 1983 , pp.227-234. !!. HASSAN . S. Z., and MCCLUSKEY. E. L 'Increased fault-coverage through multiple signatures· . Digest of 14th Int'l Symposium on Fault-Tolerant Computing (FTCS-14), (IEEE Computer Society Press ), 1984.pp.354-359.

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12.BHA VSAR. D. K.. and KRlSHNAMURTHY. B .. 'Can we eliminate fault escape in self-testin~ h) polynomial division?'. Proceedings of the 1984 IEEE lnt'l Test Con f. (ITC-1984 ). (IEEE Cnmputl!: Society Press). pp.134-139. l.3.ROBINSOK J. P.. and SAXSENA. N . R.. "Simultaneous signature and syndrome compression ·. IEEE Transactions on Computer Aided Design. vol.7. no ..5. 1988. pp ..589-594. 14.AHMAD. A. and NANDA. N. K .. 'Effectiveness of multiple compressions of multiple signatures ·. International Journal ofElectronics, vol.66. no.5. 1989, pp.775-788. J 5.AHMAD. A .. NANDA, N. K., and GARG. K .. ·Are primitive polynomials always best in signature analysis?'. IEEE Design & Test of Computers, vol./, no.4, 1990, pp.36-38. 16.RAINA. R. and MARINOS, P. N .• 'Signature analysis with modified linear feedback shift registers(M-LFSRs)', Digest of 2 i st Int'l Symp. on Fault-Tolerant Computing (FTCS-21 ). (IEEE Computer Soc. Press).1991, pp.88-95 . i 7.MCCLUSK.EY. E. J .. and BOZORGUJ-NESBA T. S., 'Design for autonomous test '. IEEE Transactions on Computers. voi.C-30. no. II. 1981. pp.866-875. 18.PETERSOJ\. W.V. . .. and WELDON. J.J .. 'Error correcting codes'. (2nd editioni. MIT Press(Cambridg London). 197'2 19. GOLOMB . S.\\· .. 'Shift register sequences' . Aegean Park Press. (Leguna Hi lis. L.S.A. ). 1982. Tablel: Summary of simulated Ics : IC

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