s Clock Recovery

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PAPER

Special Issue on Ultra-High-Speed IC and LSI Technology

Exclusive OR/NOR IC for 40-Gbit/s Clock Recovery Circuit Koichi MURATA†a) , Taiichi OTSUJI† , Takatomo ENOKI†† , Yohtaro UMEDA†† , and Mikio YONEYAMA† , Members

SUMMARY The clock recovery circuit is a key component in high-speed electrical time-division multiplexing (ETDM) transmission systems. In the case of clock extraction from non-returnto-zero (NRZ) signals, differentiation and full-wave rectification are indispensable. Exclusive OR/NOR circuits (XOR) are widely used for this purpose. In this paper, we describe an XOR IC fabricated with 0.1-µm gate-length InAlAs/InGaAs/InP HEMTs for a 40-Gbit/s class clock recovery circuit. The IC was configured with a symmetrical Gilbert cell type XOR gate and two types of peaking techniques are used to achieve its high bit-rate. On-wafer-measurements indicate that the IC operates as fast as 80 Gbit/s and can extract a 40-GHz frequency component from 40-Gbit/s NRZ input signals. To confirm the feasibility of using the packaged XOR IC in clock recovery circuits, the conversion gain of the IC, which was operated as a differentiater and fullwave rectifier, was evaluated. Assuming that the input to the clock recovery circuit is a 1 Vp-p signal, the relatively high output power of −17 dBm can be obtained with low dependency on the length of the input pseudo-random bit streams. Furthermore, a clock recovery circuit was assembled using the packaged XOR IC, a waveguide filter and a commercial amplifier; it offers the practical system-bit-rate of 39.81312 GHz with the low rms jitter of 900 fs. key words: exclusive OR/NOR, clock recovery circuit, InP HEMT

1.

Introduction

Because of growing multimedia services, large capacity optical transmission systems will be required in backbone networks. The role of high-speed, reliable electronic components which operate at over 40 Gbit/s is becoming more and more important in the development of next generation cost effective systems. Clock recovery circuit is a key component to develop those transmission systems. The clock recovery circuit can have two types of circuit configuration. One uses a passive resonator. The circuit type uses a differentiater, a fullwave rectifier, a high Q resonator (filter), and a limiting amplifier. The other circuit uses a phase locked loop (PLL) constructed on a phase comparator, a loop filter, and a voltage controlled oscillator. A key component in both circuit configurations is the exclusive OR/NOR Manuscript received July 10, 1998. Manuscript revised September 18, 1998. † The authors are with NTT Optical Network Systems Laboratories, Yokosuka-shi, 239-0847 Japan. †† The authors are with NTT System Electronics Laboratories, Atsugi-shi, 243-0122 Japan. a) E-mail: [email protected]

(XOR) circuit. It realizes differentiation and full-wave rectification in the former case, and phase comparison in the latter case. To date, XOR circuits that operate at over 10 Gbit/s based on various device technologies such as AlGaAs/GaAs HBT [1]–[3], AlGaAs/GaAs HEMT [4] have been reported, and have been applied to 40-Gbit/s class PLL circuits offering phase comparison [3] and preprocessing [4]. The passive resonator type clock recovery circuit has the advantage of a simple circuit configuration without a feedback loop. However, no XOR IC has been applied to a passive resonator type clock recovery circuit operating at over 40 Gbit/s due to the difficulty of achieving high frequency operation with high output power. To overcome this barrier, the InAlAs/InGaAs/InP HEMT is the most promising approach because of its high transconductance, currentgain cut-off frequency, fT , and maximum frequency of oscillation, fmax . In this paper, we describe an XOR IC based on 0.1-µm InAlAs/InGaAs/InP HEMTs. We incorporate inductor peaking into a symmetrical exclusive OR gate (SXOR) in order to obtain high-speed operation with small timing jitter. The symmetrical configuration mainly contributes to the improvement of the output waveform quality, while the peaking technique improves the gain-bandwidth characteristic of the XOR. The IC is shown to operate as fast as 80 Gbit/s on a wafer for a standard logic application, and 40 GHz for timing extraction [5]. To confirm the feasibility of the XOR IC for use in clock recovery circuits, we assembled a clock recovery circuit with the packaged XOR IC, a waveguide filter and a commercial amplifier. The clock recovery circuit offers the practical system-bit-rate of 39.81312 GHz with low rms jitter. We simultaneously evaluated the conversion gain of the packaged IC to clarify the requirements for other components of the clock recovery circuit. The clock recovery circuit configurations and the requirements of the limiting amplifier are discussed based on the experimental results. In the next section, we describe the circuit design and the features of the SXOR circuit. The results of on-wafer-tests are reviewed in Sect. 3. This section also describes 0.1-µm InP HEMT device technologies, the measurement method, and set-up of the XOR IC. In Sect. 4, the measured conversion gain of the XOR IC module and the performance of a clock recovery circuit using the module are presented.

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Fig. 1 Circuit diagram of the XOR IC. (a) The symmetrical XOR. (b) Block diagram of the XOR IC.

2.

Circuit Design

The conventional Gilbert cell mixer is often used in both standard logic and analog applications. Figure 1(a) shows the circuit diagram of the SXOR [6], which is basically configured as a two level series-gate circuit. It consists of two Gilbert cell mixers (indicated by the shaded area) that are connected in parallel to a pair of load resistances, an input level shift stage, and output source follower circuits. Here, the input level stage consists of four source follower circuits which correspond to the output source follower circuits of the data input buffers. D1T and D1C refer to data 1 and its complementary input terminal, respectively. D2T and D2C refer to data 2 and its complementary input terminal, respectively. Note that a conventional XOR has the circuit configuration which corresponds to removing a Gilbert cell indicated by the shaded area in the Fig. 1(a) from the SXOR. In the conventional XOR, data inputs of D1T and D1C drive the first level FETs of the core XOR, and those of D2T and D2C drive the second level FETs of the core XOR through the input level shift circuits. The signal delay time of data 2 is generally larger than that of data 1 due to the additional level shift and the difference in input capacitance between the first level and second level FETs. This difference in delay time causes timing jitter especially in

the high frequency region. In the SXOR circuit configuration, the delay time difference is absolutely reduced over the entire frequency and temperature range, because the load condition of data 1 is the same as that of data 2 [6]. The symmetrical configuration contributes to the improvement in output waveform quality. In order to boost circuit speed, we also applied two types of peaking techniques [7] to the SXOR gate as shown in Fig. 1(a). The first is inserting an inductor between the load resistance and the ground. The second is capacitance peaking which is applied to the output source follower circuits to compensate for circuit loss in the high frequency region. These peaking techniques improve the gain bandwidth characteristics of the output nodes. Figure 1(b) shows a block diagram of the XOR IC. The IC consists of an input data buffer which includes data amplifiers, the core SXOR, an output buffer and an output driver. These components were designed as SCFL (Source Coupled FET Logic) series-gated circuits. The data input buffer is designed as a three-stage capacitive peaking differential amplifier [8] and a couple of source follower with capacitive peaking [7]. The simulated gain and 3-dB bandwidth of the data buffer are 11.7 dB and 24 GHz, respectively, which allows the processing of NRZ data signals at over 34-Gbit/s. The third stage data amplifier generates complementary two level data signals which are needed for the core SXOR.

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Fig. 2 Simulated output waveforms of several types of XOR ICs. (a) The conventional asymmetrical XOR with 25-Gbit/s inputs. (b) The symmetrical XOR with 25-Gbit/s inputs. (c) The symmetrical XOR with 40-Gbit/s inputs. (d) The peaking symmetrical XOR with 40-Gbit/s inputs.

The output buffer is designed as an inductor peaking amplifier, and the driver is an open drain type differential amplifier. The simulated gain and 3-dB bandwidth of the output stage are 7.8 dB and over 40 GHz, respectively, which is sufficient for 40 GHz clock extraction. The IC has single data inputs and differential outputs which can be directly connected to an SCFL interface. These inputs and outputs are connected to impedance-matched 50 and 67 Ω termination resistors, respectively, to obtain clear eye patterns. The supply voltage is −5.2 V. Figure 2 shows the simulated output waveforms of the conventional asymmetrical XOR (a) and the SXOR (b) with 25-Gbit/s data signal inputs. In this simulation, both inputs of the IC were driven by the same NRZ signal with the word length of 27 − 1 pseudo random bit stream (PRBS), and one of them was input with a half-bit-width phase shift. This operating condition corresponds to the XOR IC operating as a differentiater and full-wave rectifier in a clock recovery circuit. Here, the difference in the simulated circuit configurations is only the core XOR gate. The duty of the output waveform of the SXOR is drastically improved by the symmetrical configuration. According

to the circuit simulation, the delay time difference between the two data inputs is 6 ps which approximately corresponds to a quarter of the period of a 40-Gbit/s NRZ signal. It also indicates that the SXOR has sufficient operating margin for 40-Gbit/s operation with an excellent balance of high and low level. Figure 2 shows the output waveforms of the SXOR without (c) and with (d) the two types of peaking. The bit-rate of the input signal is 40 Gbit/s. The output waveform was especially improved by the peaking techniques in the high frequency region around 40 GHz. The maximum operating bit-rate was also estimated using transient simulations. Here, we defined the maximum operating bit rate as that at which the low level fluctuation of the output waveform was less than 10% of the output voltage swing. The SXOR with the peaking techniques operates up to 45 Gbit/s, which was approximately 30% faster than the SXOR without them. 3.

Experimental Results

An IC was fabricated using 0.1-µm InAlAs/InGaAs/ InP HEMTs [9], [10]. A novel InP gate-recess-etch stopper was inserted into the InAlAs barrier layer to drasti-

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Fig. 3

A microphotograph of the XOR IC.

cally improve the uniformity of transistor performance. Furthermore, to reduce the interconnection propagation delay by making the layout denser, small low-loss Schottky diodes using additional InAlAs/n-InAlAs layers were used. The average threshold voltage (Vth ) was −0.597 V with a standard deviation of less than 20 mV in a 3-inch wafer. The average transconductance, fT and fmax were 1.32 S/mm, 209 GHz, and 222 GHz, respectively. A microphotograph of the IC is shown in Fig. 3. The chip size was 2 mm×2 mm. The IC was tested on a wafer in two ways using dedicated 40-GHz bandwidth multiple contact probes. One way was to monitor the dipulse pattern. The timing chart and the measurement set-up for the experiment are shown in Figs. 4(a) and (b), respectively. In this measurement, one input was a 40-GHz sinusoidal wave and the other was an NRZ type 40-Gbit/s PRBS. When the rising or falling edges of these signals coincided, the output signal is always inverted at the mid-point of each time period, indicated by the dots in Fig. 4(a). Therefore, the input data bit rate is upconverted twice, resulting in double-rate dipulse output. This method makes it easy to evaluate the maximum operating speed of the logic operation, and so is suitable as the initial test confirming suitability for clock extraction application. All of the components in the measurement set-up were synthesized by a single 40-GHz signal source using a clock source module constructed with frequency dividers. The input 40-Gbit/s NRZ pulse sequence was generated by multiplexing, with appropriate delays, a complementary 10-Gbit/s 231 −1 PRBS signal in a GaAs MESFET multiplexer unit and an InP HEMT multiplexer module [11]. The output of the IC was monitored by a 50-GHz bandwidth digitizing scope by way of a 50-cm long 40-GHz bandwidth coaxial cable. The other test method was to monitor of the waveforms of the output of differentiation and full-wave rectification. Timing chart and the measurement set-up are shown in Figs. 5(a) and (b), respectively. In this

Fig. 4 Dipulse pattern measurement. (a) Timing chart. (b) Measurement set-up.

Fig. 5 Differentiation and full-wave rectification measurement. (a) Timing chart. (b) Measurement set-up.

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Fig. 7 Block diagrams of the clock recovery circuits and the discrete passive differentiater. (a) The clock recovery circuits. (b) The discrete passive differentiater.

Fig. 6 Operating waveforms of the XOR IC. (a) Dipulse pattern at 80 Gbit/s. (b) 40-GHz timing extraction waveform. (c) The frequency spectrum of the 40-GHz timing extraction.

case, both inputs were driven by equal NRZ pulse sequences half-bit-width phase shifted against each other. The methods used to generate the 40 Gbit/s data signal and monitor the waveform were the same as those used in the dipulse pattern tests. In order to boost the output voltage swing of the InP HEMT multiplexer module, a commercial pulse amplifier was inserted in the output of the MUX. Figure 6(a) shows the dipulse pattern at 80 Gbit/s. Although the insufficient bandwidth of the measurement instruments degraded the transition speed, the eye opening is still clear with sufficient voltage swing. This result indicates that the IC can operate as fast as 80 Gbit/s. Figures 6(b) and (c) show the output waveform and frequency spectrum in the 40-Gbit/s differentiation and full-wave rectification, respectively. These figures clearly show the differentiation and full-wave rectification waveforms, and the 40-GHz frequency component with −7.67 dBm output power (including the loss of cable and RF contact probe). The power dissipation of the IC was 1.7 W.

After these on wafer tests, the IC was mounted in a dedicated digital IC package [12], a ‘chip-size cavity’ package [13], and was used for clock recovery experiments. The package can accommodate up to six RF ports with V-band connectors. Ribbon bonding was used to connect the chip pads to the substrate pads. 4.

Clock Recovery Experiments

Clock recovery experiments using a passive resonator were executed to clarify the XOR IC requirements in actual applications. The XOR IC can be used in two ways in a passive resonator type clock recovery circuit. One is for differentiation and full-wave rectification, and the other for just full-wave rectification. In the latter case, a discrete differentiater is needed. In this section, we describe the measured conversion gain of the packaged XOR IC and its dependency on the input data sequences and mark ratio for both cases. The conversion gain is an important parameter in designing the power diagram of the clock recovery circuit because the parameter directly affects the design of the gain and dynamic range of the limiting amplifier, and the requirements for the insertion loss of the resonator. After that, the experimental results of clock recovery are presented and discussed. Figure 7(a) shows the block diagrams of the clock recovery circuits. The circuit was configured using the

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Fig. 8

Measurement set-up of the clock recovery circuits.

packaged XOR IC, a waveguide filter, and a commercial amplifier (HP83050A). The XOR IC operates as a differentiater and full-wave rectifier in the upper circuit configuration of Fig. 7(a), and it operates as the only full-wave rectifier in the lower circuit configuration of Fig. 7(a). In the latter case, a discrete passive differentiater, shown in Fig. 7(b), was used. The circuit consists of a 50 Ω-resistor and a quarter-wavelength shortcircuited microstrip stub on an aluminum substrate. The differentiater was mounted on a brass bed that had two RF ports with K-connectors. The center frequency of the waveguide type filter was 39.81312 GHz, which corresponds to a practical system bit-rate in the synchronous digital hierarchy (SDH). The measured Q value and insertion loss of the filter were 740 and 6 dB, respectively. The gain of the amplifier was approximately 21 dB at 40 GHz. The 39.81312 Gbit/s input data signal was generated in the same way as for the onwafer measurements. The measurement set-up for the clock recovery circuit is shown in Fig. 8. The outputs of the XOR IC and clock recovery circuit were monitored using a spectrum analyzer and a 50-GHz bandwidth digitizing scope via 40-GHz bandwidth coaxial cables that were 1 m and 50 cm, respectively. The input delay of a half bit width was created by a 40-GHz bandwidth delay line. In order to examine the conversion gain of the XOR IC, an attenuator was inserted between the pulse amplifier and the clock recovery circuit. The output voltage swing of the pulse amplifier was approximately 3 Vp-p . Figure 9(a) shows for the XOR IC the relationship between the voltage swing of the input NRZ data signal and the output power at 39.81312 GHz. In this case, the IC performed differentiation and full-wave rectification. This figure also shows the dependency on the input signal sequence. The output power was saturated with over 500 mVp-p input. Assuming over 1-Vp-p input to the clock recovery circuit, which corresponds 500 mVp-p input of the XOR IC, the relatively high output power of over −17 dBm was obtained. The IC operates as a digital IC, which means that the IC exhibits limiting operation over the input voltage range. The output power deviation due to the input PRBS sequence was

Fig. 9 Conversion gain of the XOR IC in performing differentiation and full-wave rectification. (a) PN pattern dependency. (b) Mark ratio dependency (217 −1 PRBS).

quite small especially in the saturation region. These results indicate that the IC can operate in the saturation region from the viewpoint of relaxing the gain requirements of the next stage limiting amplifier. Figure 9(b) shows the dependency of the output power on the mark-ratio for the 217 −1 PRBS input. The signal length was limited by the ability of the pulse pattern generator (PPG) used. The mark ratio varied from 1/8 to 7/8. The maximum degradation in output power in this mark-ratio variation range was less than 20 dB over the entire input power range. This parameter affects the required dynamic range of the limiting amplifier. Assuming the use of the XOR IC and the 1-Vp-p voltage swing signal interface for the input and output of the clock recovery circuit, the limiting amplifier must offer 20-dB gain with 20-dB dynamic range. Figure 10 compares the conversion gain of the IC in performing differentiation and full-wave rectification with that in performing just full-wave rectification. The horizontal axis of Fig. 10 is referred to as the input power for the XOR IC. The measured data was plotted as solid symbols in the former case, and as gray symbols in the latter case. The solid line indicates the conversion gain in the former case. It should be noted that the measurement involved the clock recovery cir-

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Fig. 10 Comparison of the conversion gain of the XOR IC in performing differentiation and full-wave rectification, and just full-wave rectification.

cuits shown in Fig. 7(a), and the insertion loss of the discrete differentiater was included in the latter case. Therefore, the true conversion gain in the latter case was estimated as the broken line considering the measured 5-dB insertion loss (as shown by the arrow in the figure). In both cases, the conversion gain was observed to saturate. The output power in the former case was much higher than that in the latter case. Even considering the measured insertion loss of the discrete differentiater, the power penalty in the case of just full-wave rectification remained steady at 6 dB. The penalty is derived from the operating principle of the XOR IC; the output voltage of the IC in just full-wave rectification becomes half that in normal XOR logic operation. It was experimentally confirmed that the using the XOR IC as a differentiater and full-wave rectifier offers better conversion gain than using it only as a full-wave rectifier. Figures 11(a) and (b) show the spectrum of the filter output, and the output wave forms of the InP HEMT MUX module and the clock recovery circuit, respectively. Here, the input signal voltage of the XOR IC was adjusted to approximately 500 mVp-p which corresponds to the clock recovery circuit input of 1 Vp-p . The 39.81312 GHz clock signal was successfully obtained with the high S/N ratio of over 40 dB as shown in Fig. 11(a). The voltage swing of the clock signal was 600 mVp-p . The output rms jitter of the clock recovery circuit was quite low at 900 fs. The phase deviation of the clock recovery circuit was over 180 degrees when the mark ratio of the input signal was changed from 1/2 to 1/8. This seems to be due to the limited phase deviation tolerance of the amplifier. To overcome this, configurations such as that in Ref. [14] should be examined, and we will need to precisely investigate the relationship between the Q value of the filter and the limiting amplifier’s characteristics.

Fig. 11 Output waveform of the clock recovery circuit. (a) Spectrum of the extracted clock signal (Filter Output). (b) Input and output waveforms of the clock recovery circuit.

5.

Conclusion

In order to develop a 40-Gbit/s clock recovery circuit, we designed and fabricated an exclusive OR/NOR IC using 0.1-µm InAlAs/AlGaAs/InP HEMTs. The IC was configured as a symmetrical Gilbert cell type XOR gate and two peaking techniques were used to achieve high bit-rate operation. The IC was found to operate as fast as 80 Gbit/s and extracted a 40-GHz frequency component from 40-Gbit/s NRZ input signals in onwafer measurements. In order to confirm the feasibility of the packaged IC for clock recovery, the conversion gain of the IC was evaluated. The output power was relatively high, −17 dBm, with quite low dependence on the input signal bit-sequence if the clock recovery circuit has 1-Vp-p input. The clock recovery circuit configuration and the requirements for the limiting amplifier were also discussed and clarified based on the experimental results. Assuming the 1 Vp-p interface for the clock recovery circuit, the limiting amplifier must offer 20-dB gain with 20-dB dynamic range. A clock recovery circuit using the packaged IC, a waveguide filter and a commercial amplifier was operated at the practical system-bit-rate of 39.81312 GHz and found to yield the low rms jitter of 900 fs.

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State Circuits, vol.31, no.8, pp.1091–1099, 1996.

Acknowledgement The authors would like to thank Ikutaro Kobayashi, Eiichi Sano and Yasunobu Ishii for their continual encouragement throughout this work. References [1] H. Ichino, Y. Yamauchi, and T. Nittono, “20 Gbit/s exclusive OR/NOR IC using AlGaAs/GaAs HBTs,” IEE Electron. Lett., vol.27, no.2, pp.180–181, 1991. [2] T. Ihara, Y. Oikawa, T. Yamamoto, H. Tomofuji, H. Hamano, H. Ohnishi, and Y. Watanabe, “InGaP/GaAs HBT-IC chipset for 10-Gbit/s optical receiver,” 1996 GaAs IC Symp. Tech. Digest, pp.262–265, 1996. [3] R. Yu, R. Pierson, P. Zampardi, K. Runge, A. Campana, D. Meeker, K.C. Wang, A. Petersen, and J. Bowers, “Packaged clock recovery integrated circuits for 40 Gbit/s optical communication links,” 1996 GaAs IC Symp. Tech. Digest, pp.129–132, 1996. [4] Z.-G. Wang, M. Berroth, A. Thiede, M. Rieger-Motzer, P. Hofmann, A. H¨ ulsmann, K. K¨ ohler, B. Raynor, and J. Schneider, “40 and 20 Gbit/s monolithic integrated clock recovery using a fully-balanced narrowband regenerative frequency divider with 0.2 µm AlGaAs/GaAs HEMTs,” IEE Electron. Lett., vol.32, no.22, pp.2081–2082, 1996. [5] K. Murata, T. Otsuji, T. Enoki, and Y. Umeda, “Exclusive OR/NOR IC for over 40 Gbit/s optical transmission systems,” IEE Electron. Lett., vol.34, no.8, pp.764–765, 1998. [6] L. Schmidt and H.-M. Rein, “New high-speed bipolar XOR gate with absolutely symmetrical circuit configuration,” IEE Electron. Lett,. vol.26, no.7, pp.430–431, 1990. [7] M. Yoneyama, A. Sano, K. Hagimoto, T. Otsuji, K. Murata, Y. Imai, S. Yamaguchi, T. Enoki, and E. Sano, “Optical repeater circuits design based on InAlAs/InGaAs HEMT digital IC technology,” IEEE Trans. Microwave Theory & Tech., vol.45, no.12, pp.2274–2282, 1997. [8] M. Vadipour, “Capacitive feedback technique for wideband amplifiers,” IEEE J. Solid-State Circuits, vol.28, no.1, pp.90–92, 1993. [9] T. Enoki, Y. Umeda, K. Osafune, H. Ito, and Y. Ishii, “Ultra-high-speed InAlAs/InGaAs HEMT ICs using pnlevel-shift diodes,” Tech. Digest Int’l Electron Device Meet., pp.193–196, 1995. [10] T. Enoki, H. Ito, K. Ikuta, and Y. Ishii, “0.1 µm InAlAs/InGaAs HEMT with an InP-recess-etch stopper grown by MOCVD,” Int’l Conference on Indium Phosphide and related Materials, Conf. Proc. Hokkaido, Japan, pp.81– 88, 1995. [11] T. Otsuji, M. Yoneyama, Y. Imai, S. Yamaguchi, T. Enoki, Y. Umeda, and E. Sano, “46 Gbit/s multiplexer and 40 Gbit/s demultiplexer modules using InAlAs/InGaAs/InP HEMTs,” IEE Electron. Lett., vol.32, no.7, pp.685–686, 1996. [12] Y. Imai, S. Yamaguchi, S. Kimura, and H. Tsunetsugu, “New module structure using flip-chip technology for highspeed optical communication IC’s,” IEEE MTT-S Int. Microwave Symp. Tech. Dig., pp.243–246, 1996. [13] T. Shibata, S. Kimura, H. Kimura, Y. Imai, Y. Umeda, and Y. Akazawa, “A design technique for a 60 GHz-bandwidth distributed baseband amplifier IC module,” IEEE J. SolidState Circuits, vol.29, pp.1537–1544, 1994. [14] M. Nakamura, Y. Imai, S. Yamahata, and Y. Umeda, “Over-30-GHz limiting amplifier IC’s with small phase deviation for optical communication systems,” IEEE J. Solid-

Koichi Murata was born in Osaka, Japan, in 1963. He received the B.S. and M.S. degrees in mechanical engineering from Nagoya University, Nagoya, Japan, in 1987 and 1989, respectively. In 1989 he joined NTT LSI Laboratories, Atsugi, Japan. He is currently a senior research engineer at NTT Optical Network Systems Laboratories, Yokosuka, Japan. He has been engaged in research and development of ultra-high speed digital ICs for optical communication systems. His current research interest includes optoelectronic IC design and high-speed optical transmission systems. Mr. Murata is a member of IEEE.

Taiichi Otsuji was born in Fukuoka, Japan, in 1959. He received the B.S. and M.S. degrees in electronic engineering from Kyushu Institute of Technology, Fukuoka, Japan, in 1982 and 1984, respectively. He received the Ph.D. degree in electronic engineering from Tokyo Institute of Technology, Tokyo, Japan, in 1994. In 1984, he joined the Electrical Communication Laboratories, NTT, Japan, where he engaged in the research and development of high-speed LSI test systems. He is currently a senior research engineer, supervisor at Optical Network Systems Laboratories, NTT, Japan. His current research interest includes ultra-broardband electronic IC design and ultrafast optoelectronic measurement technologies. He is a recipient of the Outstanding Paper Award of the 1997 IEEE GaAs IC Symposium. Dr. Otsuji is a member of IEEE, and OSA.

Takatomo Enoki was born in Tottori, Japan, on November 19, 1959. He received the B.S. and M.S. degrees in physics and the Ph.D. degree in electronic and electrical engineering from the Tokyo Institute of Technology, Tokyo, Japan, in 1982, 1984, and 1996, respectively. He joined the Atsugi Electrical Communications Laboratories of NTT, Kanagawa, Japan, in 1984. Since then, he had been engaged in research and development work on fabrication technologies for high-frequency and high-speed GaAs MESFET’s and IC’s. Since 1989, he has studied and developed ultra-high speed and low noise heterojunction FETs and their ICs on an InP substrate. He is currently a Senior Manager in Research Planning Department of the NTT System Electronics Laboratories. Dr. Enoki is a member of the Institute of Electrical and Electronics Engineers and the Japan Society of Applied Physics.

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Yohtaro Umeda was born in Kanagawa, Japan on September 1, 1957. He received the B.S. and M.S. degrees in physics from the University of Tokyo, Tokyo, Japan in 1982 and 1984, respectively. In 1984 he joined Nippon Telegraph and Telephone Corporation. He is currently with NTT System Electronics Laboratories, Kanagawa, Japan, engaged in the study on microwave characteristics of HEMTs on InP and its application to monolithic millimeter-wave ICs and ultrahigh-speed digital ICs. Mr. Umeda is a member of the Institute of Electrical and Electronics Engineers (IEEE).

Mikio Yoneyama was born in Nagano, Japan, on September 28, 1965. He received the B.S. and M.S. degrees in instrumentation engineering from Keio University, Yokohama, Japan, in 1988 and 1990, respectively. In 1990, he joined the NTT LSI Laboratories in Atsugi, Japan. He had been engaged in research and development on broadband electronic and optoelectronic IC design. In 1996, he joined the NTT Optical Network Systems Laboratories in Yokosuka, Japan. He is currently engaged in developement on optical repeater circuit for future optical fiber communication systems.