Safe operation region characterization for quantifying the reliability of

Safe Operation Region Characterization for Quantifying the Reliability of CMOS Logic Affected by Process Variations Usman Khalid, Antonio Mastrandrea, Mauro Olivieri

Department of Information, Electronics and Telecommunication Engineering Sapienza University of Rome, Italy {khalidu, mastrandrea, olivieri}@diet.uniroma1.it Abstract— Technology parameter variations combined with voltage noise can become a major cause of logic errors in digital circuits. This presentation brings in the idea of “safe operation region” to permit a robust analytical Monte Carlo evaluation of the reliability of logic circuits in a given technology, avoiding timeconsuming SPICE-level or device-level Monte Carlo simulations. The application of the approach is demonstrated for the case of a 22 nm bulk CMOS process. Keywords— Failure probability, input-signal variation, process variations, , nano-CMOS circuits.

I.

INTRODUCTION

Stochastic deviations in device process parameters have increased the matter of variability in digital circuits’ speed and leakage power, on which extensive research have already been conducted in recent years [1-4]. The reliable logic operation issues increases with deep submicron CMOS technologies, this concludes that the random fluctuation of noisy logic errors in the digital circuit’s output – generally minimal – can be tremendously raised by process variations [4-8]. The immense numbers of device or circuit level iterative Monte Carlo simulations of the required circuit should be executed, in terms of estimating the output error probability, as an input of standard deviations by using compact models. There is a huge number of iterative simulations are required in order to capture the realistic probability values, therefore such techniques are infeasible in terms of extensive time consumption. This research paper demonstrates an approach for analyzing the failure probability of CMOS logic in a given technology by using safe operation regions’ Monte Carlo analysis. As for other technology-related performance parameters, such as minimum propagation delay and energy-delay product, the reference circuit for analyzing the reliability associated to a given technology is the basic inverter logic gate [9]. The application of the proposed approach is demonstrated for the case of an inverter gate in 22 nm bulk-CMOS technology, subject to variations on effective length Leff, effective width Weff, oxide thickness Tox and doping concentration Ndep, for different values of standard deviations of the parameters. II.

BACKGROUND DEFINITIONS

It is generally agreed that a logic circuit operates fallaciously when its output voltage does not equate to the input logic values and by the logic value determined by the function 978-1-4799-4994-6/14/$31.00 ©2014 IEEE

it implements. Let’s take the case study of the inverter cells, the conventional definition of valid output voltage is shown in Fig. 1. Generally in all CMOS technologies, the output high logic of inverter A is representing VGND as corresponding nominal voltage VoutA, whereas VDD is the case for logic low output. The voltage shifts from its nominal value if malfunctioning occurs which may induce the erroneous logic value to inverter B. The threshold voltages for correct logic value representation VIH and VIL in inverter B are specified as the points where the gain of voltage slope of the voltage transfer characteristics (VTC) of the inverter cell is equivalent to negative one. The values of VIH and VIL are widely described in data sheets of standard cells. Thus, the value of logic input of inverter B, i.e. VoutA, is not valid when it falls within VIL and VIH threshold values [9]. INV_A

INV_B

VoutA

VoutB

VoutB

VIL

VIH

VoutA

Fig. 1. Top: Two inverter cells. Bottom: Logic thresholds. Grey area denotes invalid VoutA logic value.

III.

METHODOLOGY IMPLEMENTATION

The logic thresholds in 22 nm metal gate/high-k bulk CMOS technology [9][10] are computed by direct SPICE simulations of the VTC with titular values, getting high noise margin value VIH at 0.64 V and low noise margin value VIL at 0.33 V with 1 V supply. The following simulation setup for right operation analysis is represented in Fig. 2. The ideal values of VGND or VDD could

forcefully turns-on the pull-down or pull-up device by the varying input voltage when it is supposed to be turned-off. This phenomenon finally deteriorating the literal output voltage provided the large enough variation on input signal. Such faulty output is also deteriorated by process-induced fluctuations of the P-type and N-type device threshold voltages from their titular values. The joint effect of noise-induced input voltage variation and process-induced threshold voltage fluctuations can be thoroughly characterized by SPICE simulation by driving predetermined deviations, and guiding to a plot of the output voltage as a function of the literal fluctuations. Fig. 3 represents the case of threshold voltage V𝑇𝑇𝑇𝑇 only variations, taking V𝑇𝑇𝑇𝑇 fixed at the titular value, and input voltage V𝐼𝐼𝐼𝐼 variation, in the target technology, for high and low anticipated output logic value. One can form a similar diagram between V𝑇𝑇𝑇𝑇 and V𝐼𝐼𝐼𝐼 by fixing V𝑇𝑇𝑇𝑇 value as well. Vdd

Vtp

Vin Vout Fig. 3. Fluctuations between VTHP versus VIN. Top: VIN High; Bottom: VIN Low.

Vtn

Vout

1 0,8 0,6 0,4

HL Input transition

0,2 0 0

3E-11 6E-11 Time (ps)

9E-11

1 0,8 LH Input transition

0,6 0,4

Vout

0,2 0 0

4E-11 8E-11 Time (ps)

1,2E-10

Fig. 2. Top: Simulated circuit; Bottom: Output voltages for selected VTHP variations for HL and LH inputs respectively.

We can set up a diagram by finding the intersections of the V𝑂𝑂𝑂𝑂𝑂𝑂 versus V𝑇𝑇𝑇𝑇 and V𝐼𝐼𝐼𝐼 with boundaries VIL and VIH voltages, where the curves 𝑉𝑉𝑇𝑇𝑇𝑇 = G(𝑉𝑉𝐼𝐼𝐼𝐼 ) specifies the boundary for safe operation region when V𝑇𝑇𝑇𝑇 is nominal. To take into account also V𝑇𝑇𝑇𝑇 variations, various G(𝑉𝑉𝐼𝐼𝐼𝐼 ) curves can be produced for low and high V𝐼𝐼𝐼𝐼 according to the matching V𝑇𝑇𝑇𝑇 values, and correspondingly we can characterize the boundary for safe operation region as a function 𝑉𝑉𝑇𝑇𝑇𝑇 = G(𝑉𝑉𝐼𝐼𝐼𝐼 , 𝑉𝑉𝑇𝑇𝑇𝑇 ). Hence, Fig. 4 illustrates the combined variation of 𝑉𝑉𝑇𝑇𝑇𝑇 , 𝑉𝑉𝑇𝑇𝑇𝑇 and 𝑉𝑉𝐼𝐼𝐼𝐼 which leads to a 3-D safe operation region. Now, having characterized the values of G(V𝐼𝐼𝐼𝐼 , V𝑇𝑇𝑇𝑇 ) for the range of interest of V𝐼𝐼𝐼𝐼 , V𝑇𝑇𝑇𝑇 (we targeted a 6-sigma range of variation around the nominal values), we can generate a sufficiently large set of pseudo-random numbers of 𝑉𝑉𝑇𝑇𝑇𝑇 , 𝑉𝑉𝑇𝑇𝑇𝑇 and 𝑉𝑉𝐼𝐼𝐼𝐼 and execute a Monte Carlo computation of the circuit’s probability operation in order to fall the samples up or down of the safe operation region.

The threshold voltage values in P-type and N-type MOSFET devices are evaluated with extensive detail in the BSIM4 compact model as a heuristic parameters and mathematical function of technology by using 𝑉𝑉𝑇𝑇𝑇𝑇 equation declared in [11] and also has been used in [12] for BSIM and PD-SOI models’ threshold voltage comparison analysis. Ultimately, it is likely to produce a haphazardly big vector of 𝑉𝑉𝑇𝑇𝑇𝑇 and 𝑉𝑉𝑇𝑇𝑇𝑇 numbers as an input of process parameters variations. The selected process parameters and their corresponding nominal values are briefly described in the result section.

RESULTS

Without loss of generality we limited the analysis on the variations of oxide thickness Tox, channel doping Ndep, effective length Leff and effective width Weff. In the target 22 nm technology model, the nominal (i.e. mean) values are shown in Table I. We considered a Normal distribution of the selected process parameters. TABLE I. NOMINAL VALUE OF ANALYZED PROCESS PARAMETERS IN THE TARGET 22 NM TECHNOLOGY

1

Vthp

IV.

Safe Operation Region

0

-1 -0.1

Tox Ndep Leff Weff PMOS 6.7·10-10 4.4·1018 1.93·10-8 1.20·10-8 NMOS 6.5·10-10 1.2·1019 1.93·10-8 1.20·10-8

-0.5

0.1

0

Vin (Low Value) 0.3

The resulting speedup of the proposed approach over SPICE in computation run time was always above 104. Accuracy results are shown in Table II, along with diverse standard deviation values assumed for process parameter (L, W, Tox, and Ndep) referring to both high and low logic level for 𝑉𝑉𝐼𝐼𝐼𝐼 . The relative error between the proposed approach and SPICE Monte Carlo simulation is below 17% relative error for high 𝑉𝑉IN and below 5% relative error for low 𝑉𝑉𝐼𝐼𝐼𝐼 respectively, on the calculated failure probabilities. Note that for the purpose of evaluating the general reliability of a given technology in certain noise condition, even predicting the correct order of magnitude of the failure probability would be significant. Table III shows another set of results for the same standard deviations of process parameters, but with four different standard deviation values for voltage input voltage noise, namely σ𝑉𝑉𝐼𝐼𝐼𝐼 = 0.15, 0.20, 0.25 and 0.30. The results show the increased probability of failure according to both process parameters and input higher standard deviation values.

0.5

1.5

2 1 0

Vthp

A subset of the configurations was used as a verification test set, for which the proposed calculation approach was verified versus SPICE level Monte Carlo simulations assuming the same technology parameter variations. For the verification purposes, we fixed input voltage standard deviation at σ𝑉𝑉𝐼𝐼𝐼𝐼 = 0.25 V, a rather large value, in order to have SPICE Monte Carlo simulation results significant in a relatively low number of simulation iterations. We performed 106 Monte Carlo iterations, enough to obtain convergence of the resulting probability of failure to a stable value.

0.5

Vthn

1

-1

-2 1.1

Safe Operation Region

0.9

Vin 0.7 (High Value)

0.5

1.5

1

0.5

High Vin Low Vin

σ Ndep σ Leff

σ Weff

15·10-12 20·10-12 25·10-12 30·10-12 15·10-12 20·10-12 25·10-12 30·10-12

20·1016 25·1016 30·1016 15·1016 20·1016 25·1016 30·1016 15·1016

30·10-10 15·10-10 20·10-10 25·10-10 30·10-10 15·10-10 20·10-10 25·10-10

25·10-10 30·10-10 15·10-10 20·10-10 25·10-10 30·10-10 15·10-10 20·10-10

-0.5

Vthn

Fig. 4. 3-D Safe operation regions in 22 nm CMOS inverter cell, Top: Low VIN; Bottom: High VIN.

We furthermore explored a total of 256 experiments resulting from 4 process parameters, 4 standard deviation values and 4 input voltage standard deviation values. The experiments addressed the analysis of the dependency of failure probability on the different process parameters. The results identified oxide thickness Tox as the most critical parameter for variations, having the highest relative effect on the failure probability for lowest values of input noise standard deviation. The detail of the impact of Tox standard deviation on the probability of failure is reported in Fig. 5, for 0.15 V input noise standard deviation.

TABLE II. FAILURE PROBABILITY COMPARISON BETWEEN PROPOSED APPROACH AND SPICE MONTE CARLO SIMULATIONS σ Tox

0

Safe Operation Region SPICE level Monte Carlo Monte Carlo 3.10·10-2 3.41·10-2 -2 3.14·10 3.49·10-2 -2 3.30·10 3.85·10-2 -2 3.37·10 3.99·10-2 3.18·10-2 3.24·10-2 -2 3.20·10 3.31·10-2 -2 3.34·10 3.37·10-2 -2 3.39·10 3.54·10-2

Relative Error - 09.09 % - 10.02 % - 14.28 % - 15.53 % - 01.85 % - 03.32 % - 00.89 % - 04.23 %

TABLE III. FAILURE PROBABILITY RESULTS FOR SELECTED CASES OF PROCESS PARAMETERS’ STANDARD DEVIATION VALUES WITH INPUT VOLTAGE NOISE HIGH 𝑉𝑉𝐼𝐼𝐼𝐼 σ Tox 15·10-12 15·10-12 15·10-12 15·10-12 20·10-12 20·10-12 20·10-12 20·10-12 25·10-12 25·10-12 25·10-12 25·10-12 30·10-12 30·10-12 30·10-12 30·10-12

3.00E-03 2.50E-03

σ Ndep 20·1016 20·1016 25·1016 30·1016 15·1016 20·1016 25·1016 30·1016 15·1016 15·1016 25·1016 30·1016 15·1016 20·1016 25·1016 30·1016

σ Leff 15·10-10 25·10-10 20·10-10 20·10-10 15·10-10 25·10-10 20·10-10 30·10-10 15·10-10 25·10-10 25·10-10 30·10-10 20·10-10 25·10-10 20·10-10 30·10-10

σ Weff σ Vin=0.15 25·10-10 1.170·10-2 30·10-10 1.170·10-2 15·10-10 1.170·10-2 20·10-10 1.170·10-2 25·10-10 1.470·10-2 30·10-10 1.470·10-2 15·10-10 1.470·10-2 25·10-10 1.460·10-2 25·10-10 1.630·10-2 30·10-10 1.630·10-2 25·10-10 1.640·10-2 25·10-10 1.640·10-2 25·10-10 2.020·10-2 30·10-10 2.010·10-2 15·10-10 2.010·10-2 30·10-10 2.000·10-2

σ Vin=0.20 σ Vin=0.25 9.950·10-2 3.107·10-2 9.960·10-2 3.101·10-2 9.940·10-2 3.106·10-2 9.960·10-2 3.107·10-2 1.103·10-2 3.146·10-2 1.101·10-2 3.146·10-2 1.102·10-2 3.148·10-2 1.100·10-2 3.146·10-2 1.166·10-2 3.307·10-2 1.165·10-2 3.307·10-2 1.165·10-2 3.308·10-2 1.165·10-2 3.306·10-2 1.267·10-2 3.377·10-2 1.268·10-2 3.376·10-2 1.269·10-2 3.378·10-2 1.267·10-2 3.375·10-2

σ Vin=0.30 6.032·10-2 6.033·10-2 6.030·10-2 6.024·10-2 6.125·10-2 6.126·10-2 6.125·10-2 6.121·10-2 6.225·10-2 6.224·10-2 6.221·10-2 6.221·10-2 6.249·10-2 6.244·10-2 6.246·10-2 6.241·10-2

REFERENCES P{failure}

[1]

2.00E-03 1.50E-03 1.00E-03 5.00E-04

σ Tox

0.00E+00

Fig. 5. Detail of the dependency of the probability of failure from Tox standard deviation, for noise standard deviation σVin = 0.15 V.

V.

CONCLUSIONS

The characterization of safe operation regions has been introduced, to analyze the behavior of the probability of failure in logic circuits fabricated in nano-CMOS technologies, resulting from noise-induced voltage variations and processinduced device parameter fluctuations. A wide range of verification of the safe operation region approach versus SPICE Monte Carlo simulations has been conducted. An exploration of the impact of different parameter variations on logic level reliability has identified Tox as the most critical device parameter for variations. The approach shows >104 speedup with respect to SPICE Monte Carlo analysis and therefore can be the baseline for efficiently characterizing the expected reliability of digital nano-CMOS processes, as functions of process parameter variability and voltage noise. Further research is addressing the extension of the approach to the evaluation of failure probabilities in specific circuits composed of multiple standard cells including memory elements.

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