SAGE: A Toolsuite for Rapid Application Development in High Performance Computing Environments
Minesh I. Patel, Ph.D., Matthew C. Clark, Ph.D. and Hoyt M. Layson, Jr. Honeywell Space Systems; Commercial System Operations Clearwater, Florida mpatel, mclark,
[email protected] Patel
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SAGE™ Framework to Capture HW/SW Knowledge Supporting System Application Developers
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Application Software
Hardware Environment
Run-Time Environment
Lower Cost Integrated Application/System Solutions 2
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Problems with Large Distributed or Parallel Computing Systems • Optimizing performance on a particular board requires intimate knowledge of architecture. • Bundled software libraries have significant learning curve. • Previously, most applications had limited portability across platforms and re-use. • Tool support by vendors is limited to their own hardware. • Problem is compounded when considering multiple boards/boxes or, worse, heterogeneous systems.
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SAGE™ Solutions for Large Distributed or Parallel Computing Systems • SAGE™ captures intimate knowledge of board architecture. • SAGE™ captures knowledge of bundled software libraries reducing application developer’s learning curve. • SAGE™ automates portability across platforms and supports software re-use. • SAGE™ supports multiple vendor hardware and device drivers. • SAGE™ supports heterogeneous vendor hardware and run-time environments across multiple boards and boxes. SAGE™ is the next generation software development tool that encompasses the entire system of hardware, runtime environment and application software. Patel
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Systems and Applications Genesis Environment (SAGETM) SAGE™ is a toolsuite that “Captures the Knowledge” of the hardware environment and run-time software. Application development is supported in Less Time, at Lower Cost and with Reduced Complexity.
• Unified graphical interface - user need only learn system functionality once. • Complexity Management - keeps application engineers at the “application level.” • Ability to partition/map software functions and data objects to and across multiple processor/boards/boxes. • Supports rapid prototyping and experimentation with different hardware/ software partitions & parallelization mappings to optimize design. • Provides instrumentation for target implementations. • Evolves to follow evolving COTS market trends and developments. Patel 5
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SAGETM
Requirements
Automates System Development
Software, Hardware Arch Capture • Integrated SW/HW architecture capture, parallel design, and code generation
Requirements
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Architecture Trades, Optimization
VHDL System & Architecture Simulation
Optimization Parameters, Visualization
Dynamic Dynamic System System Optimization Optimization and and Simulation Simulation
Design
• System architecture optimization: size, weight, power, cost. hw/sw partitioning, sw partitioning/allocation • System simulation
Implementation
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Hardware/ Software Performance Measurement • Hardware /Software performance validation and instrumentation, on-line diagnostics of target system
Integration/Validation
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SAGETM Software Development Environment Components
• SAGETM Designer Visual Design Tool • Specification of application characteristics • Knowledge capture of HW and SW components, auto code generation • Architecture Trade Optimization Tool (ATOT) • Partitioning and mapping of application functions • Trade-off architectures for size/weight/power/cost factors • Performance Modeling and Simulation (PML) • Automated synthesis of simulation model of complete HW architecture, run-time SW layers, and application functions • VHDL-based HW/SW co-design • SAGETM Visualizer • Real time instrumentation and visualization
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SAGETM Components
Released In Pre-Beta
Designer DSP Control Visualizer SAGE™ Today
Auto Partition
Architecture Trade
Modeler
1999 SAGE™ Product Release Road Map 2000 Designer Designer DSP Control Control Visualizer
Designer Designer DSP Control Control
Designer DSP Control Control
Auto Partition
Architecture Trade
Designer DSP Control Control Modeler
SAGE™ Will Integrate DSP and Control Domains
A Common User Interface for All Tools Patel
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SAGE™ Designer Software Shelf
• Allows software knowledge (e.g. libraries, device drivers, kernals and run-times) to be captured once and stored on the software shelf for (re)use. • More complex software modules may be built from existing objects and placed onto the software shelf. • Legacy application software can be placed on the shelf • User defined code/modules may also be captured onto the shelf. • COTS Board vendor libraries can be placed on the shelf. • Supports building block approach of Patel validated software modules. 9
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SAGE™ Designer Hardware Shelf
• Allows hardware knowledge to be “captured” once and stored on the shelf for (re)use. • Simpler components can be combined to create more complex architectures, both COTS and non-COTS. • Users may define their own architectures with the Hardware Editor and place them on the shelf. Patel
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SAGE™ Designer Application Data Type Editor
• The Data Type Editor describes multiple dimensions of data and striping properties in each dimension. • Data striping and iteration in all dimensions is automatically inferred. Patel
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SAGE™ Designer Hardware Editor • Capture hardware design: • Component level • Board level • Box level • Network level • Integrate components into composites • Supports major hardware resource types: • Processors • CPUs • DSPs • Memory • Busses • Backplanes Patel
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SAGE™ Designer Application Editor • Applications are built on the Application Editor by selecting functions from the software shelf, defining their port data types, and linking them together. • Standard operations, select, cut, copy, paste, drag & drop allow easy configuration. • Parallelism is inferred automatically from the data type assigned to the function’s ports. Patel
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Mapping Software Functions to Processors, Generating Glue-Code and Load Modules • Functions may be mapped to target hardware or to the host processor . • Once all functions are mapped, “glue code” may be generated and compiled into an executable to support inter-task, inter-processor, inter-board and inter-box communications.
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TM SAGE SAGETMDesign DesignTool ToolConcept Concept Software Architecture
f1
f2
Hardware Architecture
DSPs f3
latency = 10ms
f4
Design Tool
HW/SW Connectivity Tables
VME
Glue Code
Distributed Run Time f4
f2
f1
Heterogeneous Networked System
f3
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SAGETM Design Tool Views Application Development
Tool Customization to Domain & Platform
Software Engineer’s View f1
Data Schema
f2
latency = 10ms
Tool Developers’ View
f3
f4
Software Design Builder
Mapping DSPs
Hardware Design Builder
Backend Editor Software Shelf
Function Editor
Glue-Code
Code Generator
Connectivity Tables (hw (hw//sw) sw) Hardware Shelf
Hardware Component Editor
VME
System Engineer’s View
Legacy Model Data Capture Interfaces Library Capture
Hardware Data Book Capture
Honeywell Domain Modeling Environment (DoME) SmallTalk VisualWorks
Tool developers put software and hardware objects on the shelf that are then selected by the application developers to build system applications. Patel
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SAGETM Visualizer CPU/Bus Optimization Graph
Fraction Of Full Load
1.4
1.2
1
0.8
0.6
InterNode Bus Ld
0.4
PCI Bus Ld 0.2
Schedulability CPUMemLD
0 0
1
2
3
CPU / Bus
CPUPerLD 4
5
6
7
Monitor System Resource Utilization Patel
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SAGETM Trade Off Tree Requirements
Min (Cost, Risk)+Max(Perf, StratFac)
Optimized design Candidates
Architecture Trades Network Efficiency
Performance Density
Life Cycle Cost
Size
Hardware Dev.
Weight
Hardware Rec.
Power
Software Dev.
• All Attributes are weighted by user (given relative importance)
Software Maint.
Risk Technology Maturity (probability of availability) New Design Usage
Constraints Time to reconfigure Latency
Strategic Factors Evolvability Reliability Scalability
Number of Drops
Unit Cost
Architecture trades considers quantified factors to find the “Best” Architecture Patel
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How SAGETM Benefits Application Developers • • • • •
Reduction in system integration cost and schedule Porting legacy systems to COTS environments Performing system studies and architecture trades Performance modeling and simulation Partitioning and mapping across multiple processors/boards/boxes • Parallelizing applications • Instrumentation of target implementations • Multiple hardware and run-time support for application developers. Patel
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