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Self-Driven Synchronous Rectification System With Input Voltage Tracking for Converters With a Symmetrically Driven Transformer Arturo Fernández, Member, IEEE, Diego G. Lamar, Member, IEEE, Miguel Rodríguez, Student Member, IEEE, Marta M. Hernando, Member, IEEE, Javier Sebastián, Member, IEEE, and Manuel Arias, Student Member, IEEE
Abstract—Synchronous rectification (SR) is mandatory to achieve good efficiencies with low output voltages. If a transformer is driven asymmetrically without dead times, the self-driven SR (SDSR) is a very interesting solution. However, if the transformer is driven symmetrically, the synchronous rectifiers are off during the dead times, and as a consequence, the efficiency is lowered. This paper deals with the optimization of an SDSR system that keeps the rectifiers on even during the dead times. The input voltage is tracked, and the information is used to adapt the gate to the source voltage of the synchronous rectifiers and improve the efficiency. The system has been implemented in a prototype, and the results have been compared with the ones obtained in the same prototype without SDSR. Index Terms—Self-driven, synchronous rectification (SR).
I. I NTRODUCTION
S
YNCHRONOUS rectification (SR) is mandatory to achieve good efficiencies in low output voltage converters [1]–[7]. Nowadays, the most widely used topology for this application is the synchronous buck converter or voltage-regulator module [8]. It is a very simple topology; the dynamic response is very fast, and it has no transformer. However, if the input voltage is high, the duty cycle will be quite narrow, and the performance of the converter will not be so good [9], [10]. At medium power levels, the half-bridge and the push–pull converters are very popular when galvanic isolation is needed. They are inherently efficient topologies because of the symmetric excitation of the transformer. The output filter operates at twice the switching frequency, and hence, the size of the passive components is relatively small. The output stage is usually built with diodes because, during the dead times on the transformer, the voltage across it is zero and, hence, SR is not very efficient. Apart from the current doubler rectifier output [11], [12], some recently proposed methods [13], [14] overcome this problem by keeping the synchronous rectifiers on even during the dead times. As a consequence, the half-bridge converter can also be used for low output voltage applications with a very high efficiency. This paper shows an optimization of a previously proposed self-driven SR (SDSR)
Fig. 1. (a) Scheme of the proposed SDSR system. (b) Gate-to-source voltages in the SR with the proposed system. (c) VGSon1 and VGSoff values as a function of the input voltage.
system [14]. The idea is to change the gate-to-source voltage of the synchronous rectifiers when the input voltage changes to achieve a better efficiency. To verify the system, a 12-V–250-W prototype with the European input voltage range (190–250 V) has been built and tested. As it will be shown, the SDSR system increases the efficiency of this prototype up to two points. II. R EVIEW OF THE P ROPOSED SDSR S YSTEM
Manuscript received January 11, 2008; revised July 10, 2008. First published January 19, 2009; current version published April 29, 2009. The authors are with the Department of Electrical Engineering, Universidad de Oviedo, 33204 Gijón, Spain (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2009.2012455
The basic idea of the system [14] is to extend the conduction period of the MOSFETs also to the dead times. This way, the body diode of the transistors will not conduct at any time, and the losses are minimized. To achieve this, a voltage source VA is added, as shown in Fig. 1(a). Thus, the voltage waveforms
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FERNÁNDEZ et al.: SDSR SYSTEM WITH INPUT VOLTAGE TRACKING FOR CONVERTERS WITH A TRANSFORMER
Fig. 2.
Proposed method to obtain the voltage VA .
at the gate of the MOSFETs will be as shown in Fig. 1(b). As can be seen, while the voltage across the transformer is zero, the gate voltage of the MOSFETs is VA instead of zero, as in the conventional approach. Then, the MOSFET will be always on, and the body diode will not conduct. The voltage source VA does not deliver any power in steady state because the average value of the current passing through the gate is zero. III. T HEORETICAL O PTIMIZATION OF THE SDSR S YSTEM The implementation of VA is very simple because a regulated voltage can be obtained from the output filter inductor or from an additional winding of the transformer. Fig. 2 shows a possible implementation of VA using the output inductor. As can be seen, an additional output is connected to a winding placed on the output filter inductor. The voltage VA will be controlled by cross-regulation. Although the regulation accuracy of the VA voltage is not very important, it can be tightly regulated by means of a tiny linear regulator, as shown in Fig. 2. It should be mentioned that this regulator can be a very small one because the average current passing through it is also extremely low (ideally zero). In the conventional approach, the voltage VA will be the same in any operating condition. Then, the peak gate voltage (VGSon1 ) will depend on the input voltage VGSon1 = VA +
VCB 2nA
(1)
where VCB is the voltage across the bulk capacitor (the input voltage of the dc/dc cell) and nA represents the turns ratio of the auxiliary winding. While there are 0 V across the transformer, the gate voltage is VGSon2 = VA .
(2)
During the off time, the voltage across the gate is VGSoff = VA −
VCB . 2nA
(3)
If VA is constant and assuming a maximum gate voltage of 20 V and a minimum gate voltage of 5 V (i.e., VA = 5 V), the following is obtained from (1)–(3): VCB_MAX VCB_MIN ≤ nA ≤ 30 10
(4)
where VCB_MAX and VCB_MIN are the maximum and minimum voltages across the bulk capacitor, respectively. In addition, the maximum possible variation of the input voltage, compatible with the previously proposed SDSR, can also be
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obtained from (4). In practice, a 4.7 : 1 input voltage range is achievable with a gate threshold voltage of 3.5 V. With a threshold voltage of 5 V and setting nA = 12, the turn-on voltage at 90 V is 10 V, while the turn-off voltage is 0 V. Fig. 1(c) shows VGSon1 and VGSoff as a function of the input voltage. As can be seen, the turn-off voltage is more and more negative when the input voltage increases. Note that the peak value of the gate voltage during the on time VGSon1 also increases with increasing input voltage. The behavior of the gate voltage can be improved if the voltage VA can be adapted according to the variation on any chosen parameter, for example, the input voltage. This is very easy to achieve by building a linear regulator, such as the one shown in Fig. 3(a), where the reference voltage Vref (and, therefore VA ) is properly changed. In fact, making VA change with the input voltage implies several advantages for this SDSR system. With a regulated system, the turn-off voltage could be 0 V for any operating condition. From (3), this can be achieved making VA = VCB /2nA . Thus, the gate capacitor will not be charged to a negative voltage, and hence, charging losses can be reduced. This option also maximizes the VGS voltage. Thus, the transistor will have a lower on resistance, and as a consequence, conduction losses will be lower. Moreover, when the input voltage is higher, the duty cycle is smaller, and hence, the VA voltage is more significant because the transformer has 0 V during a longer period of time. Note that the rDSON of the MOSFET used changes from 12.5 mΩ when VGS = 5.5 V to 7 mΩ when VGS = 12 V. Hence, conduction losses will be proportional to VGS . On the other hand, a very high VGS will also increase the gate charge and, hence, gate losses. Moreover, the rest of the switching losses (due to a voltage–current overlap) must be added on top of these two. In the end, the impact of the improvement will depend on the relative weight of each of them, which depends on the MOSFET used. This VA voltage control can be achieved by many different ways. Fig. 3 shows two possible options to regulate VA as the input voltage change. The circuit shown in Fig. 3(b) needs an optocoupler to give the operational amplifier (OA) the information of the input voltage. It should be noted that even the information about the ripple on the bulk capacitor is transferred to the OA reference, and hence, the voltage VA is perfectly adapted to the real input conditions. Fig. 4 shows the voltage VA when the input voltage is [Fig. 4(a)] 190 and [Fig. 4(b)] 250 V. As can be seen, the low-frequency ripple of the input bulk capacitor is also observed on VA . Fig. 4(c) and (d) shows the gateto-source voltage of the synchronous rectifiers when the input voltage is 190 and 250 V, respectively. As can be seen, the turn-off voltage is zero in both cases, while the maximum gate voltage changes. When the input voltage is 190 V, VA is equal to 5 V, and when the input voltage is 250 V, VA is equal to 8 V. A weak point of this system is the temperature dependence of the optocoupler. Moreover, the current transfer ratio of these devices is also quite variable. Hence, the voltage reference would be difficult to adjust in a real manufacturing process. Another option is shown in Fig. 3(c). In this case, no optocoupler is needed, and the information of the input voltage is obtained from the transformer. It should be noted that the voltage across the winding, while one of the input MOSFETs
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Fig. 3. (a) Linear regulator built with a transistor and an OA. (b) System to obtain the reference by means of an optocoupler. (c) System without optocoupler.
Fig. 4. (a) VA voltage when the input voltage is 190 V. (b) VA voltage when the input voltage is 250 V. (c) VGS voltage when the input voltage is 190 V. (d) VGS voltage when the input voltage is 250 V.
is on (Vwinding ), is VCB /2nA , and therefore, it depends on the input voltage. Thus, a peak detector can be connected to the gate of one of the synchronous rectifiers in order to obtain information about the input voltage. The additional surface needed to place all the extra components is around 1 cm2 when surface mount device technology is used. Hence, the impact on the power-supply power density will be very low. Then, the reference of the OA that controls the voltage VA can be changed by the input voltage. As was explained before, if the reference is set to be half the maximum gate voltage, the turn-off voltage would be zero for any operating condition. The capacitor used for the peak detector should be the smallest possible to avoid dynamic problems. Thus, the dynamic response of the peak detector should be at least as fast as the dynamic behavior of VCB to avoid problems during the transient response. However, this is not difficult because the input capacitor is generally designed to comply with the holdup time specifications, and hence, its transient response will be slower than the one of the peak detector, which operates at the switching frequency. Note that, if the converter is operating in the upper limit of the input voltage, VA will have a large value. If there is a sudden change on the input voltage and it decreases, the voltage VA should also decrease to avoid having a positive voltage during turn-off. If this happened, both MOSFETs will be on at the same time, and the transformer will be shortcircuited. If the input voltage changes from low to high, this problem does not exist.
Fig. 5. Gate-to-source voltage on a synchronous rectifier during an input voltage transient. View of the whole transient and detailed view of the beginning and the end of the transient.
Fig. 5 shows the gate-to-source voltage of one of the synchronous rectifiers during an input voltage transient. In this paper, the input voltage suddenly changed from 230 to 180 V. Fig. 5 shows the whole transient (which is very slow due to the input bulk capacitor) and the detailed views of the beginning and the end of the transient. As can be seen, when the MOSFET should be off, the gate voltage is always slightly negative. Hence, no cross-conduction problems exist.
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Fig. 6. (a) Gate-to-source voltage programmed to turn the MOSFET off with 0 V. (b) Detail of the turn-off process. (c) Gate-to-source voltage programmed to turn the MOSFET off with a negative voltage. (d) Detail of the turn-off process.
Regarding the dynamic response of the circuit during a load transient, the proposed SDSR system does not have any dynamic drawback in comparison with the conventional SDSR system. If the input voltage is constant, VA should not be changed at all. Hence, a load transient will only have some impact on the duty cycle as in a conventional converter. As far as the duty-cycle information is transmitted by the transformer, there are no additional energy storage components involved in the process. As a consequence, the dynamic response will depend on the transfer functions of the converter and the regulator.
IV. P RACTICAL O PTIMIZATION OF THE SDSR S YSTEM As has been mentioned, the proposed method has been implemented on a power-supply prototype with the European input voltage range (190–250 V), 12-V output, and 250 W. To achieve the best possible efficiency, both conduction and switching losses should be minimized on the SRs. As was explained before, it is worth maximizing VGS to reduce conduction losses. Regarding switching losses, one of the key issues is the transformer leakage inductance. As in any SR system, it is very important to minimize it in order to avoid resonances on the waveforms. These resonances can turn on and off both SRs at wrong moments, and hence, the crossconduction will make way for short circuits that will lower the efficiency considerably. Fig. 6(a) shows the VGS of one MOSFET when the VA voltage source is programmed to be VGS /2. As can be seen, there are small resonances during the turn-off of both transistors. Fig. 6(b) shows a detailed view of the gate voltage during the turn-off process. The peak voltage of the resonance is slightly higher than 2.5 V, which is enough to turn the MOSFET on. As a consequence, there will be a short circuit between both SRs, and the efficiency will decrease. This can be avoided by different ways. One possibility is to have a very tightly coupled transformer (e.g., a planar transformer) in order to reduce the resonance as much as possible. The other possibility is to turn the MOSFET off with a slightly negative voltage, e.g., −2 V. Thus, the resonance should be much higher to turn on the transistor. Hence, this
Fig. 7. Efficiency of the prototype for different VA voltages.
method enables the use of conventional transformers (as in the prototype) instead of planar transformers. This is very interesting because, in some other SDSR topologies, the use of a planar transformer is absolutely mandatory to achieve a good performance. Fig. 6(c) shows the gate-to-source voltage of the synchronous rectifiers with a lower VA voltage. As can be seen, the turn-off voltage is slightly negative. Fig. 6(d) shows the detail of the turn-off. In this case, although there is a resonance, the peak voltage is lower than the threshold voltage, and hence, the MOSFET does not turn on again. Fig. 7 shows the efficiency measured in both cases. 1) VA = 8 V, and the turn-off voltage = 0 V. 2) VA = 5 V, and the turn-off voltage = −2 V. As can be seen, the efficiency is about two points higher when the resonance is avoided. The gate voltage was changed systematically in order to find the best configuration. The outcome is that the best result is obtained with the highest voltage that prevents the resonance on VGS from turning on the SR. To verify the improvement due to the SDSR system, the efficiency was also measured using diodes on the output stage and also using self-driven MOSFETs but without the voltage source system and without a diode in parallel (the body diode conducts during the dead times). The results are shown in Fig. 8(a),
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Fig. 8. (a) Efficiency with the proposed SDSR system, with diodes and with a conventional SR system. (b) Efficiency of the power supply.
in which the input voltage was 230 V. The best results were obtained with the proposed system, with the efficiency being about two or three points higher than the efficiency obtained with the conventional rectification system based on diodes. If the voltage source system is disconnected, the synchronous rectifiers will only be on during the duty-cycle length. In this case, the efficiency was about five–six points lower, as shown in Fig. 8(a). Finally, Fig. 8(b) shows the efficiency of the power supply for the whole input voltage range (190–250 V) when the new SDSR system was used. As can be seen, the efficiency is quite constant in all the operating conditions and is typically around 90%. V. C ONCLUSION This paper has presented a detailed study of a recently proposed SDSR system that keeps the synchronous rectifiers on during the dead times of the transformer. The system is based on the use of a voltage source which charges the gate of the MOSFETs when there are 0 V across the transformer. This voltage source can be programmed by means of a very simple system so that it can adapt its value depending on the input voltage. The objective is to have the most efficient voltage for each operating condition. The experimental study concludes that the switching losses due to small cross-conduction periods are more significant than the conduction losses. Hence, a lower voltage source value makes way for a slightly negative turnoff voltage which avoids any cross-conduction problem on the synchronous rectifiers. The efficiency was two points higher than in the case of using conventional rectifying diodes. R EFERENCES [1] C. Blake, D. Kinzer, and P. Wood, “Synchronous rectifiers versus Schottky diodes: A comparison of the losses of a Schottky diode rectifier,” in Proc. IEEE APEC, 1994, vol. I, pp. 17–23. [2] J. A. Cobos, O. García, J. Sebastián, and J. Uceda, “Active clamp PWM forward converter with self driven synchronous rectification,” in Proc. IEEE INTELEC, 1993, pp. 200–206. [3] M. M. Jovanovic, M. T. Zhang, and F. C. Lee, “Evaluation of synchronous-rectification efficiency improvement limits in forward converters,” IEEE Trans. Ind. Electron., vol. 42, no. 4, pp. 387–395, Aug. 1995. [4] J. A. Cobos, O. García, J. Uceda, and F. Aldana, “Optimized synchronous rectification stage for low output voltage DC/DC conversion,” in Proc. IEEE PESC, 1994, pp. 902–908.
[5] P. Alou, J. A. Cobos, J. Uceda, M. Rascón, and E. de la Cruz, “Design of a low output voltage DC/DC converter for telecom application with a new scheme for self driven synchronous rectification,” in Proc. IEEE APEC, 1999, pp. 866–872. [6] S.-S. Lee, S.-W. Choi, and G.-W. Moon, “High-efficiency activeclamp forward converter with transient current build-up (TCB) ZVS technique,” IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 310–318, Feb. 2007. [7] J.-J. Lee and B.-H. Kwon, “DC–DC converter using a multiple-coupled inductor for low output voltages,” IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 467–478, Feb. 2007. [8] M. Castilla, L. G. de Vicuna, J. M. Guerrero, J. Matas, and J. Miret, “Designing VRM hysteretic controllers for optimal transient response,” IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 1726–1738, Jun. 2007. [9] A. Fernandez, J. Sebastian, P. J. Villegas, M. M. Hernando, and L. Alvarez Barcia, “Low-power flyback converter with synchronous rectification for a system with AC power distribution,” IEEE Trans. Ind. Electron., vol. 49, no. 3, pp. 598–606, Jun. 2002. [10] A. Fernandez, J. Sebastian, F. F. Linera, and A. Ferreres, “Single-stage AC-to-DC converter with self-driven synchronous rectification that complies with EN61000-3-2 regulations,” IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 1062–1064, Oct. 2003. [11] Y. Panov and M. M. Jovanovic, “Design and performance evaluation of low-voltage/high-current DC/DC on-board modules,” in Proc. IEEE APEC, 1999, pp. 545–552. [12] H.-J. Chiu and L.-W. Lin, “A high-efficiency soft-switched AC/DC converter with current-doubler synchronous rectification,” IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 709–718, Jun. 2005. [13] P. Alou, J. A. Cobos, O. García, R. Prieto, and J. Uceda, “A new driving scheme for synchronous rectifiers: Single winding self-driven synchronous rectification,” IEEE Trans. Power Electron., vol. 16, no. 6, pp. 803– 811, Nov. 2001. [14] A. Fernández, J. Sebastián, M. M. Hernando, P. Villegas, and J. García, “New self-driven synchronous rectification system for converters with a symmetrically driven transformer,” IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 1307–1315, Sep. 2005.
Arturo Fernández (M’98) received the M.Sc. degree and the Ph.D. degree in electrical engineering from the Universidad de Oviedo, Gijón, Spain, in 1997 and 2000, respectively. In 1998, he joined the Universidad de Oviedo as an Assistant Professor, where, since 2003, he has been an Associate Professor. Since 2007, he has been a contractor at the European Space Agency and is currently working in the Power and Energy Conversion Division. He has been involved in about 20 power electronics research and development projects since 1997, and he has published over 50 technical papers. His research interests are switching-mode power supplies, low output voltage, converter modeling, highpower-factor rectifiers, and power electronics for space applications. Regarding power factor correction issues, he has been involved in the development of highpower-factor rectifiers for Alcatel and Chloride Power Protection. Dr. Fernández cooperates regularly with the IEEE and the IEEE PELS Spanish Chapter.
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FERNÁNDEZ et al.: SDSR SYSTEM WITH INPUT VOLTAGE TRACKING FOR CONVERTERS WITH A TRANSFORMER
Diego G. Lamar (M’05) was born in Zaragoza, Spain, in 1974. He received the M.Sc. degree and the Ph.D. degree in electrical engineering from the Universidad de Oviedo, Gijón, Spain, in 2003 and 2008, respectively. In 2003, he became a Research Engineer at the University of Oviedo, where, since September 2005, he has been an Assistant Professor. His research interests are switching-mode power supplies, converter modeling, and power-factor-correction converters.
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Javier Sebastián (M’87) was born in Madrid, Spain, in 1958. He received the M.Sc. degree from the Polytechnic University of Madrid, Madrid, and the Ph.D. degree from the University of Oviedo, Gijón, Spain, in 1981 and 1985, respectively. He was an Assistant Professor and an Associate Professor with the Polytechnic University of Madrid and the University of Oviedo. Since 1992, he has been with the University of Oviedo, where he is currently a Professor. His research interests include switching-mode power supplies, resonant power conversion, converter modeling, and high-power-factor rectifiers.
Miguel Rodríguez (S’06) was born in Gijón, Spain, in 1982. He received the M.S. degree in telecommunication engineering in 2006 from the University of Oviedo, Gijón, where he is currently working toward the Ph.D. degree. His research interests include low- and mediumvoltage dc–dc converters and power supply systems for RF amplifiers.
Marta M. Hernando (M’94) was born in Gijón, Spain, in 1964. She received the M.S. and Ph.D. degrees in electrical engineering from the University of Oviedo, Gijón, in 1988 and 1992, respectively. She is currently an Associate Professor with the University of Oviedo. Her main interests include switching-mode power supplies and high-powerfactor rectifiers.
Manuel Arias (S’05) was born in Oviedo, Spain, in 1980. He received the M.Sc. degree in electrical engineering in 2005 from the University of Oviedo, Gijón, Spain, where he is currently working toward the Ph.D. degree. Since February 2005, he has been a Researcher with the Department of Electrical and Electronic Engineering, University of Oviedo, where he is developing electronic systems for UPSs and electronic switching power supplies. Since February 2007, he has also been an Assistant Professor of electronics at the same university. His research interests include dc–dc converters, dc–ac converters, and UPSs.
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