Schlumberger Technologies -ATE Division. 1601 Technology Dr. San Jose, CA 951 10-1397. ABSTRACT. This paper describes a novel digital functional test ...
Sequencer Per PinTM Test System Architecture Burnell West and Tom Napier Schlumberger Technologies -ATE Division 1601 Technology Dr. San Jose, CA 951 10-1397 ABSTRACT
This paper describes a novel digital functional test system architecture in which the timing and waveform generation hardware work with a sequence of events in the same manner as an IC timingllogic simulator. INTRODUCTION
As the complexity and pin count of VLSl integratedcircuits have exploded, test program generation has become immensely more complicated. VLSl semiconductor manufacturers are using the data from the simulationof these complex IC’s to generate timing information and test vectors for the test program. In most cases either the input data to, or output data from the simulator must be modified, before timing and test vectors can be generated with this simulation data. This is primarily due to the difference in the technique in which the simulator and test systems handle waveform generation. TimingAogic simulators work with transitions in the input and output waveforms to the IC which are called events (i.e. event driven simulation). Test systems generate waveforms by trying to fit a certain format around these transitions and then programming the time at which these transitions are to occur with edges from a timing generator. The IC simulation is not restricted to using formats or limiting the number of transitions that occur in a period of time. Often a simulation will contain waveforms that the test system can not produce. One solution is to perform a special simulation in which the input data to the simulator has been modified so that the simulation will not contain waveforms that cannot be produced on the test system. Another approach is to modify the simulation output to make the data fit the test system. Modifying the input or output of the simulation has several negative effects: Increases test program generation time. Reduces the accuracy of the test by diverging from the intent of the simulation. Increases debug time if modifications to the simulation output create errors. This paper introduces a new and novel ATE architecture, sequencer Per PlnTM, in which waveforms are
generated in the same manner as a timing/logic simulator. We will describe how the Sequencer Per Pin architecture allows waveforms to be generated from the simulation data using an event sequence concept. Because this is the same concept as used by the simulator no modifications are necessary to make the simulation fit the test system architecture. This architecture reduces the test program generationtime, while insuring that the intent of the simulation is performed during testing. The Sequencer Per Pin architecture also makes generating hand coded test programs more straight forward and faster. BACKGROUND
When digital functional automatic test equipment first became popular in the latter part of the 603, its architecture was very straightforward. Latches written by controllers formed the stimulus for the device under test, and comparators on the outputs would verify the device response. The standard paradigm for digital functional test was embedded in the ATLAS language statement “DO-DIGITAL-TEST”, with the logical image of test functionality represented by the diagram of Figure 1.
Mask (or Strobe
Figure 1. Digital FunctionalTest Paradigm The device is driven by FDrv if enabled by I/O. Otherwise the device output is compared to FExp as long as the signal Mask (or Strobe) permits. Each succeeding digital functional test consists of the following sequence of events: Establish the device inputs. Wait for the device to respond.
1990 InternationalTest Conference CH2910-6/0000/0355$01.OO 0 1990 IEEE
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Check the device outputs.
For each device pin, at any given instant in time at most one of the following state changes can occur: Drive to HIGH Drive to LOW Drive OFF Begin Test for HIGH Begin Test for LOW Begin Test for Z-State End Test Complexity arises because different pins require different sequences of events, and the timing at which the state changes are to occur will in general vary from pin to pin. Test system architectures in the sixties and seventies evolved to minimize the hardware requiredto effectively produce large sequences of pin events. This was necessary, because good test hardware is costly. The principal architectural innovationof that period was the separation of functional data from timing, resulting in the development of very deep pattern memory applied with shared timing generators (TG’s).[lJ The functional data appeared as tables of 1’s and 0’s(test vectors). Very effective functional tests could be produced for complex devices with just a few timing generators connected to pattern data by multiplexers and formatters. But this architecturalconstruction, effective as it was at that time, introduced difficulties of its own. As devices became more complex, the process of parsing the test requirement into the pattern table and the timing became increasingly difficult. Limited numbers of timing resources inevitably imposed increasingly stringent restrictions on their use. The translation from the simulator output to the test program became increasingly more obscure and problematical. At the same time, device speeds dramatically increased, which made test margins ever more difficult to obtain. Pin skew and timing generator distribution skew began to dominate tester performance considerations.[2] During the last decade, TG-per-pin test systems were introduced to help alleviate some of these problems.[361 As more and more resources are applied independently to each of the device pins, fewer and fewer machine restrictions are imposed on the functional test program. But simply applying a TG per pin does not eliminate the translation problem. The need to modify the simulation data exists regardless of whether the test system has shared resource timing or TG-per-pin timing architecture. The TG-per-pinarchitecture allows the flexibility to generate independent waveforms on
Paper 18.2 356
every device pin, but still restricts the waveforms with tester oriented formats and limited transitions. Furthermore, many of the available TG-per-pinsystems do not provide calibrated edge placement on all functions. Thus manual changes to the timing are still required to get adequate yields. These restrictions are removedby providing each pin with a full test event sequence capability. SEQUENCER PER PIN
We define an ‘event’ to be a pair (s,t), where ‘s’is a state and 7’ is the time associated with a transition to ‘s’.An ‘event sequence’ is a time-ordered list of such pairs. For example, the waveform in Figure 2 here:
I
Figure 2.
is defined by the event sequence (D1,l),(D0,8),( D1,13),( D0,18), interpreted as: Drive to HIGH at T=l Drive to LOW at T=8 Drive to HIGH at T=13 Drive to LOW at T=18 The seven event types identified earlier are sufficient to define any digital test completely. Clearly, such a list can be derived directly from a simulator output. The goal is to apply this simulator data directly to the device. This goal is achieved simply by applying appropriate event sequences, as defined by the simulator output, to each pin independently. For this, we need a full sequencer for each pin. A Sequencer Per Pin circuit contains the local memory, local memory addressing, event timing generation, drive and strobe edge generation, event sequence memory, hardware calibration circuitry, strobe comparison, and fail storage logic. Each Sequencer Per Pin circuit is independentof all other pins. For convenience in pattern storage and human comprehension of the test sequence, we do not dispense with the concept of Fdata entirely. Also to reduce the amount of storage allocated to time values, the concept of global test period is reintroduced. However, the global test period is no longer a statement of how fast the device is running; it becomes nothing more than a convenient method of subdividing the test. This results in the architecture shown in Figure 3.
StimuIuJ~~Response Period Marker
TF TF2 T E TF2TZ X
- Test for 1st bit LM data
- Test for 2nd bit LM data - Test for 1st LM data complement
- Test for 2nd bit LM data complement - Test for high impedance - Turn window strobe off
The Sequencer Per Pin circuitry is organized as shown in the block diagram of Figure 4. Master Clock
Pin
Figure 3. Sequencer Per Pin Architecture The Sequencer Per Pin circuit receives a global period marker and global event selection. The global event takes on the appearance of a 'test vector' as defined by the test systems of earlier architectures. We will use these terms interchangeably, but the reader is cautioned to keep in mind the distinction. These signals, together with the master clock, keep all pins synchronized. The stimulus waveforms generated by each Sequencer Per Pin are sent to the pin electronics in the test head. Each Sequencer Per Pin also receives the DUT output data for comparison after it has been compared to preset thresholds by the pin electronics in the test head. The period marker consists of a period time zero event which is synchronized with the master clock, together with a period vernier value which tells the Sequencer Per Pin precisely when within the clock period the event sequence is to begin. The resolution of the period vernier is the test period resolution (not, as in many earlier architectures, the master clock itself). Clearly, with this arrangement, there is no need to manipulate the master clock frequency to achieve desired stimulus pattern rates, with the consequent test program complications. EVENT GENERATION
Reintroduction of the concept of F-data enlarges the table of event types. In the current implementation, pattern memory may contain one or two bits per pin per global event (test vector). With these additions, events (now designated s*, t*) may be any of the following types: DO D1 DF DF2 DFDF2DZ TO T1
- Drive a 0
- Drive a 1 - Drive 1st bit LM
- Drive 2nd bit LM data - Drive 1st LM data complement - Drive 2nd bit LM data complement - Turn drive off - Test for a 0 - Test for a 1
The Global Event Selection Signal accesses the event sequence assigned to each pin in its local event store. This sequence of events is stored in the form (9,t*), where now s' is the expanded table, and 1' is the time after the global period commences. This event sequence selection is loaded into the circuitry at the clock cycle containing the period beginning. At the same time, one or two F-data bits are latched from the pin's local memory, and the period offset (time from clock cycle edge to start of the period) is saved up. This action also initiates a new period count (several period counters are used, permitting overlap of the calculated times). The fractional part of the programtimet* is added to the period off set, and the result of this calculation becomes the cycle-count-plus-vernierfor the specified edge, but at this point the time value is uncalibrated. The event type s' is converted in the Event Type Decoder to one of the original seven types. This type controls the selection of the calibration offset, which is used to compensate for inevitable path length and circuit performance differences. To minimize skew from various state transitions, the calibration store contains values for different starting states. For example, the calibration offset associated with D1 from Z is different from that associated with D1 from 0. The event time t* is calibrated by an event-dependent cal memory. The calibrated time is designated t". Additionally, each Sequencer Per Pin can store a sequence of 192 events. These may be segmented up to 64 times to give 64 different event sequences per pin. Event sequences are defined on a per pin basis and each pin's event sequences are independent of those on any other pin. This gives the flexibility for 1 pin to have only a single event sequence with 192 events, while another pin could have 64 different sequences with 1,2, or 3 events each. The pins are synchronized by local event sequence memory (which is similar in concept to a Time Set Memory). A global event sequence chooses which event sequence to use of the 64 available for each Sequencer Per Pin. The current design has memory to store 1024 global event sequences, and this memory may easily be expanded to store 4096 global event sequences. The global event Paper 18.2 357
Global Sequence Address
Global Event Sequence Store Memory (Time Set Memory) (1024x 8)
%=I-
p-k
Global Memory
II
t 62 I Memory 1 or 2 Bits per Pin 4 I8 Mbits Period Vernier
I
Event Time1 Event TvDe
I
Signals to Pin Electronics
I,. 1
M I
+
EventType Decode Strobe
Pin Electronics
--). Format + -- -t + Logic
___fl__
4
S
Calibrated Time
v
Drive Edge Generator
Counters Period Value, Global TZ, Master Clock
Comparator Edge Generator
Figure 4. Sequencer Per Pin Block Diagram
sequence is selectedfrom local memory on a vector by vector basis.
To give even greater flexibility in waveform generation, as for instance when testing devices with long analog delays, events may be programmedto occur anywhere within 3 cycles. The resolution of placing the event is 12.5~s. Waveform frequencies can be generated in excess of 100 MHz. As noted above, each event type generated by the Sequencer Per Pin has a unique calibration value which is used to calibrate the event. Each pin has a memory to store these values for each event type, so the event is calibrated, “on the fly”, as it is used. This allows the system to be calibrated with no more than 175ps of skew between pins.
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LOCAL MEMORY (F-DATA) MEMORY
The local memory has a depth of 4 megabits per pin and this may be optionally expanded to 32 megabits. The local memory can be used in a 1 bit or 2 bit per pin per vector mode. The 2 bit per pin mode can be used for presenting 2 bits of functional data to a pin in a cycle such as required by an IO pin where the data driven to the DUT is different from the DUT output data. The second bit may also be used as a mask bit for devices that require a large combination of “care” and “don’t care” pins in different cycles, such as are frequently found on ASIC simulations vectors. Each pin in the Sequencer Per Pin design has a counter to control the local memory addressing. This is very useful in performing scan mode testing since the local memory for the scan pin may be stepped without affecting the other pins. The Sequencer Per Pin is also designed to support alternate sources of data from
such options as an algorithmic pattern generator or a super large scan memory. The local memory may be augmented with an optional subroutine local memory. Afail memory register is also a part of each Sequencer Per Pin and this can be expanded to store up to 16K bits of fail data per pin.
IC will never exceed 85' C. A low stable junction temperature will greatly decrease component failure and improve accuracy by preventing component timing from drifting due to temperature changes.[9]
200 MHZ DATA RATES AND WAVEFORMS
The Sequencer Per Pin architecture makes programming complex waveforms very simple. The user only needs to define the type of event and the time at which the event is to occur. Waveform formats that were used on the previousgenerationof ATE are easily generated using the event sequence concept. For example NRZ format is specified by programming one event.
Pulse Mode provides a means for generating data rates up to 200 MHz and clock rates up to 312.5 MHz without using pin mux mode. In Pulse mode each drive event initiates a Returnto Zero, RTZ, or Return to One, RTO, pulse depending on the event type, local memory data, and the pulse direction programmed on a pin. The width of the pulse on each pin is programmed before executing the test. The placement of the pulse is determined by the programming of the event time. Pin Mux Mode is also part of the Sequencer Per Pin architecture. This allows the Sequencer Per Pin to double its frequency and still use all the flexibility of event types. This mode logically ORs the timing events and functional data between 2 adjacent pins to double the functional data rate and event rate. Each pair of Sequencer Per Pin channels may use pin mux mode independent of any other pin. IMPLEMENTATION
The Sequencer Per Pin circuit is implementedin a total of eight custom integratedcircuits. The heart of the circuit is an ASIC which performs the event generation and timing. Six calibratable linear delay elements using ECL technology for speed and stability are used to achieve the required high resolution and accuracy. A local memory control IC is implemented in CMOS. A pin slice PCB contains four Sequencer Per Pin channels.[7-81 Since the local memory, timing, waveform generation, and calibration circuits are all contained on a single board the configuration of the system is very modular and easily configured to the user's needs. Also, this partitioning minimizes the number of system interconnections and therefore improves the overall reliability.
PROGRAMMING THE SEQUENCER PER PIN
DF@1ns This statement directs the hardware to drive to the current vector's data at InS. The following is a graphical display of the NRZ waveform.
I I
to
10
' D'F
'
DF
SBC format is specified by programmingthe following sequence of events. This shows the ease with which other ATE architecture test programs may be ported to the Sequencer Per Pin architecture. DF-@2n s D F @ l l ns DF-@22ns
I
to
to
The high speed sections of the system are liquid cooled to insure their reliability and stability. A cold plate is attachedto each card and a specially designed heat sink transfers the heat from each component on a board to the cold plate. The cold plate is cooled by refrigerated FC77 liquid circulating through copper tubing. This ensures that the junction temperature on any
Paper 18.2 359
1
A clock pin can be generated with no local memory data by programming the following sequence of events.
I
Dl@Ons DO@4ns D1@8ns DO@ 1Ons
I
The Following diagram shows a graphical drawing of this sequence of events:
T1
TZ to
TF2
t t
t t o
to
I Different event sequences may be used to change the number of clocks that occur in a cycle and the placement of the clock transitions. More complex control pin sequences can also be programmedwithout the use of functional data tables at all. As a consequence, actual data pattern storage can be well below one bit per pin per vector, reducing the demand on pattern storage space and load times. Below is an example of waveform generation for an IO cycle with the DUT pin being driven with a surround by complement (SBC) waveform, then the driver being turned off and the output being strobed first for tri-state, then a 1, and then local memory data which is different from the drive data. DF-@ 2ns DF@7ns OF-@ 16ns DZ@20ns TZ@24ns X@26ns T1@32ns X@34ns TF2@40ns X@42ns
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- Drive functional data complement - Drive functional data - Drive functional data complement - Turn driver off
- Test for Tri-state - Turn window strobe off
- Test for a 1 - Turn window strobe off - Test for 2nd functional data - Turn window strobe off
x
x
x
Complex waveforms such as this are not possible on test systems with shared resource or TG-per-pinarchitectures. This example used 10 events and the Sequencer Per Pin could generate up to 192 events in one cycle. The ability to have two bits of functional data in each cycle allows the Sequencer Per Pin architecture to drive one set of data or test for a different set in the same cycle. This is done without using mux mode which would reduce the available pin count of the test system. Being able to place an event with 1 2 . 5 ~ sresolution and anywhere across 3 cycles, gives the architecture even more waveform generation and strobe placement flexibility. This type of flexibility makes generating timing statements and test vectors from simulation data fast, easy, and accurate. Eliminating the need to make the simulation fit the test system will improve the time to generate new test programs, generate better tests that follow the intent of the simulation, and decrease the amount of time to debug a new test program. Because the Sequencer Per Pin is truly a complete functional slice of the tester, including pattern memory management, another benefit of the Sequencer Per Pin architecture is its ability to let the operating system dynamically allocate test system channels at the time the test program is installed. To provide the optimum electrical interface between the test system and DUT several different pin configurations may exist for a test program (i.e. wafer sori and package part pin configurations). The Sequencer Per Pin architecture allows each tester channel to be assigned to a device pin at install time. The tester operating system will prompt the user for which pin configuration is to be used at install time. This saves disk space by not having to store test programs and local memory patterns for each DUT to test system pin configuration. The logistics of managing a program library are also eased because only a single test program and test vector pattern file are re-
quired for each device.
Reference:
Software tools have been designed to work with the Sequencer Per Pin architecture. These tools make viewing and modifying the test program waveforms very simple by displaying the waveform graphically and allowing the user to modify the test program via the graphical display. The changes not only affect the current tester setup but also may be used to update the test program automatically.
1. Herlein, R.,‘Optimizingthe Timing Architecture of a Digital LSI Test System’, ITC Proceedings, pp. 200-205,1983. 2. Sugamori, S., Yoshida, K., Maruyama, H., Kamata,
S . ‘Anaylsis and Definition of Overall Timing Accuracy in VLSl Test System’, ITC Proceedings, pp. 143-153, 1981. 3. Bisset, S.,‘The Development of a Tester-Per-Pin
CONCLUSION 4.
A revolutionary tester architecture, the Sequencer Per Pin architecture, has been described. This architecture implements tests as sequences of events for each pin, synchronized by global period markers. This allows for performing complex tests on VLSl integrated circuits without requiring extensive program development and debug efforts. The automatic generation of these complex waveforms and strobe placement from timing simulators was not possible on the prior generations of ATE. In addition, this architecture is more flexible than previous designs, permitting more precise implementations of simulation data with fewer restrictions. The Sequencer Per Pin architecture will decrease the time needed to generate test programs by reducing the manual intervention required to generate timing and test vectors from timing/logic simulation data. The event sequence concept allows significant reduction in test pattern storage requirements, and optimizes this feature even further by permitting run-time assignment of pin data, avoiding duplications of test patterns and test programs for different package configurations.
5. 6.
7.
VLSI Test System Architecture’, ITC Proceedings, pp. 151-155, 1983. Sudo, T., Yoshii, A., Tamama, T., Narumi, N., Sakagawa, Y. ‘“ULTIMATE”: A 500-MHz VLSl Test System with High Timing Accuracy’, ITC Proceedings, pp. 206-213, 1987. Chang, Y., Hoffman, D., Gruodis, A., Dickol, J., ‘A 250 MHZ Advanced Test System’ ITC Proceedings, pp. 68-75, 1987. Grasso, L.J., Morgan, C., Peloquin, M., Rajan, F., ‘A 250 MHz Test System’s Timing and Automatic Calibration’, ITC Proceedings, pp. 76-84, 1987. Tamama, T., Narumi, N., Otsuji, T., Suzuki, M., Sudo, T., ‘Key Technologies for 500-MHz VLSl Test System “ULTIMATE”’, ITC Proceedings, pp.
108-113, 1988. 8. Muething, R., Saikley, C., ‘Integrated Pin Electronics: A Path Toward Affordable Testing of High-Pin Count ASIC Devices’, ITC Proceedings, pp. 883887,1987. 9. Sakagawa, Y., Akazawa, Y., Narume, N., Yoshii, A., Sudo, T., ‘Packaging Technologies for 500-
MHz VLSl Test System “ULTIMATE”’, ITC Proceedings, pp. 120-124, 1988.
(Sequencer Per Pin and SPP are trademarks of Schlumberger Technologies)
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