Several Approaches to Parallel Computing in the Boolean Domain

Several Approaches to Parallel Computing in the Boolean Domain Bernd Steinbach and Wolfram Wessely

Christian Posthoff

Institute of Computer Science Freiberg University of Mining and Technology Freiberg, Germany Email: [email protected]

Department of Mathematics & Computer Science The University of the West Indies Trinidad & Tobago Email: [email protected]

Abstract—Each additional variable doubles the number of function values of a Boolean function. This exponential increase is known as combinational explosion and limits strongly the solvable problems for a given computer. In order to solve larger Boolean problems, it is necessary to exploit each concept that reduces the required efforts. The parallel consideration of all Boolean variables that are assigned to a machine word of the computer, the mapping of an exponential number of Boolean vectors to a single ternary vector, and the distribution of the calculations to several Boolean spaces are some approaches which were realized in the software package XBOOLE. An important further approach is the segmentation of the Boolean tasks and their parallel computation using several connected computers as well as the available processor cores of these computers. In this paper we explore alternative approaches to parallel computations of Boolean problems. Experimental results document the achieved benefits. Index Terms—Parallel computing, Boolean function; message passing interface; XBOOLE.

I. I NTRODUCTION The comprehensive utilization of digital systems has significantly changed life all over the world. Boolean functions and equations are one source of this continuously extended process. Hence, solving Boolean equations is a big challenge to solve Boolean problems which will be larger and larger. Boolean operations (with sets), such as complement, intersection, union or symmetric difference are required for the analysis, the synthesis and the testing of combinational circuits as well as finite state machines [6], [11] and [15]. Innovative approaches in nanotechnologies [19] lead to the same basic operations. Convenient data structures for large problems in these fields are binary decision diagrams (BDD) [11] and ternary vector lists (TVL) [1]. A suitable toolbox that allows an efficient solution of large logic problems is XBOOLE [1], [2], and [12]. The toolbox XBOOLE can be used beneficially for the education of engineers in the area of computer-aided design of discrete devices [6], and [15]. Therefore we use TVLs and the given operations of XBOOLE consistently to solve the specified problems. It is well-known that the possible number of solutions of an equation of n logic variables is equal to 2n . This exponential complexity requires the use of each possible approach to the improvement of existent algorithms. Additionally motivated

by the strong technological progress in implementing very high-scale integrated circuits, it is a scientific challenge to solve Boolean problems depending on a very large number of variables. It is the aim of this paper to show several approaches to improve the state of the art in this field [8] and [18]. Due to the restricted space of this paper and in order to emphasize the achieved improvements we selected appropriate examples of neighboring fields [7], [8], [9], [15] and [17]. Such problems can be easily explained and simply extended to higher numbers of variables such that the limits of practical solvability are reached. It is our aim to shift these limits as much as possible into the direction of larger numbers of logic variables. Our approaches in this paper focus on the application of parallel processing [3], [5], [8], and [18].

II. TASKS TO BE S OLVED A. Satisfiability Problem There is a huge number of different special tasks in the Boolean domain. Many of these can be mapped to the satisfiability problem, called SAT. Each SAT problem is given as Boolean equation having a constant value of 1 on the right-hand side. The left-hand side is a Boolean expression in conjunctive form. That means, disjunctions of Boolean variables are connected by AND-operations. The k disjunctions are called clauses. There is an overall number of n variables. These variables are used in the clauses directly or as negated variables. Typically, in each clause a subset of the n variables is connected disjunctively. An example of a SAT problem may be (x4 ∨ x13 ∨ x18 ∨ x24 ) ∧ (x2 ∨ x7 ∨ x119 ∨ x184 )∧ (x15 ∨ x24 ∨ x29 ) ∧ . . . ∧ (x1 ∨ x154 ∨ x172 ∨ x254 ) = 1 . The SAT equation can be transformed into a system of Boolean equations that consists of k Boolean equations having one of the clauses on the left hand-side and a constant value

1 on the right-hand side. For the example given above, we get (x4 ∨ x13 ∨ x18 ∨ x24 ) = 1 (x2 ∨ x7 ∨ x119 ∨ x184 ) = 1

III. PARALLELIZATION ON A S INGLE P ROCESSOR

(x15 ∨ x24 ∨ x29 ) = 1 .. .

A. Parallel Calculation of Boolean Values

(x1 ∨ x154 ∨ x172 ∨ x254 ) = 1 . The solution set si of each of these equations can be represented by a list of orthogonal ternary vectors (TVL). The solution set s1 of the first equation is displayed in the following TVL.

s1

=

x4 0 1 1 1

x13 – 0 1 1

x18 – – 1 0

x24 – – – 1

After this preprocessing the main task of the SAT problem consists in the calculation of k − 1 intersections according to (1). S=

k \

si

(1)

i=1

Formula (1) looks simple, but it is very time-consuming to calculate the final solution set S [17]. A second limit for the solution process is the huge memory needed to store the intermediate and final solution vectors. B. Decomposition Problem As a second example we explain the bi-decomposition of an incompletely specified Boolean function [4], [6] and [15]. The incompletely specified function is given by the Boolean function fq (x) which describes the ON-set and the Boolean function fr (x) for the OFF-set, respectively. For a bidecomposition we break the set of variables into three subsets x = (xa , xb , xc ). An OR-bi-decomposition f (xa , xb , xc ) = g(xa , xc ) ∨ h(xb , xc ) with regard to xa and xb exists if (2) holds: fq (x) ∧ maxm fr (x) ∧ maxl fr (x) = 0. xa

xb

For other types of bi-decomposition similar calculations can be done in parallel. From the found bi-decompositions the most compact one will be selected.

(2)

Whether there is an OR-bi-decomposition depends on both the given incompletely specified function and the segmentation of the variables into the three subsets. It was proven that there is no OR-bi-decomposition for a given incompletely specified function if (2) does not hold for any pair of variables in the subsets xa and xb . Hence, Formula (2) must be evaluated for any pair of variables. These calculations are completely independent on each other and can be executed in parallel. For extended sets of variables xa and xb further calculations of (2) can be executed in parallel as well.

The basic operations for Boolean variables in the Boolean algebra are the complement (NOT), the conjunction (AND), and the disjunction (OR). In the Boolean ring additionally the EXOR-operation (XOR) is defined. These operations can be executed directly for variables of the type Boolean by the arithmetic logic unit (ALU) of a processor. The operations mentioned above are available as bitwise operations on each processor. Hence, these Boolean operations can be executed in parallel for a number of Boolean variables that is less or equal to the width of the computer registers. At present it is possible to consider 32 or 64 Boolean values as result of the mentioned operations in parallel on standard PC’s. For more powerful processors this processing width w of calculations is equal to 128 or even higher. A package that utilizes these bitwise parallel operations consequently is XBOOLE [1], [2], [6], [12] and [15]. If the number of Boolean variables is larger than the calculation width of the processors, several memory words are used. Inside of these words the calculation is executed in parallel while the required words of Boolean vectors are considered in a sequential order. This approach improves the Boolean calculations by a factor of the processing width w. B. Ternary Representation of Boolean Vectors The number of Boolean vectors grows exponentially with the number of Boolean variables in the vectors. Assume two Boolean vectors that have a combination of (0,1) in one of the components and identical values in each of the remaining components. Such two Boolean vectors can be replaced by a single ternary vector, that includes a dash 0 −0 instead of the (0, 1) - combination and the unchanged values of the remaining components. As example we can express the Boolean vectors (0100110) and (0100010) by the single ternary vector (0100-10). The same principle of merging Boolean vectors can be applied for ternary vectors, too. In the identical components of two vectors the elements 0, 1 and - are allowed. In the single component with different values the combination (0,1) is required. Such pairs of ternary vectors can be merged into a single ternary vector that includes a dash 0 −0 instead of the (0, 1) - combination and the unchanged values of the remaining components. As example we can express the ternary vectors (--00110) and (--00010) by the single ternary vector (--00-10). Let be given two ternary vectors x and y. The intersection of these two vectors (i.e. the intersection of the respective two sets of binary vectors) will be computed according to Table I which has to be applied in each component of the two vectors. The symbol ∅ indicates that the intersection of the two sets is empty and can be omitted. A sophisticated coding of the three

TABLE I I NTERSECTION OF T ERNARY VALUES . xi yi xi ∩ yi

0 0 0

0 1 ∅

0 − 0

1 0 ∅

1 1 1

1 − 1

− 0 0

and data between processes that run in parallel is supported by the functions of the message passing interface (MPI) [3]. − 1 1

− − −

values 0, 1 and − allows the introduction of binary operations for the ternary vectors. As shown in the subsection III-A, these binary operations can be executed on the level of registers (32, 64 or even 128 bits in parallel). We use the coding of Table II. The first bit indicates that the variable has a value in the ternary vector, the second bit indicates the value itself. TABLE II B INARY CODE OF T ERNARY VALUES . ternary value 0 1 −

bit1 1 1 0

bit2 0 1 0

When the three-valued operations for the intersection are transferred to these binary vectors, then the intersection is empty iff bit1(x) ∧ bit1(y) ∧ (bit2(x) ⊕ bit2(y)) 6= 0 .

(3)

In this case the two vectors are orthogonal to each other. If the intersection is not empty, then it can be determined by the following bit vector operations: bit1(x ∩ y)

= bit1(x) ∨ bit1(y) ,

(4)

bit2(x ∩ y)

= bit2(x) ∨ bit2(y)

(5)

Assume the numbers of dashes are nd1 and nd2 in the given two ternary vectors x, y of nall variables. Then the three vector operations of (3) verify whether the intersection of the given ternary vectors is empty. Due to the ternary representation, the three vector operations of (3) realize the computation of nall ·2nd1 ·2nd2 Boolean values. When the given ternay vectors are not orthogonal, the two vector operations of (4) and (5) compute a new ternary vector that represents the intersection of 2nd1 Boolean vectors of the first set and 2nd2 Boolean vectors of the second consisting of nall Boolean values each. Hence, the advantage of the ternary representation grows exponentially with the numbers of dashes in the ternary vectors. It should be mentioned that the software package XBOOLE [1], [2], [6], [12] and [15] utilizes this approach. IV. PARALLELIZATION U SING S EVERAL P ROCESSORS A. Parallelization of the Core Algorithm We assume that there are npc processor cores that can be used to solve a Boolean problem commonly, and for each of these processor cores a dedicated process is used. It is quite obvious to check the core algorithm for subtasks which can be solved independently in parallel. The exchange of information

Let us study first the properties of the parallelization of the SAT problem (1). Solving this problem requires the calculation of k−1 intersections of partial solution sets si . The intersection is a binary operation. That means the intersection operation needs two operands in order to calculate their intersection. Hence, bk/2c subtasks can be created which must calculate the intersection of one pair of partial solution sets (si , sj ). bzc indicates the largest integer that is smaller than or equal to z. These bk/2c subtask can be assigned to the np processes. The number bk/2c of subtasks must not fit to the number of processes np . If bk/2c > np , each process can solve at least one subtask. It leads to a good utilization of the available processor cores when the number of subtasks is significantly larger than the number of processor cores. A complete uniform utilization of all processor cores will not be reached in practice, because first of all the number of processor cores must not be a common divisor of the number of subtasks, and secondly the calculation efforts for the different subtasks must not have the same size. The result of the first run are bk/2c intermediate solution sets extended by sk in the case of an odd value k. On the first glance, it is a nice property of the SAT-problem that the result of an application of the procedure described above leads, for a SAT- problem of k partial solution sets, to a SAT problem of bk/2c + k mod 2 partial solution sets. This reduced SAT-problem can be solved in the same way. The loop of runs stops when a single final solution set was calculated. An essential disadvantage of the parallelization of the core algorithm is that in the later runs the number of subtasks becomes smaller than the number of processor cores, and the intersections of much larger partial solution sets than in the earlier stages must be calculated. Hence, at the end of the whole procedure few and finally one processor core must solve the largest subtask while the other processor cores must wait. This detailed analysis of the SAT-problem has shown that the parallelization of the core algorithm with obvious properties for the concurrent execution of subtasks utilizes the parallel processing power only partially. This counter-example should not exclude this basic approach of parallelization of the core algorithm for other task but it should sensitize to evaluate the reachable benefit of such a parallel approach carefully. Much better properties for parallelization of the core algorithm has the task of multilevel circuit design for incompletely specified Boolean functions by means of the bi-decomposition [4], [6] and [15]. The calculation of (2) must be executed for many combinations of the dedicated sets of variables xa and xb . Similar required calculations for other types of decomposition gates can be executed independently in parallel. The concurrent calculation of these subtasks even allows to skip some of the calculations if an initial intermediate result is found for one of the paths evaluated in parallel.

B. Ordered Lists of Ternary Vectors Advantages of the bit-parallel computation and the ternary representation are explained in Section III. The main data structure that utilizes these approaches is the ternary list of vectors (TVL). The vector operations mentioned in Section III must be executed typically for each pair of ternary vectors (ti , tj ), where ti is taken form the first TVL and tj from the second. Hence, the complexity of such TVL-operations is O(nr1 , nr2 ) where nr1 is the number of rows in the first TVL T1 and nr2 is the number of rows in the second TVL T2 . The approach of ordered lists of ternary vectors (OTVL) was suggested in [13], where the basic idea is given, and applied for the often needed intersection operation. We explore the intersection of OTVLs in this section too, but emphasize their application for parallel calculations. In later publications this approach was extended to other TVL-operations. The aim of OTVL is to reduce the calculation effort. An OTVL describes like a TVL one Boolean function. In contrast to the TVL, the ternary vectors of a OTVL are distributed to several sub-TVLs. The segmentation of a TVL into a OTVL is realized in two steps. First of all, sub-TVLs are created such that each ternary vector of a sub-TVL includes the same number of values 1. Secondly, each sub-TVL having the same number of values 1 in their ternary vectors is segmented again into part-TVLs such that each ternary vector of a partTVL includes both the same number of ones and the same number of dashes. The term ordered of the OTVL was chosen because the sub-TVLs can be ordered by their index that is equal to the number of ones in the ternary vectors, and the partTVLs can be ordered by two indexes, the first one no indicates the number of the ones and the second one nd the number of dashes in the part-TVL. All part-TVLs can be organized as elements of a (n + 1) × (n + 1) - matrix where at least one half of the elements is empty. The intersection of the TVLs T1 and T2 requires the comparison of each pair of their ternary vectors as explained above. This rule is passed to the OTVL such that the intersection of each pair of part-TVLs must be calculated. Using a single processor, the advantage of OTVLs is that not all such pair of part-TVLs must be included into the calculation. Using the values no1i for the number of ones in the part-TVL P T1i , nd1i for the number of dashes in the part-TVL P T1i , no2j for the number of ones in the part-TVL P T2j , and nd2j for the number of dashes in the part-TVL P T2j , it was proven in III that all pairs of ternary vectors of the P T1i and P T2j are orthogonal to each other if either no1i ≤ (no2j + nd2j )

(6)

a machine with several processor cores. The calculation of the remaining necessary intersections of the pairs of part-TVLs can be calculated independently in parallel on available processor cores. The strong segmentation of the TVL into smaller part-TVL leads to many subtasks which can be assigned to the available processor cores. These advantages are bought by the counting of the zeros and ones of all ternary vectors and the management of the ternary vectors using the counted numbers. C. Dividing the Boolean Space into Subspaces Subtasks of a Boolean problem can be created in a simpler way by dividing the Boolean space into subspaces. The theoretical basis for this approach is the Shannon-decomposition [10]. Using f (x0 , x1 ) = x1 ∧ f (x0 , x1 = 0) ∨ x1 ∧ f (x0 , x1 = 1) (8) each Boolean function can be divided into two subfunctions that are independent on each other. The Shannondecomposition (8) can be applied recursively to several Boolean variables of the expression of the SAT-problem. A given SAT-problem can be divided into 2s smaller SATproblems if such Shannon-decompositions with regard to s variables are executed recursively. The created smaller SAT-problems can be solved in parallel on the available processor cores. The complete solution of the original SAT-problem comprises all solution sets calculated in parallel. No further operations are necessary for the combination of the partial solution sets. On the first glance this simple approach seems to be a general ideal solution for parallelization in the Boolean domain. All Boolean subspaces have the same number of Boolean values. However, the complexity of the tasks to be solved can be different for the 2s Boolean subspaces, therefore different run times occur. Another disadvantage is that this approach contradicts the benefits of the ternary representation. A dash in the position of the decomposition variable leads to the assignment of this vector to both subspaces and consequently to identical calculations in two processor cores which can be done basically only once in a single processor core. D. Controlled Distribution of Subtasks The segmentation of a Boolean problem into subproblems can be done without additional calculations utilizing a property of the Boolean function itself. In this approach the representation of a Boolean function as disjunctive form [16] is used. In such a disjunctive expression nc conjunctions Ci are connected by OR-operations: nc _ f (x) = Ci . (9) i=1

or no2j ≤ (no1i + nd1i ) .

(7)

The intersection of all such pairs of part-TVLs is empty. Therefore these pairs of part-TVLs can be excluded from the calculation of the complete intersection. In addition to this direct benefit on a single processor machine, the OTVL approach gives a valuable preparation for

Subsets of conjunctions of (9) can be used to build nf subfunctions fi (x). If each conjunction Ci is used in exactly one of the nf subfunctions fi (x), the Boolean function f (x) can be expressed by f (x) =

nf _ i=1

fi (x) .

(10)

Using the distributive law, we get from (10) f (x) ∧ g(x) =

nf _

(fi (x) ∧ g(x)) .

(11)

i=1

Formula (11) shows that the calculation of one AND-operation between two Boolean functions f (x) and g(x) can be replaced by nf AND-operation between each of the subfunctions fi (x) and the Boolean function g(x). These nf AND-operation are independent and can be executed in parallel. It is an advantage when the nf subfunctions fi (x) are orthogonal to each other. In that case the partial results include different parts of the entire solution so that these partial solutions can simply be combined without any further operations. This basic approach can be used for such Boolean problems where the solution can be calculated by one Boolean operation or iteratively by several Boolean operations. The SAT-problem belongs to this class of problems. Based on this method of segmentation, in [18], an approach for the parallel solution of a wide class of Boolean problems by controlled distribution of subtasks has been suggested. This approach is controlled by two parameters. The first parameter is the interimlimit. It defines how many rows must be created at least in an intermediate solution in order to split the task to be solved into subtasks. This parameter is important to avoid time-consuming communications between several processes for small tasks. Small tasks can be solved more efficiently on a single processor core. Practical experiments have shown that the optimal value of the interimlimit is in the range of 102 to 104 . The number of available processor cores may influence the optimal value of the interimlimit as well. The second parameter is the distlimit. The distlimit is equal to the number of conjunctions that are assigned to one subfunction of (11). If the quotient interimlimit/distlimit is equal to nf , each one of the napc available processor cores has to solve exactly one subtask. Experimental results in [18] have shown that the value one as distlimit is the best choice. The reason for that observation is that many very small task are created which can be flexibly assigned to the available processor cores. Hence, we get a good load balancing and consequently a short solution time. More details and experimental results about this approach are given in [18]. E. Parallel Backtracking The approach of parallel backtracking allows to solve Boolean problems of the same class as discussed in the previous subsection. This approach was suggested in [18], too. In contrast to the previous approach the parallel backtracking organizes its parallel work itself, utilizes a just suitable number of processors, and needs a single parameter only. The parallel backtracking selects one process as master and the available remaining processes work with equal rights and identical algorithms as clients. The main work to solve the problem is done by the clients. It is the task of the master to maintain the knowledge about all clients whether the client is

working on a subtask or waiting for a new subtask. Hence, each client is in one of the states working or waiting during the runtime. The initial action of the master is to assign the whole task to be solved to one of the clients. This client executes the necessary operations until the number of rows in the intermediate solution TVL becomes larger than the single parameter of the parallel backtracking which is the splitlimit. In this case the client splits the intermediate solution TVL into two parts due to Formula (11) with nf = 2. The first subtask will be solved as next by the client, and the second subtask is stored at the end of a local queue. It depends on the states of the other clients whether a subtask is moved at that point of time. If the number of rows in the intermediate solution TVL becomes larger than the splitlimit in one client, this client asks the master for a waiting client. • If there is no waiting client, the available subtask is solved. • If there is one waiting client, the subtask at the begin of the queue is moved to the waiting client and removed from the local queue. In that way most time-consuming tasks are exchanged first for the parallel backtracking. When a client has solved a subtask, the partial solution is stored locally. The further procedure depends on the local queue of subtasks. • If there is no further subtask in the queue, the client changes his state from working into waiting, it sends a message about this change to the master. • If there is at least one more subtask in the local queue, in one backtracking step the subtask from the end of the queue is extracted and solved as next. When all clients finished their work, the master collects all partial solutions from the clients and connects them to the complete solution of the problem to be solved. V. E XPERIMENTAL R ESULTS Due to the restricted space we present very few of our experimental results. In order to compare the approaches suggested in the last two subsections we used the 3-SAT-benchmark problem uf100-1. The given Boolean expression in conjunctive form depends on 100 Boolean Variables distributed over 430 clauses. For this comparison the best solution of the approach controlled distribution of subtasks was used. The value of the interimlimit was fixed to 1,000 in order to have enough conjunctions for the distribution. The best found value for the parameter distlimit was fixed to 1. Hence, due to the interimlimit more than 1,000 subtasks were created, each of them based on a single conjunction taken from the interim solution. It should be mentioned that for this special task a distlimit of 50 doubles the solution time, approximately. A uniform distribution of the interim solution vectors to the available processor cores requires even a four times longer solution time as in the best case of distlimit = 1.

For Boolean tasks with very large intermediate solution sets the approaches controlled distribution of subtasks and parallel backtracking were suggested. We have shown the advantage of the parallel backtracking for the solution of SAT problem.

180 160

controlled distribution of subtasks

140

R EFERENCES

120 time 100 (sec.) 80 parallel backtracking

60 40 20 0

10

20 30 40 50 number of processor cores

60

70

Fig. 1. Comparison of the approaches controlled distribution of subtasks (dotted line) and parallel backtracking (solid line) for the 3-SAT problem uf100-1 of 100 Boolean variables.

The splitlimit for the approach of parallel backtracking was fixed to 10,000. Figure 1 shows, that both approaches need 177 seconds to solve the task using 8 processor cores. However, the speed-up is much higher for the self-organized parallel backtracking. The reason of the advantage of the parallel backtracking in comparison to the controlled distribution of subtasks comes from the better load balancing. The trend of the curves in Figure 1 shows that, due to Amdahl’s law, the benefit of adding further processor cores is restricted. VI. C ONCLUSION The exponential complexity of the Boolean functions requires parallel approaches in order to solve Boolean tasks for larger numbers of variables. In this paper we have explored several such parallel approaches for both a single processor core and for multiple processor cores. The parallel calculation of the bits of a computer word should be applied as much as possible. The ternary representation allows to get profit from this approach exponentially. There are several approaches to tasks in the Boolean domain that require several processor cores. The selection of one of these approaches or the combination of some of them depends on the properties of the task to solve. If there is a large subset of different subtasks, the parallelization of the core algorithm should be taken into account. The parallelization of the basic operations by means of OTVL is still more general. A general approach for parallelization in the Boolean domain is the division of the Boolean space into subspaces. This can be done in several ways. The application of the Shannon decomposition may weaken the benefits of the parallel work inside of the processor cores.

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