SiC MOSFETs Based Split Output Half Bridge Inverter: Current Commutation Mechanism and Efficiency Analysis Helong Li, Stig Munk-Nielsen, Szymon Bęczkowski, Xiongfei Wang Department of Energy Technology Aalborg University Aalborg, Denmark
[email protected] Abstract—Body diode of SiC MOSFETs has a relatively high forward voltage drop and still experiences reverse recovery phenomenon. Half bridge with split output aims to decouple both the body diode and junction capacitance of SiC MOSFETs, therefore achieving a reduced switching loss in a bridge configuration. This paper makes the current commutation mechanism and efficiency analysis of half bridge with split output based on SiC MOSFETs. Current commutation process analysis is illustrated together with LTspice simulation and afterwards, verified by the experimental results of a double pulse test circuit with split output. The double pulse test shows the devices’ current during commutation process and the reduced switching losses of SiC MOSFETs compared to that of the traditional half bridge. The efficiency comparison is presented with experimental results of half bridge power inverter with split output and traditional half bridge inverter, from switching frequency 10 kHz to 100 kHz. The experimental results comparison shows that the half bridge with split output has an efficiency improvement of more than 0.5% at 100 kHz switching frequency.
I.
INTRODUCTION
Silicon Carbide (SiC) devices are emerging as an attractive replacement for silicon (Si) devices in various power conversion applications [1-3]. SiC devices have a higher band gap, electric breakdown field and saturated electron velocity than Si devices [4]. These material characteristics make the SiC devices more suitable for higher frequency and higher voltage operation. Among SiC devices, SiC MOSFETs are considered as an alternative of Si IGBTs. Compared with Si IGBT, SiC MOSFETs are unipolar devices and have no tail current during turn off transient [5]. Therefore, SiC MOSFET system aims to switch faster and operates at a higher frequency in order to achieve smaller size passive components and reduced system cost [6]. However, at present the fast switching speed capability of SiC MOSFETs has not been fully developed, one limitation of which is the present package technology. Large package
978-1-4799-5776-7/14/$31.00 ©2014 IEEE
stray inductance will induce excessive voltage and current stresses on the devices [7-9]. Besides that higher switching frequency may be inflicted with higher switching losses, which can considerably compromise the power efficiency, although SiC MOSFETs have fast switching capability. Therefore, decreasing the switching losses of SiC MOSFETs is a target in high switching frequency applications. SiC MOSFET has an intrinsic body diode, which, however, may not be a merit of SiC MOSFET due to its relatively high forward voltage drop and reverse recovery phenomenon. The high forward voltage drop could cause high conduction losses in the condition that the body diode works as a freewheeling diode. The reverse recovery current could cause extra switching losses. Consequently, in a bridge configuration, for instance three phase inverters and rectifiers, the usage of SiC MOSFET body diode is not recommended and an external anti-paralleled Schottky diode is suggested by the manufacture [10]. All the commercial SiC MOSFET power modules released by the manufactures use external anti-parallel SiC Schottky diodes. However, anti-parallel diode increases the total junction capacitance, which makes a contribution to switching losses, especially for high switching frequency applications. Moreover, during switching transient, the external diode may not prevent the body diode turning on due to the leakage inductance [11]. To avoid the body diode conducting current, the traditional solution is to put a diode in series with the SiC MOSFET and then parallel another external diode, as shown in Fig. 1 [12]. Using this method, two external diodes are required, which increases the semiconductor area, device cost and complexity of the system. Especially for power module, DBC (Direct Bonded Copper) area is larger with two external diodes and the layout design freedom is also limited. To fully utilize the fast switching capability of SiC MOSFETs and avoid the limitations of SiC MOSFET body diode in a bridge configuration, a split output topology was proposed [13-14].
Figure 1. Two external diode solution to blocking body diode
The salient merit of the split output configuration is that it decouples both the MOSFET body diode and the junction capacitance , which means that in half bridge these two SiC MOSFETs do not see each other directly. Besides that, the circuit design has more freedom compared to the traditional half bridge. The top SiC MOSFET and bottom one are not necessarily placed very near to minimize the stray inductance. The circuit stray inductance between these two switches is part of the leakage inductance which is needed in this topology. At present, however, there is no current commutation mechanism and experimental efficiency analysis in these existing literatures [13-14]. Before split output is applied in SiC MOSFET inverters and more application fields, a fully understanding of split output is required. Therefore, there is a need to make the current commutation mechanism and experimental efficiency analysis and validation. This paper attempts to cover the gap from topology understanding to power application. First is the description of the split output topology. Then detail current commutation mechanism of half bridge with split output is analyzed together with LTspice simulation. Afterwards, a double pulse test (DPT) circuit is employed to validate the current commutation mechanism analysis and test the switching losses. The DPT circuit has same current commutation process with the half bridge inverter and the device current of DPT circuit is convenient to measure. Half bridge with split output is also tested as a power inverter to make the efficiency comparison between traditional half bridge inverter and half bridge inverter with split output. II.
Split output could be achieved with a coupling inductor, as an example of Fig.2 (a). The equivalent circuit could be with three separate inductors, as an example of Fig.2 (b). Lf1 and Lf2 are effective leakage inductance of L1 and L2. The inductor core for Lf1 and Lf2 could be quite small or they could even be air core inductors in some applications, as the inductance could be quite small compared with the load inductance. Spit output topology could be applied to DC-DC converters and also DC-AC inverters. Half bridge is the basic cell of many converters or inverters. The analysis and experiment validation of half bridge could be applied in many other converters and inverters. Therefore, the analysis and experiment study in this paper is with half bridge based on the type shown in Fig.2 (b). B. Current Commutation Mechanism The half bridge split output current commutation mechanism is analyzed with the half bridge works as an inverter, as shown in Fig. 3. S1 and S2 are defined as the control signal of Q1 and Q2. S1=1 S2=1 means that Q1 and Q2 is on while S1=0 S2=0 means Q1 and Q2 is off. A typical control signal of Q1 and Q2 are shown in Fig. 4. In a half bridge inverter, it could be divided into two conditions according to the load inductor current (iL) direction. First condition is that the direction of iL is from left to right. In this condition, the current commutation process in the SiC MOSFETs, diode and inductors could be simulated with a DPT circuit, shown in Fig. 5. The DPT circuit could show the current commutation clearly, simply and exactly. According to the gate control signal in Fig. 4, the current commutation processes (red color) are shown from (a) to (f) in Fig.6. The simulation results are shown in Fig.7 to Fig.9.
SPLIT OUTPUT TOPOLOGY AND CURRENT COMMUTATION MECHANISUM
A. Split Output Topology Introduction Half bridge with split output is depicted in Fig.2.
Figure 3. Half bridge inverter with split output
(a) With coupling inductor (b) With separate inductors Figure 2. Split output half bridge.
Figure 4. Typical control signal
(a) Gate driver signal Figure 5. LTspice simulation model
b a
c
f d (a) S1=1, S2=0
a
e
(b) S1=0, S2=0 (b) Inductor current
(c) S1=0, S2=1
(d) S1=0, S2=0
(c) Device current Figure 7. Simulation results (e) S1=1, S2=0
(f) S1=1, S2=0
Figure 6. Current commutation process
Fig. 7 shows the overview current commutation process. Fig. 8 shows the dead time period simulation waveforms, which is corresponding to the process in Fig. 6(b). Fig. 9 shows the time period simulation waveforms corresponding to the process in Fig. 6(d) to Fig. 6(f). In t1 period S1=1, S2=0, current flows through Q1, Lf1, L and R, C, then goes back to the DC supply and DC capacitor, as shown in Fig.6(a), the current of Lf1 and L are identical iLf1=iL. The inductor and device current simulation results are shown in Fig. 7(b) and (c). In t2 period S1=0, S2=0, both Q1 and Q2 are off, which is the dead time. The inductor Lf1 has a tendency of keeping the current iLf1. Consequently, D1 turns on as a freewheeling diode. In the beginning of t2, uCDS2=uDC. CDS2 discharges to uCDS2 ≈ 0 through Lf2. Therefore, there is a current in Lf2 as in Fig. 6 (b). As the dead time is a short time period, iL could be
considered as a constant value. As CDS2 is only around hundred pF, it discharges quite fast. After CDS2 is fully discharged, iLf2 could not suddenly become zero, and it commutates to DQ2 in t2 period. Compared with iLf1, iLf2 is much smaller as this current is the freewheeling current from discharging the junction capacitance. The detail current commutation simulation results could be seen in Fig. 8. In t3 time period S1=0, S2=1, Q2 turns on and works in a synchronize rectifier mode. iLf2 starts to go through Q2. This process could also be seen in Fig. 6(c) and the simulation results are shown in Fig. 7. In t4 time period S1=0, S2=0, Q2 turns off. iLf2 commutates to DQ2 again, shown in Fig.6(d). The simulation results are shown in Fig. 9. In the beginning of t1 time period S1=1, S2=0, Q1 turns on. CDS2 needs to be charged to UDC by iLf2 as shown in Fig. 6(e). After CDS2 is fully charged, iLf2 commutates to D2, and goes back through Q1 and Lf1, as in Fig. 6(f). This phenomenon could be observed with Fig. 9(b) and Fig. 9(c).
(a) Gate driver signal
(a) Gate driver signal
(b) Inductor current
(b) Inductor current
(c) Device current
(c) Device current
Figure 8. Current commutation process of Fig. 6(b)
Figure 9. Current commutation process of Fig. 6(d)-(f)
The current iLf2 decreases below 0 and the current iD2 increases exactly the value of iLf2. There may be a case that the condition of Fig. 6(f) persists until t1 period is finished, and then there is no condition of Fig. 6(a). As shown in Fig. 7(b) and Fig. 7(c), most of the load current iL is commutated to the Schottky diode D1 when Q1 turns off. Schottky diode has no reverse recovery current, and its forward voltage drop is smaller than that of the SiC MOSFET body diode. Consequently, the switching losses of SiC MOSFETs are reduced. The conduction loss of Schottky diode D1 is smaller than that of the body diode of SiC MOSFET. In the applications where the body diode works as a freewheeling diode, both switching loss and conduction loss could be reduced with split output. But in the half bridge inverter, the conduction loss may not be reduced. Because dead time is very short, when the SiC MOSFET works in synchronous mode, the conduction loss of SiC MOSFET may be smaller than the Schottky diode. The conditions is that Ron*IQ < VF (IF=IQ). Ron is the on resistance of SiC
MOSFET. IQ is the current through the MOSFET. VF is diode forward voltage drop. The other condition is that the direction of iL is from right to left. In this condition, Q2 has a reduced turn on loss because of the absence of reverse recovery current of DQ1. D2 has a smaller conduction loss than that of DQ1 owing to its lower forward voltage drop than that of DQ1.The analysis is similar with the first condition and not repeated. The half bridge with split output working as an inverter is also simulated with LTspice. The simulation results comparison with that of traditional half bridge are shown in Fig. 10 and Fig. 11. It could be easily seen that the overshoot of device current in the traditional half bridge is much higher than that with the split output. (SiC MOSFET LTspice model does not include the body diode reverse recovery effect, but it has a 700pF junction capacitance integrated to generate the current overshoot which is similar with the reverse recovery current effect of the body diode.) Fig. 12 shows the output load inductors current comparison. It could be seen that there
(a) Top SiC MOSFET current simulation results
(a)Top SiC MOSFET and schottky diode current
(b) Bottom SiC MOSFET current simulation results
(b) Bottom SiC MOSFET and schottky diode current
Figure 10. Traditional half bridge inverter device current
Figure 11. Split output half bridge inverter device current
A. Double Pulst Test Circuit Experimental Study The validity of experiment study largely depends on the accuracy of measurement system, especially for current measurement. For SiC MOSFET, a high bandwidth current measurement method is required as the high switching capability of SiC MOSFETs [15]. In addition, small circuit leakage inductance is expected. The measurement equipment is selected as shown in Table 1. TABLE I. Figure 12. Output current comparison. Top one is the traditional half bridge output current and bottom is the output current of half bridge with split output
is little difference on the output current, which shows that split output does not affect output current performance but only has an influence on switching performance. III.
EXPERIMENTAL RESULTS
To verify the analysis in part II, hardware setup circuits are designed with SiC MOSFET (C2M0080120) and SiC Schottky (C4D20120) diode from Cree. The hardware circuits include DPT circuits and half bridge power circuits. The DPT circuit could show the current commutation process. Simultaneously, the SiC MOSFETs and Schottky diode current of the DPT circuits can be measured with high bandwidth current measurement methods. With the device current, the current commutation process could be validated intuitionally. The half bridge power circuits are used the make the efficiency comparison between the half bridge with split output and the traditional half bridge.
MEASUREMENT EQUIPMENT
Part No.
Descriotion
Bandwidth
Measured signal
DL9040
YOKOGAWA oscilloscope
500MHz
Pearson 2877
Current Monitor
200MHz
iD, iQ
Lecroy 100:1 passive probe
Voltage probe
400MHz
uDS
Pearson Current Monitor 2877 is employed as the current sensor in the DPT circuit. Two different circuits of half bridge hardware setups are designed. One is the traditional half bridge with external paralleled Shottky diode and the other one is the half bridge with split output, shown in Fig. 13. The switching losses comparison is between Q2 in half bridge with split output and Q4 in traditional half bridge. The hardware setup of the DPT circuit with split output is shown in Fig. 14.
Figure 14. Split output DPT circuit hardware setup
Figure 13. DPT circuit
Gate drivers of Q2 and Q4 have identical gate resistance. The experiment results of DPT circuits are shown in Fig.15 and Fig.16. Fig.15 shows the waveforms of Q2 and Q4 during turn on transient. Fig.16 shows switching waveforms comparison of Q2 and Q4 during turn off transient. Leakage inductance of these two circuits could be calculated [16], 79nH and 71nH, respectively, which means the circuit stray inductance does not bring large difference. Although, an external Schottky diode D3 is paralleled with Q3, the larger overshoot of Q4 current is still observed in Fig. 15(a) at Q4 turning on moment, which caused by the charging current of Q3 and D3 junction capacitance. As shown in Fig.15, Q4 turn on loss is 480µJ while turn on loss of Q2 is 350µJ. Q4 has around 37% larger turn on loss than 200V/div
that of Q2 due to its larger current overshoot. Q4 and Q2 have very similar turn off loss, as shown in Fig. 16. It indicates that by decoupling the body diode and junction capacitance, switching loss of SiC MOSFET in a bridge configuration could be reduced with split output. Fig. 17 shows the device current of Q1, D1 and Q2 in DPT of the half bridge with split output. Fig. 17(b) shows detail commutation process when Q2 turns off. In Q2 off period, iQ1 is only around 1A while iD2 is more than 30A. It indicates that most of load current iL commutates into D2. As the forward voltage drop of D2 is smaller than that of DQ1, in a condition that the body diode works as freewheeling diode, the converter may have a smaller diode conduction loss with split output.
10A/div
100µJ /div
iQ4
u
DS
Eoff=330µJ
20ns /div
(a) Turn on of SiC MOSFET Q4 in a traditional half bridge 200V/div
u
10A/div
(a) Turn off of SiC MOSFET Q4 in a traditional half bridge
(a) Current commutation process overview
100µJ /div Eon=350µJ
DS
iQ2
20ns /div
(b) Turn on of SiC MOSFET Q2 in a half bridge with split output
(b) Turn on of SiC MOSFET Q2 in a half bridge with split output
(b) Current commutation process during Q2 turn off
Figure 15. Turn on comparison between traditional half bridge and half bridge with split output
Figure 16. Turn off comparison between traditional half bridge and half bridge with split output
Figure 17. Current commutation process of half bridge with split output
B. Half Bridge Power Circuit Experimental Study Besides the DPT for current commutation and switching losses analysis, half bridge circuits as a power inverter are also designed to test the output and the efficiency analysis of the split output half bridge circuit. Fig. 18(a) shows the split output half bridge inverter hardware setup. Fig. 18(b) is the traditional half bridge inverter hardware setup. As seen in Fig.18, there is no need to place the top SiC MOSFETs and bottom SiC MOSFET very close as what it should be in the traditional half bridge. This is another merit with split output.
Figure 19. Output current of half bridge with split output
100
99
98 Efficiency [%]
Fig.19 shows the output current iR of half bridge with split output and the split output does not change the output current performance. Fig.20 shows the efficiency comparison at different switching frequency from 10 kHz to 100 kHz. The traditional half bridge has a higher efficiency at 10 kHz, which has been explained in Section II, the conduction loss of Schottky diode may be higher than that of SiC MOSFET working in synchronous mode. However, when the switching frequency is larger 25 kHz, the half bridge with spit output has a higher efficiency. And with the switching frequency increasing, the efficiency improvement with split output is larger. At 50 kHz, the peak efficiency with split output is improved by 0.31%. At 100 kHz, the peak efficiency with split output is improved by 0.5%. It indicates that the circuit with split output has a lower switching losses and the topology with split output is suitable for high switching frequency applications.
10k
97
Hz
25k Hz
96
50k Hz 75k
95
100
Hz
kHz
94
93
0
5
10 15 Output RMS current [A]
20
25
Figure 20. Efficiency analysis at difference switching frequency
IV.
(a) Half bridge inverter with split output
(b) Traditional half bridge inverter Figure 18. Half bridge power inverter with split output
CONCLUSION
The split output topology aims to decouple the SiC MOSFET body diode and junction capacitance. By the decoupling, the high forward voltage and reverse recovery current of the body diode is avoid in a half bridge with split output. Current commutation process analysis and efficiency analysis of split output half bridge based on SiC MOSFETs are made in this paper. According to the analysis and simulation results, during the switching period half bridge with split output could decouple both the body diode and junction capacitance of SiC MOSFETs. Consequently, in a half bridge with split output, the SiC MOSFETs could have a reduced switching loss compared to the traditional half bridge topology. The DPT circuit experiment results shows that the turn on loss of SiC MOSFET in a half bridge with split output is smaller than that in a traditional half bridge. The power inverter experiment results show that the efficiency improvement with split output at high switching frequency (above 25 kHz). The experiment results verify the analysis and indicate that the split output is suitable for high switching frequency applications. With the switching increasing, the more efficiency improvement of split output could be achieved.
REFERENCES [1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
O. Mostaghimi, N. Wright and A. Horsfall, "Design and performance evaluation of SiC based DC-DC converters for PV applications," in IEEE 2012 Energy Conversion Congress and Exposition, 2012, pp.3956-3963. T. Zhao, J. Wang, A. Q. Huang and A. Agarwal, "Comparisons of SiC MOSFET and si IGBT based motor drive systems," in IEEE 2007 Industry Applications Conference, 2007, pp. 331-335. S. V. Araujo and P. Zacharias, "Perspectives of high-voltage SiCsemiconductors in high power conversion systems for wind and photovoltaic sources," in IEEE 2011 European Conference on Power Electronics and Applications, 2011, pp. 1-10. B. Ozpineci and L. Tolbert, “Comparison of Wide-Bandgap Semiconductors for Power Electronics Applications.” United States. Department of Energy, 2004. J. Biela, M. Schweizer, S. Waffler and J. W. Kolar, "SiC versus Si— Evaluation of Potentials for Performance Improvement of Inverter and DC–DC Converter Systems by SiC Power Semiconductors," Industrial Electronics, IEEE Transactions On, vol. 58, pp. 2872-2882, 2011. Cree application note, "Design Considerations for Designing with Cree SiC Modules," Under “Power Application Notes” at Www.Cree.Com/Power/Document-Library, pp.1-20, 2013. H. Li and S. Munk-Nielsen, "Detail Study of Silicon Carbide Switching Characteristics," in 5th IEEE International Symposium on Power Electronics for Distributed Generation Systems, 2014, pp. 1-5. Zheng Chen, D. Boroyevich and R. Burgos, "Experimental parametric study of the parasitic inductance influence on MOSFET switching
[9]
[10]
[11]
[12]
[13]
[14] [15]
[16]
characteristics," in Power Electronics Conference (IPEC), 2010 International, 2010, pp. 164-169. S. Safari, A. Castellazzi and P. Wheeler, "Experimental study of parasitic inductance influence on SiC MOSFET switching performance in matrix converter," in Power Electronics and Applications (EPE), 2013 15th European Conference On, 2013, pp. 19. B. Callanan, "Application considerations for silicon carbide MOSFETs," Under “Power Application Notes” at Www.Cree.Com/Power/Document-Library, pp. 1-6, 2011. L. Balogh and T. Instruments, Design Review: 100W, 400KHz, Dc/Dc Converter with Current Doubler Synchronous Rectification Achieves 92% Efficiency. Texas Instruments, 2001. Gaoyao, Wang. Design, “Development and Control of >13kV Silicon-Carbide MOSFET based Solid State Transformer”, PhD dissertation of North Carolina State University. pp.26-27, 2013. Michael Frisch, Technical Marketing, Vincotech GmbH (Germany), "SiC MOSFET-based Power Modules Utilizing Split Output Topology for Superior Dynamic Behavior," 2013. Patrick Baginski, Field Application Engineer, Vincotech GmbH (Germany), "Power Modules with Split Output," 2013. H. Li and S. Munk-Nielsen, "Challenges in switching SiC MOSFET without ringing," in PCIM Europe 2014; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management; Proceedings Of, 2014, pp. 1-6. G. Laimer and J. W. Kolar, "Accurate measurement of the switching losses of ultra high switching speed CoolMOS power transistor/SiC diode combination employed in unity power factor PWM rectifier systems," in Proc. PCIM, 2002, pp. 14-16.
