Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014
1
Simplified FPGA implementation of the generalized space vector pulse width modulation (GSVPWM) for three wire three-phase inverters Jos´e Restrepoa,b,c, Julio Violaa,b , Flavio Quizhpib a
Prometeo-SENESCYT, Quito-Ecuador Universidad Polit´ecnica Salesiana, Cuenca-Ecuador c Universidad Sim´on Bol´ıvar, Caracas-Venezuela email:
[email protected],{jviola, fquizhpi}@ups.edu.ec b
Abstract—This paper presents the development and implementation on a low-cost FPGA, of a fast generalized space vector pulse width modulation (GSVPWM) scheme. The implemented pulse width modulation uses a standard carrier-based triangle interception method (SPWM).
I. I NTRODUCTION The widespread use of advanced microprocessor and field programmable logic array (FPGA) is providing industry and academia with low cost access to high-performance reconfigurable devices for its use in digital controllers for power electronics applications. Most of these applications need to control a power stage, composed of an array of power-switches (power BJTs, power MOS, IGBT, etc.), such as the three phase converter shown in Fig. 1. There are different ways to link the digital controller and the power stage, and for three-phase converters the most common linking unit is a pulse width modulation (PWM) module. There is large amount of research, done since earlier works in speed drives by Schonung [1], on different ways to produce efficiently the signals of the PWM module. Injecting zero sequence components is one of the most important improvements of the PWM module, leading to an increased dynamic range of the modulator. Later, the space vectors theory provided another extension, with the concept of space vector pulse width modulation (SVPWM). However, this modulation technique imposes a large computational load on the central processing unit. Modern industrial processors include PWM modules, freeing the central processing unit of the burden of producing the gating signals for the power stage. However, hardware solutions for advanced space-vector techniques are not available at the moment. Thus requiring additional processing time devoted to calculate and carry-out the algorithms for these advanced techniques; several algorithms does not even use the standard carrier-based triangle interception method found in most modern processors. This paper proposes the implementation of the GSVPWM algorithm, into a low cost FPGA, a Xilinx Spartan 3 (XC3S200). This algorithm has the advantage of changing modulation strategies by just changing a parameter known as null vector ratio δ, as described in the next section.
AH
VDC
BH
A
CH
BL
AL
C
B
CL
GN D
Fig. 1: Typical three-phase three wire voltage source inverter.
A. Generalized Space Vector Pulse Width Modulation The three-phase three wire converter shown in Fig. 1 has only 8 valid states, ~v0 to ~v7 as shown in Fig. 2, out of the 64 possible states. Using pulse width modulation, the voltage at each phase can take any value in an averaged sense in the range [0 → VDC ], and with transformation (1), this will produce a space-vector with coordinates falling inside the hexagonal area shown in Fig. 2. Modern control algorithms use a space vector description of state variables such as currents, voltages, or fluxes. The following transformation [2], [3], known as Clarke transformation, is commonly employed in three phase systems. f~ = ξ fa a0 + fb a1 + fc a2 , where a = ej 2π 3 , and ξ usually takes the values 1,
(1)
2 3
or
q
2 3.
The voltage demand for each phase of the converter can be normalized by ξVDC , the resulting space-vector, for lineal operation, falls inside the normalized hexagonal space shown
Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014
TABLE I: Typical modulation methods using the generalized algorithm.
y
replacements
~v3
~v2
~v ~v0
2
θ
~v4
~v1
x
γ 0 1 2 3
Modulation DPWMmax DPWMmin SVPWM DPWM0
4
DPWM1
5
DPWM2
δ 0 1 1 1 2 1 2
1 2 1 2
2 N1 1 + (−1)N
1 + (−1) (N1 +1) 1 + (−1)(N +1) 2
1 + (−1) 2 6 DPWM3 For (x, y) coordinates: N1 = 2.5 − sign(fy ) [(fx > fy ) + (fx > −fy ) + 0.5] N2 = 3.5 − sign(fx + 3fy ) [(fx > 0) + (fx > 3fy ) + 0.5]
~v6
~v5
Fig. 2: Representation of the space vector loci for the three phase converter.
Fig. 3a shows an example of the control signals that must be applied to the power devices in each branch when a PWM with central symmetry is used. In this example the average voltage space vector reference is such that Da < Dc , N1 = {5, 6}, branch b is in low state and the null vector is synthesized with state (0,0,0). In this case the possible firing sequences are:
in Fig. 2. The per unit vector is, ~vpu =vx + jvy = 1
1 VDC
vaN a0 + vbN a1 + vcN a2 =
(va − vN ) + (vb − vN ) a + (vc − vN ) a2 = VDC = D a + D b a + D c a2 , (2) =
where Da , Db and Dc are the duty cycles for the respective phases. Several works have been devoted to developing simple algorithms for generating the gating signal for the converter, conforming to different space-vector methods, the most common of which are, DPWMmax , DPWMmin , DPWM0 , DPWM1 , DPWM2 , DPWM3 , and the most widely used is SVPWM [4]– [10]. Since modern control strategies describe the state variables using complex notation in the form f~ = fx + jfy , the chosen algorithm should exploit this variable description, using x, y coordinates. The modulation method can be easily selected using a single parameter, known in literature with different names as: zero state partitioning ζ0 and ζ7 [5], parameter α [6], and null vector ratio δ [9]. The duty cycles for the VSI switches in the generalized vector based algorithm are obtained by doing the following change of variables in (2), fx = vx ;
vy fy = √ . 3
B. Examples of firing sequences
(3)
In this work the null vector ratio will be employed to select the modulation method. The variation of the null vector ratio δ, representing the zero state partitioning, during the switching period, yields an infinite number of modulation possibilities. The value of δ for most common modulation methods is shown in Table I [9]. The expressions for the duty cycles, as a function of the null vector ratio δ and of N1 in Table I, are shown in Table II.
firing sequence ~v6 → ~v5 → ~v0 → ~v5 → ~v6 ~v6 → ~v1 → ~v0 → ~v1 → ~v6 ~v6 → ~v0 → ~v6
condition Da < Dc Da > Dc Da = Dc
Fig. 3b shows an example of an average vector such that Da < Dc , N1 = {1, 2}, branch b is in high state and the null vector is synthesized with state (1,1,1). In this case the possible firing sequences are: firing sequence ~v7 → ~v4 → ~v3 → ~v4 → ~v7 ~v7 → ~v2 → ~v3 → ~v2 → ~v7 ~v7 → ~v6 → ~v7
condition Da < Dc Da > Dc Da = Dc
Fig. 3c shows an example of an average vector synthesized with N1 = 2, and the null vector is equally synthesized using space vectors ~v0 and ~v7 . In this case the possible firing sequences are: firing sequence ~v7 → ~v4 → ~v3 → ~v0 → ~v3 → ~v4 → ~v7 ~v7 → ~v4 → ~v0 → ~v4 → ~v7 ~v7 → ~v3 → ~v0 → ~v3 → ~v7 ~v7 → ~v0 → ~v7
Da Da Da Da
condition < Dc < Db < Db = Dc = Dc < Db = Dc = Db
Fig. 3c shows the case when δ = 12 and Da < Dc < Db . Figs. 4a-4c show the typical duty cycles required to produce a maximum amplitude circular trajectory of the voltage space vector for the three previously discussed methods [10]. The circular trajectory is generated in the (x, y) plane using the following expression, √ 3 jωt ~vpu (t) = vx + jvy = e . 2
(4)
Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014
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TABLE II: Expressions for duty cycles required in the practical implementation of the generalized algorithm. N1 0 1 2 3 4 5
~ v6
~ v5
~ v5
~ v0
Da δ(fx + fy − 1) + 1 Db + fx − fy Db + fx − fy Dc + fx + fy Dc + fx + fy δ(fx − fy − 1) + 1
v6 ~
~ v7
Db Da − fx + fy δ(2fy − 1) + 1 δ(−fx + fy − 1) + 1 Dc + 2fy Dc + 2fy Da − fx + fy
~ v4
1 D2b D2c
1 D1c
~ v4
~ v7
~ v7
~ v4
~ v3
Dc Da − fx − fy Db − 2fy Db − 2fy δ(−fx − fy − 1) + 1 δ(−2fy − 1) + 1 Da − fx − fy
~ v3 ~ v3 v0 ~
v4 ~
~ v7
1 D3b D3c
D1a D1b
D2a t0
t1
t2
t t5 t0 + Ts
t4 Ts /2
t0
(a) Generalized method with δ = 1
t1
t2
t D3a t0 t5 t0 + Ts
t4 Ts /2
(b) Generalized method with δ = 0
t t1 t2 t4 t5 Ts /2
t0 + Ts 1 2
(c) Generalized method with δ =
Fig. 3: Firing sequence for a PWM with central symmetry.
1 D1c
1
0.8
Duty Cycle
Duty Cycle
D1b
0.6 0.4
Duty Cycle
D1a
1
0.8 0.6 0.4 0.2
0
0 0.04
0.06
Time (s) (a) Duty Cycle for δ = 1
0.08
0.1
0.4
0 D2a
D2c 0.02
0.6
0.2
0.2
0
0.8
0
0.02
0.04
0.06
0.08
Da
Dc
D2b 0.1
0
0.02
0.04
Db
0.06
0.08
0.1
Time (s)
Time (s) (b) Duty Cycle for δ = 0
(c) Duty Cycle for δ =
1 2
Fig. 4: Modulation waveform for a maximum amplitude circular trajectory of the inverter voltage space vector in SVPWM with (a) δ = 1. (b) δ = 0. and (c) δ = 12 . C. Over-modulation Any per carrier period average space vector located outside the hexagonal area is not achievable with the VSI shown in Fig. 1, since the demanded duty cycles are outside the operational range of the modulator. The space-vector falling outside the hexagonal area, in Fig. 2, needs to be adjusted for proper operation of the modulator circuitry [5], [11], [12]. There are several possible ways to adjust the duty cycle demand to be fed to the modulator circuitry. A simple approach is to clip the per phase requested duty cycle to be inside the range 0%-100%. Another option is to clip the space vector magnitude to the maximum achievable by the converter, while keeping the reference voltage space vector angle; this limiting strategy corresponds to the over-modulation in mode I, described in [11]. Fig. 5 shows the effect of using these two
limiting strategies when the required voltage space vector falls outside the hexagonal area. This work uses the field weakening over-modulation strategy proposed in [12], corresponding to ~vr2 in Fig. 5. II. FPGA
IMPLEMENTATION OF THE
GSVPWM
ALGORITHM
The duty cycle generation for the GSVPWM algorithm presented in the previous section is implemented using the industry standard hardware description language VHDL [13], [14], the block diagram of the duty cycle algorithm for the GSVPWM is shown in Fig. 6, made of 3 main units, in charge of intermediate computations required by the algorithm. The first unit receives the normalized demands for the x and y components of the space vector, and generates the following
Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014
y ~v3 ~vr2
~v ~vr1
θe θ
~v1
x
~v5
Fig. 5: Limiting strategies for overmodulation showing the required space vector ~v and the resulting vectors using rescaling ~vr1 and clipping ~vr2 . γ fx intermediate variables fy
δ select
δ=0 δ=1 δ=
Range
Scaling
[Da , Db , Dc ]
Output
1 2
Fig. 6: Block diagram of the GSVPWM.
intermediate signals, using the fixed point VHDL language [14] with the ieee proposed library [15]. k1
