SIMULATED PROFILES FROM LAYOUT - EECS Berkeley - UC Berkeley

SIMPL-2 (SIMULATED PROFILES FROM LAYOUT) VERSION 2

by

K. Lee

Memorandum No. UCB/ERL M85/55 3 July 1985

SIMPL-2 (SIMULATED PROFILES FROM LAYOUT

-

VERSION 2)

by

K. LLE

Memorandum No. UCB/ERL M85/55

3 J u l y 1985

SIMPL-2 (SIMULATED PROFILES

FROM LAYOUT

-

VERSION 2 )

by K. Lee

Memorandum No. UCB/ERL M85/55 3 July 1985

ELECTRONLCS RESEARCH LABORATORY

Coll ege o f Engineering University o f California, Berkeley 94720

SIMPL-2 (Sl'ulated

-

Aofiles from the Layout version 2) Keunmyung Lee

Ph.D. Dissertation

Department of Electrical Engjneering and Computer Sciences University of California, Berkeley,California 94 720, U.S.A.

SI!MPL is a computer-aided design (CAD) tool for simulating the cross sectional profile of integrated circuits along an arbitrary 'cut-line' drawn on the layout. The second generation of

SIMPL. SIMPL-2 is capable of

process effects such as the 'bird's-beak.'

displaying in color two-dimensional

lateral diffusion. undercur in etching and

sidewall coverage in deposition. based on i t s linked-polygonal and grid t y p daubases. The device profile from the composite process can be generated r a ~ i d i \using ~ elrmentary internal physical proccss models. More rigorous external process simula~orscan also be invoked through an interface for profile data and transfer of control. .4n external process simulator. SAMPLE. is successfully linked to SIXlPL-2 for the deposition process. As of now. the other processes are done by internal routines. However. these modules

are easily detachable and the other external simulators can be linhed for more rigorous simulation. SIMPL-2 thus acts not only a s a color display tool for othet simulators but also provides a here-to-fore missing link between layout based C.4D tools and proc-es.s and device simulators.

FOP tbe graphics interface. SIMPL-2 uses

a

device-independent graphics package.

MFB (Model Frame Buffer). The color and pattern information for each layer of layout and cross section is mored in a readable file and can be modified.

I

SIMPL-2 consists of about 12.500 lines of C codes excluding MFB and the external

proccss simulator. C u m t l y . SIMPL-2 runs on

a VAS11/780 with Berkeley UNIS

4.2BSD.

ComAittee Chairman

2

SIMPL-2 (SIMulated Profiles from t h e Layout Copyright

@

1985

bY

Keunmyung Lee

- version

2)

i

Ded icated to my parents, brother and sister

11

Acknow ledgernents I would like to thank m y advisor Professor Andrew R. Neureuther for his guidance. encouragement, and friendship throughout this research. I also wish to thank Professors

W . G. Oldham. D. A. Hodges. J.

R. Whinnery. and E. J.

Pinney for serving on m y disser-

tation committee.

1 wish to thank my colleagues in the SX.MPLE group. It has been a unforgettable experience to work with them. I thank Gin0 Addiego. Sharad Sandgaonkar, Paul Carey, Mike Grimm, Yoshi Sakai. Mike Rosenfield. the late John Reynolds. Wendy Fong. Iludy Damar. Wing Leung. and Deok

Kim for their support and friendship.

I t is a pleasure to acknowledge the contributions of Peter Moore and Professor .A. K . Newton on the last stage of this work. I wish to thank Soo-Young Oh and John \ l o i l a t HewletL-Packard Laboratories for their advice during m y work at the laboratory which influenced this research. It was joyful to make friends with many people in Berkeley. I thank everyone of them for their help on my life. The financial support from SRC

is

gratefully acknowledged.

1 dedicate this dissertauon to m y parents. )-e 3lin and Hee h u n ~ Lee sister.

Myung Sun. and brother. h e u n Jae for their love.

. .

...

111

Table of Contents

Dedication

..........................................................................................................................

Acknowledgements ......_................................................................................................... Table of Contents ..............................................................................................................

CHAPTER

1 INTRODUCTION

1.1 Definition of SIMPL

1.2 History of SIlIPL

........................................................................................

................................................................................................

....................................................................................................

i

..

11

...

111

1 1

1

1.3 Dissertation Outline ................................................................................................

2

CHAPTER 2 SIJIPL-2 : .A CAD Tool for 1C CXD ..........................................................

3

2.1 IC CAD Environment ..............................................................................................

3

2.2 Functional Role of SIMPL-2 ...................................................................................

3

CHAPTER 3 PROGR.431 STRUCTLRE OF SI\IPL-2 .....................................................

6

3.1 Program Structure ...................................................................................................

6

3.1.1 General ..............................................................................................................

6

3.1.2 Layout ...............................................................................................................

6

3.1.3 I’rocess ...............................................................................................................

6

3.1.4 \lode1 Frame Buffer ( I l l 3 3 ) ..............................................................................

h

3.1.5 R u n n i n g ~ i t h o u kt i y h r c s ...............................................................................

h

3.2 1.ayout Data D a ~ aStructure ...................................................................................

X

3.3 Cross Section Data Structure ..................................................................................

10

3.3.1 General ..............................................................................................................

10

3.3.2 1-inked-Polygonal Data Structure ....................................................................

10

iv

3.3.3 Grid Data Structure ...........................................................................................

14

..................._..............................................................................

14

3.4 Graphics Interface 3.4.1 MFB

..................._....................... .......................................................................

14

3.4.2 Routines for Graphics Interface .......................................................................

14

CHAPTER 4 PROCESS SIML'LATIOIV ............................................................................

16

4.1 General

.....................................................................................................................

16

4.2 Internal Process Simulators ....................................................................................

16

4.3 Interaction with External Process Simulators .......................................................

16

4.3.1 Interface with SX.ZlPLE

...................................................................................

17

4.3.2 Interface with t h e Other External Process Sirnulators ...................................

17

CHAPTER 5 ISTERSAL PROCESS SIMCLATORS ........................................................

20

5.1 General

.....................................................................................................................

20

5.2 Photo-Lithography Process .....................................................................................

20

5.2.1 General ..............................................................................................................

20

5.2.2 Photo-Resist Coating ........................................................................................

20

5.2.3 Exposure ............................................................................................................

21

.....................................................................................................

23

5.2.5 Shortcut for the I'hoLo-Lithograyhy Proces5 ..................................................

23

5.2.4 Development

5.3 DeposiLion Process ...................................................................................................

5.1 Etching Proces ........................................................................................................

96

5.5 Oxidation Process ....................................................................................................

27

5.6 Ion Implantation Process ........................................................................................

29

CHAPTER 6 FUTLRE EXTESSIONS 6.1 General

..............................................................................

.....................................................................................................................

32

32

V

6.2 Interaction with Other Simulators ............................ ..... ........................................

32

..........................................................................................................

33

CHAPTER 7 EX;A&IPI,E RUNS

............ ...........................................................................

34

7.1 Berkeley ChlOS Inverter

.........................................................................................

34

6.3 User Interface

i

7.1.1 Run Sheet of the Berkeley CMOS IC

...............................................................

7.1.2 Simulation by SIMPL-2 ...................................................................................

7.2 DRAM Cells

34 41

............................................................................................................. 50

References ..........................................................................................................................

53

I

Appendix : SIXlPI.-2 User Guide ......................................................................................

57

CHAPTER 1 INTRODUCTION

Q 1.1 Definition of SIMPL SIMPL (SIMulated Profiles from the Layout) is a computer-aided-design tool for integrated circuits which automatically simulates the cross sectional view of integrated circuits along an arbitrary 'cut-line' drawn on the layout. For a given layout. SIMPL extracts the mask information from the intersections of the layout geometries with the specified cut-line. Using this layout information. SIMPL generates the evolution of cross sectional structure according to the process steps given to SIiLlPL interactively or in batch mode.

0 1.2

History of SIMPL The first generation of SIhlPL. SI3lPL-I [Grim83]. was developed in 1983. The

main object of SIMPL-1 was to give rapid on-line visual feedback t o the circuit designer

a s to the topographical features being created during layout.

For this application.

SIhlPL-1 approximates the cross section with rectangles based on the linked-rectangular database. and uses very simple cne-dimensional process models. SllIPL-I takes the layout information in the CIF [Mead801 format and outputs t h e cross section in CIF. Thus. it is possible to use a layout graphics editor which understands CIF file format to d r a b

the cross section output such as KIC [KelISl]. The second generation. SIJIPL-2. which

IS

the topic of this dissertation. simulates

t h e cross section with two-dimensional e f f e c ~such s as the

undercut

in

"

bird's bzaA.." laterai diffusion.

etching. and sidewall co\.erage in deposition.

-1.a

include the two-

dimensional effects. a quantum leay, from Si\ll'l.-1 b a s necexsar).. .A neu darrr structure has been deLiised a n d implemented. SIJlI'1.-2 supports

LWO

hinds of tiatabases: a linhed-

polygonal database and grid type database. Another feature of SIhIPL-2 is that its database and modular program structure make it possible to connect external process and device simulators. As of now. the process simulation program. S.4JU'I-E [Oldh 791.

1

2 [OldhBO]. is connected to SIMPL-2 for the deposition process. A convenient user interface is also implemented using the device independent graphics package MFB (Model Frame Buffer) [Bi1183].

8 1.3 Dissertation Outline The position of SIMPL-2 in the environment of IC CAD is discussed in Chapter 2. Chapter 3 discusses the program and data structure of SIIMPL-2 including the graphics interface. Chapter 4 describes how the process simulations are and can be done with the internal and external simulators. Each of the internal process simulation modules are described in detail in Chapter 5 . The directions of future extension of SIMPL are discussed in Chapter 6. Example runs of SIhIPL-2 are presented in Chapter 7 . The appendix includes the user guide of SISIPL-2.

CHAPTER 2 SIMPL-2 :A CAD Tool for IC CAD

0 2.1 IC CAD Environment As integrated circuit technology advances. computer-aided-design

and computer

simulation become imperative in the area of the device and process design as well as circuit and system design. Fig.2-1 shows the overall CAD environment for integrated circuits. When a system specification is given, the system is partitioned into several blocks according to their functions. Circuit designers implement the functional blocks with circuit elements. The circuits are simulated and modified through two loops: at first without layout consideration. and then with layout. These two iteration loops are shown in Fig.2-1 on the left and right. respectively. Another necessary CAD effort is necessary in device design which starts from the bottom in Fig.2-1.

This path determines the physical characteristics of each element

fabricated in the integrated circuits. As a process sequence is given. the process is simulated and modified along with the exprimental feedback. The devices fabricated from the process are characterized and the resulting models are supplied t o the circuit simulator as shown in Fig.2-1 by means of the dotted line. The final layout and process steps are determined by these two main paths: one which starts from the system specification and the other from the process specification. § 2.2 Functional Role of SIMPL-2

.As discussed in

9

2.1. the process and device simulation Fro\,ides the electrical

characteristics for the circuit simulation. llost of the two-dimensional process and device simulators such as SA3II’LE. SUPRA [ChinS2]. \IISI\~lOS [SeibhO]. and ~ E \ l I ~ I

[GreeSO] do not utilize layout information for their simulations. HobeL.er. as the integration level becomes denser. layout affects the circuit performance drastically and must be taken into consideration. To include the effects of layout inLo the process and device simulation. a full three-dimensional approach is necessary. OYSTER [KoppS31

3

4

ISYSTEM r

SPEC I F.JCAT I ON i

JCIRCUIT

1

DESIGN]

CIRCUIT EXTRACTOR CIRCUIT SIMULATION

LAYOUT

$\ I

1

I

1

IDEVICE

S I M U L A T I O1N A

I PROCESS -------

SPEC I F I C A T 1 ON OLD PATH

=
Tgon. flash. u'ire. The semantics for Lhe geometries are defined

in

Introduction t o I'LSI Systems [Aleadbt)]. Each

element of t h e layout is tested against the cut-line. This test is done in a general way in order to hantile the cases like a slanted cut-line or rotated elcment. 11' the cut-line crosses an element. the layer name of the element and crossing points are stored in the string shown in Fig.3-2. The string is defined in C as follows.

9

m

'r

1

10

typedef struct Blockpair { float Left; float Right: struct Blockpair *Next: I BLOCKNODE. 'BLOCKPTR: typedef struct Masknode { char Name[NAME-LENGTH]: BLOCKPTR HeadPair: struct Masknode *Next:

1 MASRNODE. *MASKPTR;

MASRPTR

RtMask:

When the photo-lithography step occurs, the matching mask name is searched and the exposure is done with respect to the mask edges. Mask inversion is implemented to take into account the polarity of the photo-resist and mask as explained in

6 5.2.

0 3.3 Cross Section Data S t r u c t u r e 6 33.1

General

To store and manipulate the cross section. SIhlPL-2 defines t w o data structures. linked-polygonal and grid dara structure.

Q 3.3.2 Linked-Polygonal Data S t r u c t u r e The linked-Folygonal data structure is devised to handle arbitrary shapes of materials which are formed during the process. The linked-polygonal data structure is shown in Fig.3-3 and Fig.3-4.

Fig.3-3 shows a t>rpical doubly-linked polygon string.

Each node reFresents a polygon. I t contains the name of the pol>son. number of vertices. pointers to the nest and previous polxgons. and pointer

LO

a vertex node of t h e pol>.gon.

Fig.3-4 s h o w s the vertex string. Each node represents a vertex of a polygon a n d contains the coordinates of the vertex. There are three pointers to the null-terminated character strings. These character strings contain the names of the materials which are separated by the vertex. The third string is needed for the branching nodes. The three pointers

at

the bottom of each node p i n t to the next vertex of the CorresFonding material boundar!.

R t Po I ygon

L_r' >

Name Nvertex N e x t Po I ygon PrevPolyqon Headvertex

-1--

-~

( v e r t ex n o d e )

Name N v e r t e x __ NextPolyqon. PrevPo I yqon HeadVer t e x

-

( v e r t e x node)

> Name

Nver tex NextPolygonP r e v P o I ygon Headvertex

-

( v e r t e x node)

Fig.3-3 I)oubly-linkecl polygon string for the cross section.

12

fg.3-4 Linked polygonal data structure for the cross section.

13

when traversed in a clockwise fashion. In other words. you can trace the boundary of a material as follows. First. find the name of the material in the node. Then. if the name is in 'a', then go to the node pointed by the pointer 'a'- With this data structure. one can

easily keep track of the relative position of materials which is essential for the physical processing. The data structure defined in

C is as follows:

#define KAME-LENGTH 5 typedef struct Polygon { char Name[NAME-LENGTHl: int Svertex: struct Polygon *NextPo1ygon: struct Polygon *PrevPolygon: struct Vertex *Headvertex: 1 POLYGONSODE. *POLYGONPTR: typedef struct Coordinates { float x: float z: } COORDINATES: typedef struct Vertex { struct Coordinates xz: char a ~ ~ t r l [ N ~ ~ ~ E _ L E N G T H ] ; char bMtrl(NA~IE_LENGTH]: char c ~ l t r l [ S . ~ ~ ~ E L E N G T H ] : struct Vertex *a: struct Vertex *b: struct l'ertes *c: 1 VEHTESNODE. *l.ERTESPTR: POLYGONPTR

RtPol ygon:

There are two special names for VERTESSODE's. The name. ' A I R ' . is reserved for the nodes which are exposed to air. The other name. ' R ' i l I R ' (boundar).). is written on the nodes which are located on the left and right boundary of the cross section simulation window. These t w o names are useful for searching for the top layer during processing. The memory locations for these polygon and vertex nodes are allocated d>.namically

14

6 33.3 Grid Data Structure For a non-homogeneous area such as doped silicon and oxide region. a non-uniform rectangular grid is used. The grid is generated and deleted automatically as the process

evolves. SIMPL-2 initializes only a horizontal grid when a new simulation is started. During the etching. photo-resist development. and oxidation steps. new grid lines are added on the new vertices generated. And the grid lines which become void after the etching processes are deleted. The grid is described a s follows in C. Mefine N S 150 Mefine NZ 1 0 0 float impu[SZI[SS]; float x[NX]. zINZ]; float dx[NS-11. dz[NZ-11:

6 3.4 Graphics Interface

A device-indepndent graphics package. Model Frame Buffer (MFB). is employed for the graphics interface. The MFB package provides the user with a viriual graphics interface.

MFB performs the terminal dependent task of encoding/decoding graphics code,

thereby allowing the user to write graphics programs to execute on any graphics device.

h l F X X P is a database describing graphics terminals and is used t o adapt the output of M F B to a particular terminal. Terminals are described :n ME‘HCAP by defining a set of capabilities that each terminal has. and by describing how operations are to be performed. Currenriy MFl3C.Q enirles for t h e terminals such as Tektronls 4014, Tektronis 41 13. AI3I 512. AED 767. 111’ 2641j. 111’ 9872. HI’ 150. 2>Lc \.’TI25 are established. SI3IPL-2 has been developed on Ill’lSO and I’ektronis 41 13 terminals.

6 3.3.2 Routines for Graphics interface To execute SIMPL-2 in graphics mode. a file named ’ S I & W l s a t i e r n ’ is required. This file contains the fill pattern and color information for each materlal a n d mask layer

15

which will be displayed'on the screen. The layers described in this file are listed with their name on both sides of the screen. The format for each layer in the file is as follows.

NAME NWEL RGB lo00 1OOo 0 FILL 128 64 32 16 8 4 2 1 'NAME'. 'RGB'. and 'FILL' are the keywords for the material name, color code, and fill pattern. respectively. 'NAME' is limited to four characters. The three numbers following 'RGB' are the intensity of red. green. and blue colors normalized to 1000. For example. 1000 lo00 lo00 makes the color white. The fill pattern is defined with 8x8 bit pattern.

Each decimal number followed b) 'FILL' stands for the bit pattern of the

corresponding row. When SIMPL-2 is executed. SIMPL-2 uses the file. SIILlPLqattern. to load the color and pattern information in an internal string. The file. SIMPLqatterr.. also contains the color information for the impurity doping concentration.

-4 doubly linked string defined as follows in

c

is created when

SlRlPL-2 reads the file. SI31PLqattern. t y p d e f struct dopinaspectrum inL color: ini fill: float low; float high:

I

s1rucL dopingJpectrum *to_low: struct doping-spectrum 'to-high: D0PIUGSOI)E. *I)OPISGlJ'fR;

Assigning the color for ekes-> cell in the grid can be done !ast u . i r h this string since the doping change is gradual in most cases except across t h e junclions.

CHAPTER 4 PROCESS SIMULATION 9 4.1 General The main difference between SIMPL-2 and other process simulators is that SIMPL-2 is capable of simulating the entire IC process including.the affects of masking. While all the simulations are done by the internal simulation module in SIMPL-1 [Grim83]. SIMPL-2 is designed to simulate the process with external process simulators. The basic idea is when a process step is specified. SIMPL-2 transfers the current profile to the external simulator which will simulate the process step. then SIMPL-2 takes the resultant profile back and rebuilds a new data structure accordingly.

To carry out this job. the control of the external simulators should be transferred along with the profile data. In short. SIMPL-2 acts like the controller over the simulators a s well as the manager of the cross section database. SIXIPL-2 can simulate deposition. oxidation. etching. ion-implantation. and photo-lithography.

0 4.2

Internal Process Simulators Even though the overall design of SIMPL-2 is based on the philosophy described in

the previous section. SIMPL-2 maintains its own simulators due to the lack of suitable external simulators which can handle a general simulation window size. The inrernal process sirnulators are part of the program. however. these modules are separate from the

SIMPL-2 itself. Thus. when an external process simulator is a\.ailable !or a process step. sI\IPL-2 can be easily modified to incorporate t h e esrernai sirnulator. Ei..en thoun,h the internal process simulators are based on clemefitar!. models. the). still pro\ d e good cross sections. 'The physical model3 a n d managemen! {jf rhe database of the internal sirnulators are discussed in Chapter 5 . (s 4.3 Interaction with E x t e r n a l Process Simulators

10

4 43.1 Interface With SAMPLE Among the process simulation modules. the deposition module is f u l l y external except for the deposition with the vertical deposition option explained in $ 5.3. When the deposition of a material is need during the process, SIMPL-2 extracts the top contour

of the cross section as shown in Fig.4-1. SIMPL-2 builds a S X W L E input file with the extracted profile and other parameters and then executes SAMPLE by a UMX system call. "SYSTEM". SIMPL-2 supplies one of the two kinds of SAMPLE input parameters: one for the anisotropic deposition by sputtering source and the other for isotropic deposition. The etching machine in SA.MPLE is called with negative etch rate for the isotropic deposition.

SAMPLE generates two kinds of outputs. One is the standard output which contains the input information. rough resultant profile. and the run-time statistics. The other is the string point output of the deposited contour needed by SIMPL-2. S X W L E writes this graphics data into a file named 'f77punch7.' When the deposition is completed by SAMPLE. SIMPL-2 opens the f77punch7 file and reads the final contour. Then. the database is rebuilt with respect to the contour. To rebuild the database. first. a new

POLYGON node is generated and then the contour from SAMPLE is stitched with the initial toy contour to make the new polygon. The overall procedure

IS shown

in Fig.4-1.

The detailed pointer manipulation for the deposition is explained in t h e program source

code of deposition process and is not described in this dissertation. 4.3.2 I n t e r f a c e with t h e O t h e r E x t e r n a l Process Simulators

In this section. a s>.stematic way to ccnnect the esrernal simulators

is

discussed.

Every simulation program has its 0 u . n pe~ulidrit>for its specific application. l'his peculiarity includes the internal data structure. input and output format. This peculiarity deters the communication between simulation tools. SIlIPL-2 a t t e m p to be the cenLral h u b which connecu the simulators in an organized fashion.

CROSS SECTION DATA I N SIMPL-2

REBUILT CROSS SECTIOX DATA I N SIMFL-2

Fig.4-1 Data flow for the deposition simulation by SAMPLE.

19 Most of the simulation tools have grid type database or string type database. To communicate with these programs. SIMPL-2 has two kinds of data structures as discussed in

6 3.3. SIMPL-2

is f u l l y compatible with the external simulators which have

the string type database such as SAMPLE The polygons of SIMPL-2 database can be easily formed from the strings by linking them. The typical case is the deposition case in

6 4.3.1. More severe problems occur for the grid type database. Most simulation programs with grid type database have grids which are suitable for their awn specific need which is to increase computational efficiency and accurac)'. To connect a simulator with the grid type database. SIMPL-2 supports non-uniform rectangular grid. When the connection between SIMPL-2 and the grid type simulator is made. it is desirable to set up the grid in

SIAMPL-2LO resemble the grid the external simulator as much as possible. Hcwever. some data interpolation is unavoidable when the data in SISIPL-2 is to be transferred t o another external simulator. Besides the structural data stored in SIXIPL-2. generally more information such as simulator commands and coefficients must be suppiied to the external simulator. These can easily be handled by implementing a direct channel through SI1\IPL-2. The channel. however. should be exclusively designed for each external simulator. For the kinds of data described above. it

is

better to transfer data through files. and

not in an internal data array. The file-to-file interface is the best way to comnunicate The file-to-file interface also gives the freedom to replace external simulators .withour corn pi ica t ion.

CHAPTER 5 INTERNAL PROCESS SIMULATORS

4 5.1 General In this chapter. the internal process modules are discussed in detail. The physical models used by the internal simulation are rather primitive. However. the string and grid management algorithms which are used to implement those physical models are applicable to more elaborate physical models. Along with the physical models for the processes, the string and grid management routines are also discussed in each section.

6 5.2 Photo-Lithography Process 6 5.2.1 General in a real lab environment. the photo-lithograpii>~process consists of photo-resist coating. exposure and development. SIMPL-2 simulates these three process steps using

‘DEPO’. ‘ESPO’. and ‘DEVL‘ modules. Each process simulation steF is explained in the following sect ions.

0 5.2.2

Photo-Resist Coating

When a photo-lithography step occurs during a sequence of processes. photo-resist

is first coated on the wafer. The photo-resist coating is carried olit by the deposition module with the isotropic deposition option. In interactive mode. the photo-resist coating

IS

done as follows.

In the example above. the photo-resist named ‘KS7”

IS

coated isotropically with the

thickness of l p m . The polarity of the photo-resist will be raken into consideration in the development process.

21

0 5.23

Exposure

In the real physical exposure process. the exposed areas of the photo-resist to the unexposed region have a different development rate. Basically. the exposed photo-resist becomes a different material which characteri7ts itself when immersed into development solution.

The photo-lithography

development

process

rigorously.

machine in SAMPLE simulates the exposure and However.

connecting

SAMPLE for the photo-

lithography process is only possible by assuming t h e topography is locally uniform at each mask edge. This is because SAMPLE does not presently allow photo-lithography process on non-planar layers.

sII\IIPL-2 simulates the photo-lithography step by changing the material name for portions of the photo-resist which are exposed. In interactive mode. the exposure process is executed as follows.

WHICH PROCESS 7 E S P 0 WHICH MASK ? NWEL INVERT THE MASK (yes or no> ? no SAVE OF THE EXPOSED RESIST ? ERST DO Y-OL WXST TO DRAW THE CROSS SECTIOS (yes or no) ? yes The exposure step above is a CMOS process step described in Chapter 7 . The exposure of the photo-resist is done with the mask XWEL(n-wel1) without inversion. The e s F s u r e module searches the top layer (photo-resist) and the top polygon is divided along the mask edges. The exposed portions are named a s 'ERST' (exposed-resist). This name is needed for the subsequeni development process. .A simple esaniple of string management lor rhe e s p s u r e srzr

IS

hown

in

F'ig.5-1.

The original photo-resist is splii inlo fi\e poiyqons. in r h i s case into rectansles. .A. B.

I). and 1'.

c.

The eignL vertex nocies. 1 through h . are generated a n d inserted. For each

polygon. the vertices are linked together along the arrow shown in Fig.5-l(b). The

polygon A . C. and E keep the original photo-resist name. and B and D are named as specified by user. 'ERST' in the exposure example above.

22

PHOTORESIST \

i

I\

A

Fig.5-1 Simulation of exposure process.

23 § 5.24 Development The development process of photo-resist is simulated by removing the appropriate

polygons generated in the exposure step. The following example shows the development process in interactive mode.

WHICH PROCESS ? DEVL NAME OF THE LAYER TO BE DEVELOPED ? ERST DO YOU WANT TO DRAW THE CROSS SECTION (yes or no> ? yes The example above is the continuation of the examples in

8

5.2.2 and

6 5.2.3.

The

polygons na.med 'ERST' are deleted and the reserved word, AIR is written in the vertex nodes which are exposed to air by the development process as shown in Fig.5-2. Since the photo-resist used in the example is positive resist. the exposed areas are developed away in the development process. If the photo-resist happened t o be negative resist in the previous example. the answer to the second question would be 'RST' instead of

'ERST' and the unexposed areas of photo-resist would be developed away. The polarity of the photo-resist is taken in account in this way. Xew grid lines are added on the vertices which do not have grid lines crossing on them after the string management.

6 5.2.5 Shortcut for the Photo-Lithography Process When the patterned photo-resist is used a s the mask for etching without bias or undercutting. t h e overall process can be simplified. T h e processes. resist coating sure

-

development

-

material lo be etched)

etching

-

-

-

expo-

resist stripping can be substituted b) exposure (of the

etching a s explained below.

Since the exposure module changes the malerial name of the exposed area delineated b!.

the mask. the module can be used on the layer t o be etched u,itnout using ?hot\?-

resist. N o w . the mask pattern is transferred directl), t o the layer. U>.s i m p l y etching t h e patterned layer. the same effect as the original processes can be obtained. Fig.5-3(a) and ( b ) show the equivalence.

24

1 I I I

r I

I 1 I

I 1

-

I I

W

K

I

POSITIVE PHOTO. RESIST LAYER TO BE PATTERNED

(a)

LAYER TO BE

@

VERTEX NODES MPOSED TO THE AIR BY DEVELOPMENT PROCESS

Fig.5-2 Simulation of development process.

25

-

6 PHOTORESIST LAYER TO BE ETCHED

I

1 (a>

I

Fig.5-3 4 Shortcut for the photo-lithography step.

26

6 5 3 Deposition procesS When SAMPLE is not available for t h e deposition process. the deposition process can be simulated by the elementary internal model of SIMPL-2. The following is a deposition example with the internal model.

WHICH PROCESS ? DEPO NAME OF THE MATERIAL ? NTRD THICKNESS OF THE MATERIAL (micro-meter) ? 0.08 ISOTROPIC. ANISOTROPIC. OR VERTICAL (1. A. or V> ? V DO YOU WANT TO DRAW THE CROSS SECTION (yes or no> ? yes

In the example above. the internal deposition model is called by typing " V nfor the question. "ISOTROPIC. AXISOTROPIC. OR VERTICAL ( I . A . or 17) ?" The specified material is deposited only vertically.

6 5.4 Etching Process The etching process is another process which SAhIPLE is able to simulate IReyn791. As in the case of photo-lithography, the etching machine In SAMPLE works with p!anar cases which is t r u e for small simulation windows. For a large simulation window. the cross sectional structure is planar only for first few steps of the process before the layer become non-planar. For this reason. a elementary model for the etching process has been devised. The following examples show the two kinds of etching processes. WHICH PROCESS ? ETCH WHICII L.1YER DO YOC W A S T ETCH ? RST ETCH ALL (yes o r no) ? yes DO YOU \%'.\STTO DR.4W THl: ('ROSS SECTIOS ( y e s o r n o )

The first elample s h o u s the

LJW

of unmasked etching

' yes

'I'hz laher. 'CST'.

IS completel?

eiched. In t h i s case. the s t r i n g managemen1 of the p o l ~ g o nstrins and Lertex string is. simple. 'I'he polygons w i t h the specified name are deleted if they are esposed to air. Then the reserved word. AIR. is written in the vertex nodes which are now exposed to air.

WHICH PROCESS ? ETCH

WHICH LAYER DO YOU WANT ETCH ? NTRD ETCH ALL (yes or no> ? no AMOUNT OF VERTICAL ~ C (micro-meter) H ? 0.1 R.4270 X/Z O F ETCHING (0.0 .as follows.

U’IIJCH PROCESS OSID OSJDL TlIJCh\ESS (micro-meter) 7 0.05h N t (micro-meter) 7 0.0Sb >;e (micro-meter) 3 0.029 ul ? 0.1 u2 ? 0.5 u 3 ? 0.9 df ? 0.1 d 2 ? 0.5 d 3 ? 0.9

2h

LAYER TO BE ETCHED \I(

. c

Fig.5-4 Simulation of etching process.

29

DO YOU WANT TO DRAW THE CROSS SECTION (yes or no> ? yes The OXIDE THICXNESS is the thickness of oxide resultant from t h e oxidation process on the bare substrate. If there is an oxide layer before oxidation. Ut and Dt in Fig.5-5 are approximated by

Ut = ~ U 1 2 + ( c u Tl2o ,

(5.4a)

D, = J D l * + ( @ T Ol2 ,

(5.4b)

where To, is the given OXIDE THICKNESS on the bare substrate.

CY

and /3 are the frac-

tions of oxide thicknesses grown upward and downward from the initial substrate surf ace, respectively St is the total bird’s beak length and Xe is the length of encroachment as shown in

Fig.5-5.

u 1. u z . u 3 , d 1. d z . and d , are defined

as follows.

where I/ 1 . 012. l i 3 . D1.Dz.and D 3 are defined in Fig.5-5. The new verfes nodes generated during the oxidation process are marked by x’s in Fig.5-5. There can be previously existing vertes nodes between these neu nodes. In this case the existing nodes are moved to points calculated b!. adjacent node5

\ew

linear interpolation of the t w o

grid lines are added on the \ertlce< u hic!i do not

lid\?

:rid

lines

crossing on them after the string management.

4 5.6 Ion Impiantation Process The rigorous simulations for the doping process are available [Duffti I ] . [RyssOO]. However. SIMPL-2 supports its own internal ion implantation module because of the limited window size of those simulators. The ion implantation Frocess is simulated w i t h

30

I

A

\I,

I

t I

I

f

I

t,

I I

I, 1'

A

Ut V

..

Fig.5-5 Simulation of local oxidation process.

31 the following information given by the user.

WHICH PROCESS ? IMP& IMPLAhTATION TYPE ( p or n > ? n DOSE (cm**(-2)) ? 1.OeC12 STANDARD DEVIATION (micro-meter) ? 1.5 PEAK DEPTH (micro-meter) ? 0.0 BLOCK THICKNESS (micro-meter) ? 0.1 DO YOU WANT TO DRAW THE CROSS SECIION (yes or no) ? yes The model used in SIMPL-2 is a Gaussian distribution. The implanted profile is approximated by

where N is the implanted dose. R; is the projected range. and AR is the projected standard deviation. Since SIXIPL-2 does not have a module for thermal annealing. the final profile after any thermal steps should be approximated by a Gaussian. The BLOCK THICKNESS is the thickness of oxide that implanted ions cannot fully penetrate. For a given BLOCK THICKNESS.SIMPL-2 searches the areas where the bare substrate is exposed or where the oxide is thinner than the BLOCK THICKNESS. Also.

SIMPL-2 assumes a complete 'block' by other materials covering the surface. Before the impurity concentration is calculated for the implanted region. veriical grid lines are added near the implantation mask edges. After the new grid is formed. the implanted dose is super-imposed on the original doping concentration. Lateral diffusion is apFroximated by the same Gaussian distribution decaying radially from the implantation mask edges. T h i s is a crude approximation i o be used unLil a suitable two-dimensional simulator which can treat large simulation windous is a \ ailable.

CHAPTER 6

FUTURE EXTENSIONS

9 6.1 General The first form of SIMPL-2 has been established.

However, there are numerous

ways to expand and improve the simulation capabilities of SIMPL-2. The main directions are connecting ‘rigorous process simulators. device simulators. and electrical parameter extractors to SIMPL-2. Another area of interest is the improvement of the user interface.

0 6.2

Interaction with Other Simulators -4s indicated through out this dissertation, the internal process simulation modules

are to be exchanged with external ones. There are some prime candidates to be linked to

SIMPL-2. The photo-lithography and etching processes can be simulated by S X W L E when SAMPLE extends i t s capabilities to simulate non-planar cases. SAhIPLE may exploit the data structure of SIMPL-2 for the non-planar problems. The separation of

S A I P L E into individual processes and the file-to-file interface are desirable [Nand841 for the connection to sIx.lPL-2. For two-dimensional oxidation and diffusion process simulations. programs such as BICEPS [Penu83]. SOAP [Chin83b]. “-A Universal TwoDimensional Process-Simulation Program [Lore84]” are good candidates. However. these programs should be able to simulate large areas. before they can optimally interact with

SIAIPI.-2. When these connections are made. SI\lPL-2 will become an indispensable tool to eqtablish neu ground rules lor ne% integrated circuit3 at their initial stage o! develop-

ment. Elecerical parameter extraction

IS of’

sresl importance In the o\?rall (l.41) effort for

integrated circuits. Some preliminary work has been d o n e 1 o r parasitic capacitance and resistance [Lee82a]. [Lee82b]. [LeeS3]. The extension of these works to the level of

SIMPL-2 is of great interest. The extraction of electrical characteristic of active devices is usually done on a single device configured by a designer. The automation of this pro-

32

33 cedure through SIMPL-2 will be possible by cutting a single device. when SIMPL-2 is linked to rigorous simulators.

Is is desirable to set a standard format for the crcss section data file

used by the

simulators. The standard format provides smoother file-to-file communication between the simulators. EDIF (Electronic Design Interchange Format) [EDIF851 may be extended

to take into account the cross section data.

6 6.3 User Interface There is some room for improvements in the user interface of SIhlPL-2. For now, the commands are entered by typing in the key words in graphics mode as well as in non-graphics mode. The menu-driven command input is desirable in the graphics mode. The current command window at the bottom of the screen can be used for the menu display.

SIMPL-2 understands only layout files written in non-hierarchical CIF. because the sizes of layouts used by SIXIPL-2 are small enough to be written in non-hierarchical CIF. However. hierarchical parsing of CIF files is needed to simulated a portion of large layout genera 11y .

CHAPTER 7 EXAMPLE RUNS

8 7.1 Berkeley CMOS Inverter 7.1.1 Run Sheet of the Berkeley CMOS IC This section lists the CMOS process sequence developed by Y. Sakai. P. Carey. and

K. Terrill. The simulation of cross section along layout with this process is presented in

a horizontal cut-line over an inverter

Q 7.1.2.

THE NEW BERKELEY CMOS PROCESS

June 6 . 1982 Rev.1 Yoshi Sakai June 6 . 1983 Rev.2 Paul Carey Aug 20. I983 Rev.3 Kyle Terrill

(Implant doses determined) Jan 5 . 1983 Rev.4 L y l e Terrill (New PRIST technique added)

A. INITIAL WAFER PREPXR.4TION 1. Standard Wafer Cleaning ( TCA Scrub , acetone. methanol)

2. Piranha Clean

15 min.

B. INITI.4L OSIDXTIOS (1) 1. Water Break Test

( TCA clean furnace before using )

t u :DL 1 : i o

2. 1000' C Dr> 0 2 5 1 min. SS n m 3 Switch

LO

3 2 for 10 min.

4 . Oxide Thickness \leasuremenr

1. Nitride Deposition

- 500 .A

80 nm

2. Nitride thickness measurement

3. Piranha

(push in 0 2 )

5 min (optional)

35 4. Standard Photo-Lithography [ Mask- MNWL(Mask N-WeLl)]

5. Nitride Dry Etch

PLASMA THERM ELECTRODE ON TOP PLATE POWER 100 Watts FLOW SF6102 2012 PRESSURE (plasma on 1 50 m T TEMP 65°C RATE 0.022 micron per min.

--

6 . Photoresist Removal

Acetone 15 min. Piranha 15 min.

D.LOCOS 1 (TCA clean furnace before using 1. Oxide Dip

2. Oxidation

HF:DI/l:lO

- 10 sec. to remove 40.4

1000 C steam 60 min. (0.4 um)

(5min push)

3. Switch to N2 for IO min.

(5min pull)

4. Oxide thickness measurement

5 . Oxide Dip

)

- 4000 .A

HF:DI/l:lO 30 sec.

6 . Sitride Removal Phosphoric/sulfuric .Acid 2011 155 C

90 min.

(The use of a REFELIS system is required to maintain the proper temperature during etching.) 4 . Oxide thickness measurement over KU’ELL areas (need

9. Piranha 10. Oxide Dip

11. Drive In

-

50 nm)

15 min.

HF:DI,/I:IO 1 0 sec. (T(7.4 clean furnace before)

(7min p u s h ) I150 C 1 2 1 0 h r s .

E. -4CTIVE REGION DEFISITION ( h & P REGIONS 1. Oxide Etch HF:III/1:5 until surface beads then 20 sec. more

1. Initial Oxidation (11) (TCA before) 1 0 0 0 C Dry 0 2 55min. 5 5 nm

36

3. Switch to I1'2 for 10 min. 4 Oxide thickness measurement

5 . Nitride Deposition

- 550 A

120 nm

6. Nitride thickness measurement Smin (optional)

9. piranha

8. Standard Photo-Lithography [ Mask- MAA 9. Nitride Dry Etching ( see

1

c. 5 )

10. Pho toresist Removal

Acetone 15 min. Piranha 10 min.

F. P-FIELD DEFINITION 1 Standard Photo-Lithography (Mask- ?WELL) e

2. P-Field lmplantation 3. Strip off Photoresist

Boron/ZS Kev 3.3e13 Acetone 15 min. Piranha 10 rnin

G . BACKSIDE IMPLAXI' 1. Spin on frontside protection PR

3000 rpm. 30 sec.

2. Bake 120 C. 20 rnin.

3. Plasma Etch backside in barrel etcher until backside nitride is gone. SF6102 15 w a t i s . I torr 6 5 4.

RAChSIDE Implantat ion I312 2Ot)hev. 2el5.

5. Remove PR Acetone 1.3 min . Piranha 15 min . 11. LOCOS 2 ( * K O Aclean 1 urnace) 1 . ('lean again piranha 15 rnin.

2 . 111- D I P 111-/111 1 / 1 0 1 0 sec.

3. 1000

(5min p s h / p u l l ) steam

4. Oxide thickness measurement

230min. 0.9 urn

I. CAPACITOR DEFINITION/WN BIPOLAR BASE DEFINITON 1. This step is not necessary.

J. Nitride Removal 1.. Oxide Dip

HF:DI/1:10 4 0 sec.

2. Nitride Removal

Phosphoric Acid with 5%

sulfuric a t 155

C

(If some etching is not observed after 15 min then the oxide on the nitride was not fully removed.)

K OGate Oxidation (TCA clean furnace before using 1 1. Oxide Etch HF:DII'1:10

until active area is oxide free -.1.8 min.

2. Oxidation (1) (5min push/pull) 1000 C Dry 02 53 min. 55 nm + IOmin N2 anneal 3. Oxide Etch HF:DI/l:lO until active area is oxide free

- 1.8 min.

4. Oxidation (11) (5min Fushlpull) 1000

+ IOmin

c Dry 02 - 53 min. 55 nm

S1 anneal

5 . Oxide thickness measurement (want

- 550 A )

XI.P ~ L YI)I;rws1Tios 1 . Oxide Dip

2~ Pol) Deposition

IIIr:DI ' I : I O t~ get 50 nrn ositie .- 1 0 sec 0.39 urn

3. Poly Thickness J,leasurement 4. Poly Doping

PCSI-1 S2

02/32

3min

5mln

PrdeP

POCL3/02/N2 2Omin

drive-in

32

15min

PULL

Smin

(Do not TCA clean predep furnace. This tube may reflow a t high temperatures.)

HF:DI/l:lO 1 min.

5 . PSG Removal

6 . Poly Sheet Resistance Measurement

Using Four Point Probe. (desire ? yes WHICH PROCESS ? E S P 0 WHICH MASK ? SWEL INVERT THE MASK (yes or no) ? no XL1IE OF THE ESPOSED RESIST ? ERST DO YOU W.4ST TO DRAW THE CROSS SECTION (yes or no> ? yes WHICH PROCESS ? DEX'L NAVE OF THE LAYER TO BE DEVELOPED ? ERST DO YOU WANT TO DR-AW THE CROSS SECTIOS (yes or no) ? yes WHICH PROCESS 7 ETCH WHICH LA)-ER DO YOL' W X S T ETCH ? STRD ETCIi ALL (yes or n o ) 7 no XRIOL'NT OF YERTICAL ETCH (micro-meter) ? 0.1 RATIO S/'Z OF ETCHING (0.0 ? yes WHICH PROCESS ? EXPO WHICH MASK ? NWEL INVERT THE MASK (yes or no) ? no NAME OF THE EXPOSED RESIST ? ERST DO YOU WANT TO DRAW THE CROSS SECTIOX (yes or no) ? yes WHICH PROCESS ? DEVL

NAME OF THE LAYER TO BE DEVELOPED ? ERST DO YOU W A N T TO DRAW THE CROSS SECTION (yes or no) ? yes WHICH PROCESS ? 1,IlPL IMPLASTATION TYPE ( p or n) ? p DOSE (cm**(-2)) '3.Se+13 STASD.4RD DEI'I.ATIOS (micro-meter) ? 0.15

PE.4); DEPTH (micro-meter) ? 0.05 BLOCK THICKNESS (micro-meter) 7 0.1 DO YOC WANT TO DRAW THE CROSS SECl7OX (yes or no> ? yes WHICH PROCESS ? ETCH WHICH L.4YER DO YOU W A N T ETCH ? RST ETCH ALL ( y e s or no> ? y DO YOL' W X S T TO DRAW THE CROSS SECTION (yes or no) ? yes WHICH PROCESS ? OSID OXIDE THICKSESS (micro-meter) ? 0.9 S t (micro-meter) ? 0.9 S e ( micro-meter ) ? 0.45 ul ? 0.1 u2 ? 0.5 u3 ? 0.9 d l ? 0.1 d2 ? 0.5 d3 ? 0 . 9 DO Y O C WAST TO DRXW TI41 (:ROSS St.(-*I'l(I \

'

(ycfh

3 r n o ) 7 >'e?;

W I iI('1 I PROCESS 7 ETCI1 WHICH LAYER DO YOL W A S T EICH \'IXl) ETCH -ALL (yes or no) ? y DO YOU IVANT TO DRAW THE CROSS S E f l l O \ (yes or no) ? yes

WIfICH PROCESS ? IhlPL IhIPI-.A\TATION TYPE ( p or n > ? p

45

DOSE (cm**(-2 )>? 4el1 STANDARD DEVIATION (micro-meter) ? 0.05 PEAK DEPTH (micro-meter) ? 0.0 BLOCK THICKXESS (micro-meter) ? 0.1 DO YOU WANT TO DRAW THE CROSS SECTION (yes or no> ? yes WHICH PROCESS ? DEPO N A M E OF THE MATERIAL ? POLY THICKKESS OF THE MATERIAL (micro-meter) ? 0.39 ISOTROPIC, ANISOTROPIC. OR VERTICAL (I. A. or V > ? I DO YOU WANT TO DRAW THE CROSS SECTION (yes or no> ? yes WHICH PROCESS ? EXPO WHICH MASK ? POLY INVERT THE MASK (yes or no) ? n N-LVE OF THE EXPOSED RESIST ? ERST DO YOC W.4XT TO DRAW THE CROSS SECTION (yes or no)

no

WHICH PROCESS ? DE\.-L N A M E OF THE LAYER TO BE DEVELOPED ? ERST DO YOC W A S T TO DR-AW TIIE CROSS SECTION (yes or no) ? yes WHICH PROCESS ? DEPO

NAME OF THE MATERIAL 7 RST THICXXESS OF THE MATERIAL (micro-meter) ? 1.0 ISOTROPIC. ASISOTROPIC, OR VERTICAL (1. A. or V ) ? I DO YOL‘ WANT TO DR-AW THE CROSS SECTION (yes or no)

’yes

WHICH PROCESS ? EXPO WHICH MASK ? PSD INVERT THE MASK (yes or no) ? no N A V E OF THE ESPOSED RESIST ? ERST DO YOU W A N T TO DRAW THE CROSS SECTION ( y e s o r n o )

7 yes

WHICH PROCESS ? ETCH

WHICH LAYER DO YOU WANT ETCH ? RST ETCH ALL (yes or no) ? y DO YOU W A N T TO DRAW THE CROSS SECTION (yes or no) ? yes WHICH PROCESS ? DEPO

KAME OF THE MATERIAL ? RST THICKNESS OF THE MATERIAL (micro-meter) ? 1.0 ISOTROPIC, ANISOTROPIC. OR VERTICAL (I. A. or V ) ? I

DO YOU WANT TO DRAW THE CROSS SECTION (yes or no> ? yes WHICH PROCESS ? EXPO WHICH MASK ? PSD INVERT THE MASK (yes or no) ? y NAME OF THE ESPOSED RESIST ? ERST DO YOC W A S T TO DRAW THE CROSS SECTlOS (yes or no) ? ye>

WHICH PROCESS ? DEVL N.4iiIE OF THE LAYER TO BE DEVEI.OPED ' ERST DO YOC WANT TO DR.A\V THE CROSS SECTION (yes or n o )

' )e'

WHICH PROCESS ? IMPL IMPLAhTATION TYPE (p or n > ? p DOSE (cm**(-2)) ? 3.0-15 STANDARD DEVIATION (micro-meter) ? 0.1 PEAK DEPTH (micro-meter) ? 0.0 BLOCK THICKNESS (micro-meter) ? 0.1 DO YOL' WANT TO DRAW THE CROSS SECTION (yes or no) 7 yes

IVHICH PROCESS ? ETCH U'HICH LAYER I>O YOC U'4ST ETCH ? RST ETCH ALL (yes or n o ) ? y DO J'OC W A S T TO DK.AW THE CROSS SECTION

( y e s or no)

' ye3

U'lIICIl PROCESS EXPO \VIiICH ILlASK 3 COAT INI'ERT THE MASh (yes or no) ? yes NA\lE OF THE EXPOSED RESIST ? ERST DO YOU WANT TO DRAW THE CROSS SECTION (yes or no> 7 yes WHICH PROCESS ? DEVL

,

NAME OF THE LAYER TO BE DEVELOPED ? ERST DO YOU WANT TO DRAW THE CROSS SECTION (yes or no) ? yes WHICH PROCESS ? ETCH WHICH LAYER DO YOC WANT ETCH ? OXID ETCH ALL (yes or no) ? no AMOUNT OF VERTICAL ETCH (micro-meter) ? 0.700000 RATIO ? yes WHlCH PROCESS ? QUIT Fig.7-1 shows the layout of a inverter and the SO~m-longcut-line on the laycul. The sirnulaled cross-section is shown in the bottom half of Fig.7-1. Fig.7-1 was raken f r o m a Tektronix 4113 color graphics terminal. It look 8 minutes of CPC time in graphich

mode and 5 minutes in non-graphics mode to generate the crew section of the c \ I o S

Fig.7-2 shows the profile along t h e IOpcm-long cut-line 3 r o i I n d n-~.liannel sourc?

region on the same ClIOS layout. 'The 'bird's-beak'. lateral diflusion. and aluminum deposited by sputtering are clearly shown.

M

C

0 I

E

3

x

M

E

0

a

v. W.

E

'4a

.

50

9 7.2 DBAM Cells The profile of a NMOS DRAM cell along the 20pm-long cut-line is shown in Fig.7-

3. The metal line across the profile is the bit line and the left polysilicon is the word line. The polysilicon on the right side of the cross section makes the storage capacitance. Fig.7-4 shows the layout of CMOS DRAM cells and cross section along the 7.92gm-long diagonal cut-line drawn on the layout. This example has double level polysilicon and double level metal process. On the cross section. the first level metal makes contact with the second level polysilicon on the left and the second level metal is connected to the first level metal through the via on the right.

L,

f M C 0

c

Q

e

k!

v. v, (I:

E CI

e

f

s L

C

52

M

C

0

f

S

u

2

. I

v.

Ref ereaces

[Bill831 G.C. Billingsley. "Program Reference for KlC." hlemorandum no. LTCBIERL M83/62. Electronics Research Laboratory. U.C. Berkeley, Oct. 1983.

(Chin821 D. Chin. M.R. Kump. H . 4 . Lee.and R.W. Dutton. "Process Design Using TwoDimensional Process and Device Simulations." IEEE Trans. Electron Devices. vol. ED-29.

no. 2. pp. 336-340. Feb. 1982.

[Chin83a] D. Chin, S.Y. Oh, S.M. Hu, R.W. Dutton. and J.L. 31011. "Two-Dimensional Oxidation." IEEE Trans. Electron Devices, voi. ED-30. no. 7 . pp. 744-739. July 1983.

[Chin83b] D. Chin, S.Y. Oh. and R.W. Dutton. "-4 General Solution Method for TwoDimensional Nonplanar Oxidation ." IEEE Trans. Electron Devices. vol. ED-30. no. 9. pp.

993-998. Sept. 1983.

,

[Deal651 B.E. Deal and AS. Grove. "General Relationship for the Thermal Oxidation of Silicon." 1. Appl. Phys.. vol. 36. no. 12. Dec. 1965.

[Duttbl] R.W. Dutton and S.E. Hansen. "Process Alodeling of Inlegrared Circuir Device Technology," Proceedings of the IEEE. vol. 69. no. 10. pr. 1305- 1320. Oct. 1 9 b l .

[EDII'b5] Electronic Design Interchange Format Steering Ckmmittee. "EIIIF'. Elecrornic

Design Interchange Format. i'ersion 1 0 0." The EIIII: Lsers' Group. Design .Automation Department. Texas Instruments.

P.O.Box

225474, 31S366S. Dallas, Teras 75265.. 1985.

[GreeSO] J.A. Greenfield and R.W. Dutton. "Nonplanar VLSI Device .Analysis Using the

54

Solution of Poisson's Equation." IEEE Trans. Electron Devices. vol. ED-27. no. 8. pp. 1520-1532. Aug. 1980.

[Grim831 M.A. Grimm. K. Lee. and A.R. Neureuther. "SIMPL-1 (SIMulated Profiles from the Layout

- version 11." International Electron Device Meeting. Dec. 1983.

[Ke1181] K.H. Keiler. "KIC. A Graphics Editor for Integrated Circuits." Masters Report. Department of Electrical Engineering and Computer Science. L'niversity of California. Berkeley. CA. June 1981.

[Kern781 B.W. kernighan and D.11. Ritchir. "The C Programming Language " PrenticeHall. Englewood Cliffs. Sew Jersey. 1978.

fliopp831 G.M. Koppelman. and M..4. Wesley. "OYSTER: X Study of Integrated Circuits as ThreDimensional Structures." IBM J. Res. Develop.. vol. 27, no. 2. >Jar. 1963.

[Lee82a]

K. Lee. Y. Sakai and A . R . Neureuther. "Topography Dependent Step Coverage

Resistance Simulation for VLSI Design." 1982 Symposium on VLSI Technology . Proceedings pp. 61-62. Oiso. Japan. Sept. 1982.

[LeeS2b] k. Lee. Y.SaLai. a n d -4.R.Seureuther "Topograph! Dqw-ident I:leclrical Parameter Simulation." International Electron I>evice \leetins. Dzc. 1q h l

[Lee831 K. Lee. J.. Sakai, and .A&. Seureuther, "Topography-hpenden 1 Electrial Parameter Simulation for VLSl Design." IEEE Trans. Electron Devices. vol. ED-30. no. 11. pp. 1469-1474.

&OV.

1983.

55 [Lore841 J. Lotenz.

K. Haberger. G. Prinke. H.Ryssel. A. S i d e l . J. Pelka. A. Sacks. and IM.

Svoboda. ' A Universal Two-Dimensional Process-Simulation Program." Second Gonference on Numerical Simulation a i V U 1 Devices. Boston. MA.. Nov. 1984.

[Mead801 C.A Mead and L.A Conway. "Introduction to VLSI Systems." Addison-Wesley. 1980.

[Nand841 S.N. Nandgaonkar. 'A Family of Simulation Programs for IC Fabrication Processes (Their Structure. Design and Implementation)." Memorandum no. UCBIERL M84/90. Electronics Research Laboratory. University of California. Berkeley. CA 94720.

Oct. 1984.

[Oldh79] W. G. Oldham. S . N. Nandgankar. A. R. Neureuther. and SI. O'Toole. " A General Simulator for VLSI Lithography and Etching Processes: PartI-.Appl ication Lo Projection Lithography.' IEEE Trans. Electron Devices. vol. ED-26. no. 4. +"?. 717-722. -4pr1979.

[OldhBO] W. G. Oldham. A. R. Neureuther. C. Sung. J. 1.Re!.nolds and S. 1.Nandgaonkar. " A General Simulator for \'LSI

Lithography and

Elching

Processes:

PartII-

.Application to Deposition and Etching." IEIIE Trans. Elecrron Devices. vol. ED-27. no. 8 . pp. 1455-1459. . A u ~ .19hO.

[Pent1831 " -4 comprehensive Two-Dimensional \'LSI

Process Simulation Program.

BICEPS." B.R. Penumalli. IEEE Trans. Electron Devices. vol. ED-3t). no. 9. pp. 986-992. Sept. 1983.

[Reyn79] J.L. Reynolds, A.R. Neureuther. and W.G. Oldham. "Simulation of Dry Etched

56 Line Edge Profiles.' J. Vac. Sci. Technology, 16(6). Nov./Dec. 1979.

[RyssbO] H. Ryssel. K. Haberger. K. Hoffmann. G . Prinke. R. Duemcke. and A. Sachs. 'Simulation of Doping Processes.'

IEEE Trans. Electron

Devices. vol. ED-27, no. 8. pp.

1484-1492. Aug. 1980.

[SelbSO] S . Seiberherr. A. Schuetz. H.W. Poetzl. 'MI?r:IILIOS

-

a Two-Dimensional 310s

Transistor Analyzer." IEEE Trans. Electron Devices, vol. ED-27. no. 8 . pp. 1540-1550. Aug. 1980.

Appendk

SIMPL-2 User Guide

57

1. Introduction

SIMPL-2 (SIMulated Profiles from the Layout

-

version 2 ) is a computer-aided-

design tool for integrated circuits which automatically simulates the cross sectional view

of integrated circuits along an arbitrary 'cut-line' drawn on the layout. For a given layout. SYMPL-2 extracts the mask information from the intersections of the layout geometries with the specified cut-line. Using this layout information. SIMPL-2 generates the evolution of cross sectional structures according to the process steps given to

SIMPL-2 interactively or in batch mode. The device profile from the c o m p s i t e process can be generated rapidly using elementary internal physical process models. More rigorous external process simulators can also be invoked through an interface for profile data and transfer of control. As of nou'. the SA.MPLE program is linked t o SIMPL-2 to simulate the deposition process. The first version of SIMPL-2 consists of 12.SOO lines of

(3

with CNIS 4.2BSD operating system.

SlhlPL-2 Cser (iuidz

April 1, 19h.5

and runs on V A S 1 1 '7bO

2, How to load SIMPL-2

The M F B package and SAMPLE program are necessary to run SIMPL-2 and some modifications should be made according to the system before SIMPL-2 is loaded. Since

SIZIIPL-2 uses with

MFB package for

its graphics interface. SIMPL-2 should be loaded together

MFB. The line in the 'makefile' of SIMPL-2 which specifies the path

LO

MFB may be

modified. The line is currently

MFB = /oc/cad/lib/mfb.a Also the line in mfb.h Wefine DEFAL'LTMFBCAP "- cad/'lib/mfbcap"

should be modified if 'mfbcap' is located somewhere else. There is another line to be modified depending on the system. As described above. the S-AMPLE program is called for the deposition process (except for the vertical deposition option). So the line. system(" ,'od/samplelsamsof t/reIease/ uc b/ samp le.out

< S.AW'LE_lnput >

S A % P L E - ~ U ~ ~ U1:L "

in the source file 'Dep0sition.c' should be modified according

LO

the location of SXllPLE.

Now. sI31PL-2 is ready to be compiled and loaded. c/c make

compiles the source codes of SIIIPL-2 and load the object files. -An execulable file 'simpl' is

generated by the cammand.

A3

3. How to lllp SIMPL-2 3.1 Preparing ‘MFBCAP’ When the file ‘mfbcap‘ does not contain an entry for the graphics terminal. a new entry can be written with the key words specified in MFBCAP(5) in the UNIX Programmer’s Xlanual. The terminal should support the ‘replace (jam) mode’ to run SIMPL-2.

3.2 Preparing ‘SIMPL_pattern’ ‘SIMPLqattern‘ file is required to execute SIMPL-2. This file has the pattern and color information for each material and mask layer which will be drawn on the screen. -411 the layers described in this file are listed with their name on both sides of the screen.

The format for each layer in the file is as follows.

NAME SWEL RGB 10(K) 1000 0

FILL 128 64 32 16 8 4 2 1

‘N.%&IE’.‘RGB’. and ‘FILL’ are the keywords f o r the material name. color code. and

fill

pattern. respectively. *XAAlE*is limited to f o u r characters. The three numbers followins ’RGB’are the intensity of red. green. and blue colors normalized to 1000. .For example. lo00 IoOt) 1000 makes the color white. The fill pattern is defined with 8 5 8 bit pattern.

Each decimal number followed by ’FILL’ stands for the bil pattern of the

corresponding row. lvhen SI\,!PL-2 is executed. sI>IPL-2 uses the file. S1\1I’I_jattern. to load the color and pattern information in an internal swing. The file. SI\IPl.gatrern, also has the color information for the impurity doping concentration written in the same formal. Here is an example.

SlhlP1.-2 Cser Guide

.April 1. l 9 b 5

A4

N A M E NP RGB 600 5 0 0 500 FILL 255 255 255 255 255 255 255 255

N A M E N12 RGB 0 200 0

FILL 136 0 NAME N15

0 0 34

0 0 0

RGB 0 200 0

FILL 170 85 170 85 170 85 170 85 NAME N18

RGB 0 200 0 FILL 255 255 255 238 255 255 255 238

N A M E P12 RGB 400 4 0 0 FILL 136

0 0 0 34

0 0 0

YAZIE P15 RGB 4 0 0 40 0 FILL 170 85 170 85 170 85 170 85

NAME P18 RGB 400 40 0 FILL 255 255 255 238 255 255 255 238

It begins with the name 'SP' which is intrinsic substrate (not exactly intrinsic: NP covers the doping concentration less than t h e lowest concentration specified. ) Following '?d''.

the pattern information for the n-type should come. T h e number after 'N'means the exponent of doping concentraLion. For the above esamFle. 'S15' covers IO" to 10'' and ' \ I & ' covers

and above. A f t e r S s x ' k . [he p-type color spectrum is defined in the

same way. This pattern information for the doping concenLrarion should c o m e after those f o r all t h e other cross section and layout la).ers,

3.3 Commands

SI31PL-2 can be invoked by typing

A5

'% simp1 -n

or To simp1 -(terminal type)

The first command runs SIMPL-2 in non-graphics mode and the second runs SIhlPL-2 in graphics mode. In non-graphics mode, SIMPL-2 runs exactly the same way as in graphics mode except that no graphics output is drawn on the screen. The terminal type is specified by a key word in the MFBCAP file. For example. one of the key words t3. T3. 41 13D. or T4113D can be used for Tektroix 4113 color graphics terminal.

When SIMPL-2 is invoked. it searches the 'SIiMPLqattern' file in the present working directory and displays the patterns in the file on both sides o i the screen. The layers for the layout and cross section are dispIayed on the left and color spectrum of doping

concentration on the right. After the initialization described above. SIAIPL-2 prompts questions on the c o n mand window at the bottom. The first question is LAYOUT FILE NrLME ?

A CIF file name may be given for this question and SIhlPL-2 draws .the layout on the

upper half screen. The next question is

START .A XEV' SIMULATION ? (yes or no)

When 'y(es>' is typed. SIlIPL-2 asks for a location of cut-line by giving the graphics cursor on the screen. For a specifred cut-line. the mask information is stored in the file

'5liisk-Edges'.

.A substrate for the cross section is initialized by answering the following

questions.

SCBSTK-ATE TI'PE 3 ( p or n )

DOPING COSCE\TR.ATIOS (cm**(-3) 1 ?

If 'n(o1' is typed to the question. "S'f.4HI' .1 \En' Sl\lL'l.~ATlO\

7

(yes or no)".

SI3lPL-2 asks the savefile name which contains the cross section data u,hich was senerated by a previous run. At t h i s time the 'Mask-Edges' file is read and the cut-line drawn on the layout. Thus. the '\,lask-Edges' and mask information with the savefile.

IS

file should have the corresponding cut-line

A6

Before SIMPL-2 draws the cross section. i t asks

VERTICAL DIMENSION SCALE FACTOR ?

The vertical scaling is needed since the vertical dimensions a t e usually smaller than the horizontal dimension. A scaling factor between 2 and 3 are usually used.

Now. SIMPL-2 is ready to simulate the process steps. On the command line a t the bottom.

WHICH PROCESS ?

is displayed. The available answers to these questions are

DEPO DEVL

ETCH

EXPO IMPL NEW-(=UT

N E1.v-L.A YOL'T OPES-PC, CLOSE-PC

OSID

PROCESS-FILE REDR-4W

s.4IT WAIT

QUIT

In the rest of this section. each c o m m a n c ~is esplained In alphabetic order.

This is the command for the deposition process. This command is followed by the questions below

A7

WHICH PROCESS ? DEPO

NAME OF THE MATERIAL

3

NTRD

THICKNESS OF THE MATERIAL (micro-meter) ? 0.08 ISOTROPIC. ANISOTROPIC. OR VERTICAL (I. A . or V ) ? I DO YOU WAXT TO DRAW THE CROSS SECTION (yes or no> ? yes

The name of the material to be d e p s t t e d should be different from that of any material which is exposed to air before the deposition process. The deposition process is carried out by the SAMPLE program when I or A is given for the question "ISOTROPIC. -4SISO-

TROPIC. OH VERTICAL (I. A. or V ) ?" For the isotropic deposition. SIILIPL-2 calls the etching machine of SAMPLE with a negative etch rate and for the anisotropic deposition

SIMPL-2 calls the deposition machine with the sputtering source. For the anisotropic deposition the following question is asked.

SPCTTERING SOURCE ANGLE (degrees) ?

The source angle is the angle betkeen the center of the source and the edge of it seen from a point on the wafer.

DEPO

When

is

done

b\.

SAMPLE.

three

new

files.

'SA3IPLEJnput'.

'SAhPLE_Output'. and 'f77punch7' are generated in the present working directory. SA3lPLEJnput. is the input file for SXXII'LE. S.431PLE-0~tp~tis the standard output of S.4MPI.E. and f77punch7 is the string points output for plot. The f77punch7 is used to rebuild the data base of SIMPL-2. When V is given for the question "ISOTROPIC. XSISOTROPIC. OR \'EHTlCXL (1. .A. or

\'I ?". the material is deposited only vertically without running SAIIPLE.

This

is

the command for the dekelopment process in photo-lithc~Sraph>. The

development process of photo-resist

is

simulated by removing the appropriate polygons

generated by the exposure step. In interactive mode, the development process out as follow.

is

carried

WMICX PROCESS ? DEVL

N.UIE OF THE LAYER TO BE DEVELOPED ? ERST DQ

YOU WXNT TO DRAW THE CROSS SECTION (yes or no> ? yes

For the example above. the 'ERST layers which are exposed to air are removed.

This is the command for the etching process. The etching process is simulated interactively as follows. WHICH PROCESS ? ETCH WHICH LAYER DO YOU W A S T ETCH ? RST ETCH ALL (yes or no)

' yes

DO YOU W.43T TO DRAW THE CROSS SECTIOU (yes or no) ? yes

The first example shows the case of unmasked etching. The layer. 'KST'.

IS

totally

etched. The polygons with the specified name are deleted if they are exposed to air. WHICH PROCESS ? ETCH WHICH LAYER DO YOC U'ANT ETCII ? NTRD

'

ETCH ALL (yes or no) no A31OCST OF VERTICAL ETCH (micrometer) ? 0.1 RATIO S 'Z OF ETCHIYG (0.0

? n

DOSE (cm**(-2)) ? 1.&+12 STANDARD DE\'IATION (micro-meter) ? 1.5 PEAK DEPTH (micro-meter) ? 0.0 BLOCK THICKNESS (micro-meter) ? 0.1

.

DO YOU W.SST TO DRAW THE CROSS SECTIOS (yes or no) ? yes

The model used in SI3lPL-2 is a Gaussian distribution. The implanted profile is approximated by

c (x

= ( N / J Z x u p)exp (-(x -R,. >'/ 2 ~ ~ ' )

where N is the implanted dose, R, is the projected range. and M is the projected standard deviation. Since SIRIPL-2 does not have a module for the therrAal annealing. the final profile after any thermal steps should be approximated by a Gaussian. The BLOCK THICKXESS is the thickness of oxide that implanted ions cannot fully penetrate. For a given BLOCK THICKNESS. SIMPL-2 searches the areas where the bare substrate is exposed or the oxide is thinner than the BLOCK THICKNESS.

-41~0.

SIhfPL-2 assumes a complete 'block;' by other materials covermg the surface. Before the

impurity concentration is calculated for the implanted region. vertical grid lines are added near the implantation mask edges. .After the neu grid is formed. the implanted dose is super-impsed on the original dopin,0 concentration. The lateral diffusion is approsimated b>, the same Gaussian disrribution decaying radially on the implantarion mask edges. 7'his

IS a

crude aFproslmation t o be used u n t i l

a suitable two-dimensional simulator u.hici.1 can treat large simulation u indous is available.

SI51PL-2 Cher Guide

April 1. 19h5

All

When this command is typed for the question ‘WHICH PROCESS ?’. SIMPL-2 stops the current simulation and prompts the graphics cursor for a new cut-line in graphics mode or asks the coordinates of cut-line in non-graphics mode.

-

NEWLAYOUT

This command is used to call a new layout. The question. LAYOUT FILE S M I E ?

follows this command.

*** OPEN-?,

CLOSE-PC

-

These are commands to prepare a process file for the batch-mode run. When

‘OPES-PC’ is typed for the question ‘WHICH PROCESS ?’. SIMPL-2 asks PROCESS FILE l A 3 1 E TO BE WRITTES ?

After a file name is given. every question given by SI3IPL-2 and the user’s answer are

stored in the designated file until ‘CLOSL-IC’ is typed for the question ’WHICH PROCESS ?’. ‘(3LOSL-PC’ command puts ‘E.\D’

in

the process file a t the end. This file

IS

to

be used to run SIJlPl-2 in batch-mode b). the command ‘PROCESS-F1L.E’.

*** OXID =* This is the command for the oxidation process. The oxidation process is carried out interactively as follows.

A12

WHICH PROCESS ? OXID

OXIDE THICKNESS (micro-meter) ? 0.058 Xa (micro-meter) ? 0.058

Xe (micro-meter) ? 0.029 ul ?0.1

u2 ? 0.5 u3 ? 0.9 dl ?O.l

d2 ? 0.5 d3 ? 0.9

DO YOU WANT TO DRAW THE CROSS SECTION (yes or no> ? yes

A

ut

Fig.3-4

The OSlDIi T111CKSESS is the thickness on the bare substrate 1 1 there

is oxide laher

before oxidation U t and Dt in Fig.3-2 are ayFroximated by

I!, = JF,’+(a7.,

I

I), = J i l , = + ( p 7 : . ,

I= 12

where To,is the given OXIDE THICKXESS on the bare substrate.

Q

and P are the frac-

tions of oxide thicknesses grown upward and downward from the initial substrate surface. respectively.

A13

Xt is the total bird's beak length and Xe is the length of encroachment as shown in

Fig.3-2. u 1.

u2. u3.

d 1. d 2. and d 3 are defined as follows. u1

= u1/ u,

u2

= u2/ u,

u3

= u3/ u,

d

= D1/ 0,

1

d 2 = D2/ D, d3

where G I . U 2 . [I3.

= D J 0,

D 1 .D2.and D 3 are defined in Fig.3-2.

When this command is typed for the questicn 'WHICH PROCESS ?'. SI3lPL-2 asks

PROCESS FILE NAME 3

SIMPL-Z does the process simulation according to the file until 'END' is read in the file. This process file may be written by the commands, 'OPEI\;-PC' and 'CLOSE-PC'.

*** REDRATX' *** This command

is

used to redraw Llie cross section u i t h

.factor. The ques~ion \TiRTICAL I)I.\IESSIOS SCALI I'.A(I'OR

follows to set a new scaling factor.

SI>IPI--2 User (iulde

Xpril 1 . 1985

a

different kertical sialing

- -

A14

SAVE

This command saves the current cross section data in a file. The file name is given eo SIMPL-2 by answering the question SAVEFILE NAME ?

which comes after the ‘SAVE’ command. The savefile is to be used to display the section or t o continue the process later.

-WAIT-

When this command is given. SISIPL-2 sleeps until the ‘return’ key is hlt.

-

QUIT

This command terminates the session.

CTOSS

-415

4. Example

This section presents an example layout and the first few process steps for the lay-

out. The following is the CIF description of a CMOS inverter. When this file is given to

SIMPL-2. the layour is drawn on the upper half Screen of a terminal. (CIF file of symbol hierarchy rooted at cm0s.k): Ds111: 9 cm0s.k;

L ED: B 1400 850 -800 -25:

L ACTV: B 1300 500 900 0: B 1750 500 -1125 0: L POLY:; B 400 200 0 -800: W 200 -900 350 -900 -600 900 -600 900 350:

i MTL; B 4 0 0 400 0 -700:

B 400 B 400

400 -500 0: 4 0 0 500 0:

B 600 200 0 0 :

B 800 2500 -1500 -50; B 200 400 0 -1100:

B 400 2500 1300 -50: B 200 1100 0 6 5 0 :

L COST: B 200 200 -500 0 : B 600 ZOO -1500 0:

B 200 200 5 0 0 0 :

B zoo 200 I300 0: B 200 200 0 - 7 0 0 : L SWEL: B 2200 1200 -1 100 0:

DF:

c 1: E

SII\lPI.-? User Guide

.April 1. 1 Y h i

A16

When a cut-line is given. the mask infomation is stored in the files 'Mask-Edges.'

For

example. if the coordinates of cut-line end points are (-25.0 .O.O), (25.0 ,O.O> (unit : pn). the stored data in the file. 'Mask-Edges'. is as follows. cut line : -2500 0 2500 0

number of masks = 6

PSD 1 10.000 24.000

ACFV 2 5.000 22.500 27.500 40.500

POLY 2 15.000 17.000 33.000 35.000

MTL 3 6.000 14.000

18.000 32.000 36.000 40.000

CONT

4

7 . 0 0 0 13.000

19.000 2 1.OOO 29.000 31 .OOO

37.000 39.000

The process sequence of the CAIOS inverter can be carried ou1 step by step with this

mask information. The process inputs up to the local oxidation for S-well formation are given below as an example. WHICH PROCESS ? oxm

A17

OXIDE THICKNESS (micro-meter) ? 0.058 Xt (micro-meter) ? 0.058 Xe (micro-meter) ? 0.029

ul ? 0.1 u2 ? 0.5 u3 ? 0.9 d l ? 0.1

d2 ? 0.5 d3 ? 0.9

DO YOU WANT TO DRAW THE CROSS SECTION (yes or no> ? yes

WHICH PROCESS ? DEPO NAME OF THE MATERIAL ? NTRD THICKXESS OF THE MATERIAL (micro-meter) ? 0.08 ISOTROPIC. ANISOTROPIC. OR YERTICAL (I. A . or 1’)? I

DO YOU WANT TO DRAW THE CROSS SECT103 (yes or no> ? yes

WHICH PROCESS ? DEPO NAME OF THE MATERIAL ? RST THICKSESS OF THE &LATERIAL(micro-meter) ? 1.0 ISOTROPIC, ASISOTROPIC. OR VERTICAL ( I . A . or V > ? I

DO YOL W.GT TO DRAW THE CROSS SECTION (yes or no> yes

WHICH PROCESS ? EXPO

WHICH 31.4.S ? S I V E L IS\’ERT THE LI-ASK (yes or n o )

’no

X.k\IE 01:THI3 FSPOSED RESIST

’ERST

DO YOI. IV.4ST TO DKX\V TI1E CROSS SI ( T O \

( y e s or no)

hes

WHICH PROCESS ? DEVL

NAVE OF THE LAYER TO BE DEVELOPED ? ERST

DO YOC W A S T TO DRAW THE CROSS SECTION (yes or no) ? yes

A18 WHICH PROCESS ? ETCH WHICH LAYER DO YOU WAXT ETCH ? XTRD

ETCH ALL (yes or no> ? no

AMOUNT OF VERTICAL ETCH (micro-meter) ? 0.1 RATIO X/Z OF ETCHING (0.0 ? yes

WHICH PROCESS ? ETCH WHICH LAYER

Do YOU WANT ETCH ? RST

ETCH ALL (yes or no) ? yes DO YOe‘ WANT TO DRAW THE CROSS SECTIOS (yes or no> ? yes

WHICH PROCESS ’OSID

OXIDE THICKSESS (micro-meter) ? 0.4 Xt (micro-meter) ? 0.4 Xe (micro-meter)

7 0.2

u1 ? 0.1 uz ? 0.5

u3 ? 0.9 d’l ? 0.1

d2 ? 0.5 d3 ? 0.9

DO YOL‘ WANT TO DRAN’ THE CROSS SFCTlON (yes or n o ) ? yes

A19 5. SIMPL-2 structure This section contains the names of functions in the source files.

CIF44ctions.c :

AEkginCall( SymbolNum)

riBeginSymbol(SymbolNum.AB) XBox(Length. W idth.)i.Y .XDirection.YDirection) AComment( Text 1

ADeleteSymbol(Symbo1Num) AEnd( AEndCall() AEndSyrntd) .4Layer(Technology .Mask)

.

APolygon( Path) XRoundFlash( W idth.X .Y) AT(Type.XY 1 AUserExtension( Digit.Text 1 AWire(Width.Path)

CIF-Parser.c : PBox( ) PCIF( CIFFileSame.SratusString.StatusIn t . W hichXction PCall( 1 PCharacrer( W hiteSpaceContro1.EOFControll PCommen t ( 1 PDeleteSymbol( 1 PEnd ( )

.

PErrod PErrorXlessage 1 Plntegert WhiteSpaceControl .EOF Move(PPVertesName)

Move-Backward(PPVertex.Name) One_D-Search_orJnsert(

ppvertex. name. xqosition

POLYGONPTR Find-Pol ygon(p. name) Renamdfrom-vertex. to-vertex. from-name. topame) Separate_PoIygon(p p l y g o n

.

>

Substitute( p. f romjtring t o S t ring)

Two-D-Search_or_lnsert(pp_vertex. Which2Wode(p. pp. name) Write_a241R( p> float Thicknesdp. name) struct Vertex *Get-LeftTop( struct Vertex *Get-RightTop( Write-Data-c : Wri te_savefile( 9

> 1

x l . z l , x2. 22. p. q. name)