Simulation Based Experimental Investigation for ...

Proceedings of the 2015 International Symposium on Semiconductor Manufacturing Intelligence (ISMI2015)

Simulation Based Experimental Investigation for Performance Assessment of Scheduling Policies in Wafer Fabrication Rashmi Singh and M. Mathirajan 

Abstract— This paper evaluate fifteen release policies with

II. LITERATURE REVIEW

three simple dispatching rules for Intel Mini Fab, which captures the challenges involved in scheduling the highly re-entrant semiconductor wafer fabrication flow lines. Arena simulation software is used to build the model and conduct these experiments. The scheduling policies (that is release and dispatching) together are compared based on the delay/throughput trade-off curve. The simulation results show that an appropriate choice of release policy can significantly improve the system performance with respect to delay and throughput. In general, it is concluded that Shortest Imminent Processing Time (SIPT) was the best dispatching rule and Starvation Avoidance (SA) the superior release policy in all the considered scenarios.

In wafer manufacturing, there are primarily two ways in which control is exercised over the plant. First, one can specify when new lots are to be released into the plant. This is done by the release policy. Second, for lots already in the plant, one has to decide which lot is processed next at each machine as it becomes available. This is done by the dispatching rule. As the focus of this study is more on release policies so, we discuss release policies in detail and briefly we have a discussion about common dispatching rules found in the literature. Several release policies for wafer fabrication has been stated in the publications over the last years [3, 27, 9, 4,10, 2, 15, 20, 8 and 24]. A release policy has significant impact on system performance of wafer fabs [7, 9 and 21]. Based on considering the system(s) information or not for controlling the release, the earlier research on the release policies in wafer fabrication can be broadly grouped into open loop release policies and closed loop release policies. Subsequently, in next section we discuss these release policies in detail.

Keywords: Release policies, dispatching rules, simulation, re-entrant flow, semiconductor, wafer fabrication.

I. INTRODUCTION The triumph of semiconductor wafer manufacturer is determined by its capability to provide the amount and superiority of wafers demanded by customers in an immensely competitive environment. In addition, opportunities of the dual promises of more chips per wafer and economies of scale have led the development of the new 400 mm fabrications even more complicated and expensive. Therefore, the production control particularly scheduling of wafer manufacturing, if not managed properly, can result in degradation of wafer fab performance such as it can leads to high levels of work-in-process (WIP), long cycle times and poor due date performances. The shop floor control addresses this issue by implementing scheduling policies that is release and dispatching policies together with the goal of maximizing fab productivity. Consequently, this paper addresses two main aspects of shop floor control: release policies and dispatching rules. The objective of this study is to identify current benchmark and high claim release policies and commonly used dispatching rules from the literature. The second objective is to conduct a rigorous experimental performance evaluation using simulation to quantitatively compare the effect of the combination of release policies and dispatching rules on key fab performance measures. The rest of the paper is organized as follows. Section II summarizes previous studies involving release policies and dispatching rules in wafer fabrication environment. Section III describes the simulation model used for the study. The experimental performance evaluation and the results are presented in section IV and V, respectively. Finally, the conclusions of this research and the future scopes are presented in section VI.

A. Release Policies An open loop release policies uses no system information and release is usually scheduled based on demand. Open loop release policies discussed in the literature are: Immediate Release (IMR) [1, 3 and 17], Random Release (RAND) and Uniform Release (UNIF) respectively. UNIF policy is also called Deterministic Input, Uniform Start, Clockwork or Uniform Loading respectively by [21, 7, 6 and 14]. In this study we choose to examine only UNIF release policy because according to queuing theory, UNIF is the best open loop release policy since it minimizes the input variability [17]. Moreover, open-loop release policies are discussed in the literature only for the purpose of comparison with closed loop release policies. The closed loop release policies uses system information while releasing the jobs, therefore they are able to effectively respond to the dynamics and variability’s of the manufacturing system. Successively, Glassey and Resende [7] proposed (SA) release policy to reduce the cycle time of wafer fabs. This release policy releases a job into the fab, when the virtual inventory at the bottleneck workstation falls down to a predetermined value. The virtual inventory is the work content (measured in work hours at the bottleneck) of all jobs either at the bottleneck work station or expected to arrive at the bottleneck within a given lead time. Lead time is the expected time required for a job to arrive at the bottleneck for the first time, once it has entered the shop. Wein [27] developed (WR) policy to reduce the total queuing time of wafer fab. This policy releases a job into the fab when the remaining work at the bottleneck work station for all jobs in the fab falls below a prescribed level. In later 1

Proceedings of the 2015 International Symposium on Semiconductor Manufacturing Intelligence (ISMI2015)

years, modified version of WR is being proposed by many authors. For instance, Kim et al. [11] proposed a version of WR namely (PWR) release policy which releases a job into the fab based on the workload of bottleneck work station. However, unlike WR only a portion of jobs in the fab is considered to compute the workload at the bottleneck work station. Since, considering the jobs that were processed recently at bottleneck workstation and are not expected to arrive in the near future may cause overestimation of the workload at the bottleneck workstation. Another version of WR is being proposed by Rose [21] namely CONLOAD, which considers the amount of load at the bottleneck workstation instead of work. Rose [22] proposed one more release policy termed as TOTAL CT by considering the problem of distributed load in wafer fabs. The control criterion in this release policy is the average cycle time, which has to be determined in advance by simulation. Chern and Huang [4] proposed another release policy termed as (k, w) by utilizing the concept of workload regulation and batch-sizing policies to release a job into the fab. Lou and kager [15] proposed a dynamic release policy called as (FRCP) to minimize the inventory cost of the wafer fab. Under this policy, we first divide the job shop into virtual flow shop whose work stations are the job steps of the original system. Then, for each virtual work station the amounts of inventory and surplus are determined. A new job is released to the workstation when its inventory and surplus falls below a predetermined threshold. A very popular release policy namely CONWIP is proposed by spearman et al. [23] to regulate the WIP level of the system. CONWIP sets a limitation for the workload of the overall shop floor so that WIP (which can be measured in terms of number of jobs or processing times) is maintained at a constant level. Chung and Lai [4] proposed another version of CONWIP called as (HPSRC) to obtain a tighter control over a WIP. Consequently, a new job is released into the fab when the number of jobs into the system is less than both the system WIP level and WIP level of the first layer. Descending Control (DEC) release policy is being proposed by Glassey et al. [8] in which they used a hybrid optimization-simulation approach to determine the optimal control set for releasing a job into the fab. In the same year Kim et al. [10] proposed a dynamic release control policy (DRCP) to minimize the cycle time in due date constraint environment. This policy triggers the release of a new job into the fab based upon examination of the projected queue sizes at each workstation over the review horizon. The review horizon is chosen so that it is longer than the maximum of the flow times of product. Lin et al [14] also proposed a dynamic release policy termed as Dynamic releasing scheme (D-Roll) using the concept of rolling correction. Qi et al. [15] proposed WIPLOAD Control (WIPLCtrl) release policy which releases a job into the fab based on a workload for the overall shop floor. The workload is calculated as the sum of the remaining processing times for all the jobs on the shop floor. Tabatabaei and Salazar [24] proposes another version of WIP oriented release policy termed as Effective WIP Dependent (EWD) release policy which releases a job into the fab based on the varying arrival rate which is chosen according to the WIP level at bottleneck workstation.

Recently, Park and Morrison [13] also proposed a controlled release policy for clustered photolithography tools in wafer fabs. However, this release policy is not implemented yet in this simulation study. Reviews with respect to release policies in the semiconductor industry can be partially found in [4, 19 and 20]. Each release policy has its own applied field. Open loop release policy is simple and easy to implement, which is mainly used in some investigations. Closed loop release policy is flexible according to changes in system, so it is used in real manufacturing line. B. Dispatching Rules Dispatching rule determines the sequence in which jobs in front of machine are processed when machines are available. Since, the choice of dispatching rule is not the primary focus of this study. Therefore, most commonly used dispatching rules such as FIFO, LIFO and SIPT are experimented in this simulation study. The FIFO selects the job that arrived first at the queue of the work station. The LIFO rule selects the job that arrived most recently at the queue of the work station and SIPT rule selects the job with the shortest processing time at the current work station. In this study we do not consider any due date oriented dispatching rule to avoid the complexity in interpretation of the results. III. SIMULATION MODEL Given the complexity of semiconductor wafer fabrication, simulation emerges as powerful technique that describes the detail interactions among elements of such a manufacturing environment [16]. In addition, traditional techniques through mathematical models or even deterministic models are simply not adequate to analyze these complex manufacturing environments [1]. Consequently, discrete event simulation is used in evaluating such a complex system. Accordingly, in the next section we discuss the Intel Mini-Fab which is used to build the simulation model. Intel Mini Fab is selected for the construction of simulation model as it exhibits all the characteristic features of real semiconductor wafer fabrication such as re-entrant loops, operators, batching, failures, preventive maintenance, setups, disparate processing, loading and unloading. Moreover, it is a benchmark system for all kinds of semiconductor research and also is a popular one used by several authors for evaluating different sequencing rules [12, 20, 24 and 26]. Additionally, many authors in the literature agree that shop size has no significant effect on the wafer fab performance [2 and 6]. Therefore, Blackstone et al. [3] conclude a small shop can be used with considerable computational savings. A. Intel Mini Fab Description The MIMAC test bed dataset Mini Fab or Intel Mini Fab is used for simulation. It includes six processing steps and five machines distributed in three work stations and the same is presented in Figure 1. The three processing workstation includes diffusion, ion-implantation and lithography respectively. Diffusion workstation consists of two machines A and B that can process batch of 3 jobs at a time and it serves step 1 (S1) and step 5 (S5). Ion-implantation workstation consists of two machines C 2

Proceedings of the 2015 International Symposium on Semiconductor Manufacturing Intelligence (ISMI2015)

and D and it can process one job at a time and serves step 2 (S2) and step 4 (S4). Lithography workstation consists of one machine E that process one job at a time and serves step 3 (S3) and step 6 (S6). Wafer In S1

Station 1

Station 2 S2

Machine A and B A

Machine C and D S4

C

S5 B

S3

SEMATECH for the semiconductor industry [5], cycle time emerged as the number one performance metric for the survey and interview respondents. Some revisions and assumptions have been made to the Mini Fab, these include:  To exclude blocking from the model, the buffers are modeled to have infinite capacity.  Rework, support technician, inter-station travel time and operator’s travelling time is not considered.  For batching products of same production step are batched together at diffusion workstation.  Machine restriction is not considered for the test wafers to avoid the complexity.  The unscheduled or random breakdowns for machines at each station are exponentially distributed with a mean of 50 hours and the repair time is exponentially distributed with a mean of 7 hours.  The initial level of WIP inventory in the system is set equal to zero.  Minutes are the time units.

Station 3 Machine E

S6

E

Out

D

Figure 1. Intel five-machine six steps Mini-Fab [9].

The Mini-Fab operates the 24 hours of the day, 7 days of week. Each day of operations is composed of two shifts of 12 hours. In the Mini-Fab machine failures and emergency repairs occur as random events. Lithography station in Mini Fab is found to be the bottleneck workstation. B. Problem Definition and Objective The problem can be characterized by a set of jobs, where each job requires six operations to complete the fabrication process. The operations must be performed in a specific sequence at specific stations. Since, there are three stations and each job requires six operations; thus each job will visit station twice. In this paper, we evaluate fifteen release policies with three simple dispatching rules. Release policies evaluated were Uniform (UNIF), Workload Regulation (WR), Constant Work-In-Process (CONWIP), Starvation Avoidance (SA), Constant Load (CONLOAD), Total Cycle Time (TOTAL CT), Parametric Workload Regulation (PWR), Dynamic Release Scheme (Droll), WIPLOAD Control (WIPLCtrl), Dynamic Release Control Policy (DRCP), Descending Control (DEC), Workload Regulated Batch Size (k, w), Hierarchical planning system with release control (HPSRC), Effective Work-In-Process (EWIP) and Flow rate Control Policy (FRCP) and dispatching rules include First-In-First-Out (FIFO), Last-In-Last-Out (LIFO) and Shortest Imminent Processing Time (SIPT). The scheduling policies are compared based on the delay/throughput trade-off curve. This curve describes the delay or waiting time or cycle time as a function of fab throughput. Delay or waiting time is defined to be the time a job spends in the fab that is processing time plus waiting time, while throughput is the average number of jobs that leave the fab. Both axes of the delay/throughput trade-off curves are scaled. The horizontal axis corresponds to the mean throughput. We scale throughput values such that one corresponds to the maximum expected output of the fab. The vertical axis corresponds to mean delay. Mean delay entries are divided by the total processing time [7]. Therefore, the objective is to find the scheduling policy that is efficient on the frontier of delay and throughput. In addition, we are assuming that there are no due dates on individual jobs, so performance measures based on meeting due dates will not be considered. The reason to emphasize reducing delay or cycle time is mainly due to the significance of cycle time performance in semiconductor manufacturing. Furthermore, in a project constructed by

IV. Experimental Design To compute the performance measure for scheduling policies, full factorial design is considered in this study and thus total 45 (15 × 3) configurations are studied. This requires the simulation of several runs on the same Mini Fab queuing network. There are two possible approaches for this purpose one is to run several short simulation experiments with different random seed sets for each configuration and the other is to run a single long run for each configuration with a single random seed set. We select a first approach, namely to run several short simulation with different random seed sets for each configuration to avoid the correlation between the batch means. The simulation experiments are conducted on Mini Fab using Arena software developed by Rockwell Automation. A. Performance Measures Considered The scheduling policies are compared based on the delay/throughput trade-off curve. This characteristic curve is selected to evaluate the scheduling policies because it is introduced as the standard factory productivity measurement tool and a key performance indicator in wafer fabrication environment [5 and 16]. Although the mean delay and mean throughput is the main performance measure, the mean WIP at the bottleneck is also important. Since, the queue of work at the bottleneck work station is on average be the biggest queue in the system thus, WIP is computed for bottleneck station. Moreover, it is important to minimize the variability in these performance measures. Therefore, the standard deviation for each performance measure is also computed. However, to measure the regularity in output or throughput, the coefficient of variation of inter-departure (CVID) times is computed. The coefficient of variation (CV) is a relative measure and for any performance measure it is equal to the standard deviation value divided by the average value. Minutes are the time units used for the performance measures except WIP and throughput which is measured in number of jobs. B. Simulation Parameters Due to the large variability in uptimes and repair times introduced by the exponential distributions used in Mini Fab 3

Proceedings of the 2015 International Symposium on Semiconductor Manufacturing Intelligence (ISMI2015) a. Inter-arrival Mean (IM), Cycle Time (Delay), Throughput (TH) Departure Interval (DI), Work-in-process at Bottleneck (WIP at B), Mean Value (Avg), Standard Deviation (STD), Confidence Interval (C.I), Coefficient of Variation (CV).

for machine random failures, it is necessary to collect statistics for a larger number of replications so as to generate acceptable confidence intervals. Therefore, the average values of 200 replications are used to compute the performance measures and the length for each simulation run is chosen as 9600 hours, in which the beginning 4800 hours are considered as the warm-up period to avoid the error due to initial transient condition. This number and length of replications provided uniformly good statistical precision across the outputs (95% confidence interval half widths within 3% of the respective sample means). The statistical analysis is performed using the paired student’s t-test with a 95% confidence interval. Detailed description of a paired t-test can be found in Law and Kelton [14]. In Mini Fab, the work station (LT) for the process of lithography is found to be the bottleneck for all the tested cases. The different dispatching rules are applied only at the bottleneck work station. The different system loads are controlled by start rate for UNIF, critical values for WR and DRCP and WIP levels for CONWIP, DEC, HPSRC and EWIP, safety stock for SA, reference WIPLOAD for WIPLCtrl, average processing time between wafer start and first bottleneck stage for Droll, threshold value for CONLOAD, average remaining cycle time for TOTAL CT, (k, w) value for (k, w), reference inventory and reference surplus value in FRCP and parameter value in PWR.

TABLE II.

TH

Avg

STD

2306

818

113

2371 2442 2539 2680 2970 3530 5216 2015 6

880 909 1003 1062 1226 1468 2007

122 126 139 147 169 203 278

DI Avg

STD

1116

258

414

1161 1210 1264 1321 1384 1456 1532

248 237 228 217 208 197 188

398 382 367 351 334 312 283

1.6 1.6 1.61 1.61 1.62 1.61 1.58 1.51

Avg

ST D

258

414

248

398

237

382

228

367

217

351

208

334

197

312

188

283

494

1565

184

260

184

260

169

1371

190

Avg

STD

1117

257

409

1161

248

397

2482

1595

221

1210

238

387

2575

1837

254

1263

227

373

2743

2261

313

1384

217

357

3030

3065

424

1453

208

340

3549

4602 1293 9 1380 6

637

1532

198

321

1793

1542

187

295

1913

1384

186

285

TABLE III.

WIP at B CV

1.6 1.6 1.6 2 1.6 4 1.6 4 1.6 3 1.6 2 1.5 8 1.5 3

Avg

STD

2.34

3

2.61

3.29

3.06

3.76

3.58

4.19

4.43

5.88

5.93

7.58

8.8 20.7 6 128. 11

11.63 26.47 5.88

UNIF/ SIPT POLICIY PERFORMANCE IN MINI FAB TH

Delay

DI

Avg

STD

95% C.I

Avg

Avg

STD

2233

712

99

1116

258

398

2292

757

105

1162

248

386

2330

768

107

1211

238

372

2400

807

112

1264

228

360

2520

852

118

1321

218

347

2734

953

132

1385

208

336

3037

1064

148

1454

198

321

4027 1062 8

1395

193

1532

188

308

2046

283

1600

180

298

WIP at B CV

1.5 4 1.5 6 1.5 6 1.5 8 1.5 9 1.6 1 1.6 2 1.6 4 1.6 6

Avg

STD

1.92

2.52

2.18

2.8

2.4

2.96

2.79

3.27

3.31

3.64

4.32

4.32

5.88 11.0 1 48.1 6

5.2 7.58 12.26

a. Inter-arrival Mean (IM), Cycle Time (Delay), Throughput (TH) Departure Interval (DI), Work-in-process at Bottleneck (WIP at B), Mean Value (Avg), Standard Deviation (STD), Confidence Interval (C.I), Coefficient of Variation (CV).

It is observed from both the Tables I – III and Figure 2, that Uniform release policy with SIPT dispatching rule outperformed both FIFO and LIFO dispatching rule. This is because SIPT reduces setup time at bottleneck workstation by choosing the same job every time. It is also noticed from the last row of Table II and Table III that for all values of throughput rate SIPT produced schedules with less mean delay than FIFO, achieving reduction of approximately 47% in mean delay at the throughput rate of about 1 job per 178 minutes. Likewise, it is noted from Table II and Table III that for all values of throughput rate FIFO produced schedules with slightly less mean delay than LIFO except for the throughput rate of about 1 job per 178 minutes.

1.41 3565

1223

DI

Avg

a. Inter-arrival Mean (IM), Cycle Time (Delay), Throughput (TH) Departure Interval (DI), Work-in-process at Bottleneck (WIP at B), Mean Value (Avg), Standard Deviation (STD), Confidence Interval (C.I), Coefficient of Variation (CV).

WIP at B CV

2346

5862

UNIF/ FIFO POLICIY PERFORMANCE IN MINI FAB

Avg

STD

5624

A. Effect of Dispatching Rules First, three dispatching rules are selected to evaluate the performance measures of Mini Fab that include FIFO, LIFO and SIPT with UNIF release policy. Accordingly, the simulation result for Uniform release with all dispatching rules are provided in Tables I to III and for the same delay/throughput curve is presented subsequently in Figure 2.

95% C.I

Avg

95% C.I

2389

To interpret the results of our simulation experiment on Mini Fab we first consider each release policy separately and observe the effect of varying the dispatching rule within each release policy. Second, we fix the dispatching policy and compare the different release policies. The purpose of these experiments is to understand the behavior of Mini Fab when introducing different scheduling policies.

Delay

TH

Delay

V. EXPERIMENTATION AND RESULTS

TABLE I.

UNIF/ LIFO POLICIY PERFORMANCE IN MINI FAB

4

Proceedings of the 2015 International Symposium on Semiconductor Manufacturing Intelligence (ISMI2015)

Figure 2. UNIF Release Performance in Mini Fab

Figure 3. Release Policies Performance in Mini Fab with SIPT dispatching rule

With respect to the coefficient of variation of inter departure times (CVID) SIPT produced schedules with less CVID than both FIFO and LIFO for throughput rate values greater than of about 1 job per 218 minutes. The coefficient of variation of inter departure is a measure of regularity of output. Moreover, SIPT dispatching rule produced schedules with shorter queue of work at the bottleneck work station. Subsequently, other fourteen release policies with three dispatching rules are analyzed. However, the detailed simulation results for (14 × 3 × 200) simulation runs generated similarly but are not given in detail in this paper due to space restriction. Therefore, only important observations in case of other fourteen release policies with three dispatching rules are discussed further. It is observed that SIPT dispatching rule outperformed both FIFO and LIFO dispatching rules in all release policies except for EWIP in which FIFO outperformed other two dispatching rules. The reason for this change could be the variability of WIP at the bottleneck workstation which triggers the release of jobs into the system under this release policy.

The estimation for bottleneck workload is not proper under PWR release policy due to the normalization of processing time and thus it increases the delay. The control criteria in EWIP release policy is the arrival rate which is varied according to the WIP of bottleneck workstation. Accordingly there is an increase in delay due to high variability in arrival rate. The second best release policy is (k, w) which releases jobs based on the bottleneck workload in batches and thus reducing the waiting time for batch operations and thus reducing the delay. Starvation avoidance release produced schedules with approximately 35% less mean delay than (k, w) release policy. The relative performance of WR, CONWIP, WIPLCtrl, Droll, DEC, CONLOAD, TOTAL CT, DRCP and HPSRC is insignificant with respect to mean delay difference at lower throughput rate values. However, WR outperformed other release policies at higher throughput rate values closely followed by CONLOAD. WR release policy produced schedules with approximately 0.84%, 8.1%, 11.2%, 10.8%, and 14.5% less mean delay than CONLOAD, CONWIP, TOTAL CT, DRCP and DEC respectively for throughput value (95% of expected capacity) and produced schedules with approximately 15% and 12% less mean delay than WIPLCtrl, and HPSRC respectively at the throughput value (93% of expected capacity). For the throughput value (94% of expected capacity) WR release policy produced schedules with approximately 4% less than Droll release. The Droll and CONWIP release policy were almost identical with respect to mean delay as their plots overlap. With respect to CVID times, there is almost no difference among these release policies. The WR release policy produced shorter queue at the bottleneck workstation. Moreover, WR release showed less variation in queue length at the bottleneck workstation closely followed by HPSRC, CONLOAD, Droll and WIPLCtrl release policy respectively. In conclusion, with respect to Mini-Fab, varying the dispatching rule for a fixed release policy did not show as much mean delay sensitivity as fixing the dispatching rule and varying the release policy. Therefore, it can be concluded that release policies plays more significant role than dispatching rules in performance of wafer fabs. It is observed that with most of the release policies, SIPT dispatching rule produced less mean delay at all throughput rate values except for EWIP release policy in which FIFO

B. Effect of Release Policies We choose for this analysis to fix the dispatching rule to SIPT, given its overall good performance. However, we simulated with other dispatching rules as well but due to the restriction of space we choose to discuss only SIPT dispatching rule. Moreover, similar observations are found even with other dispatching rules. It is evident from the Figure 3, that the starvation avoidance (SA) produced schedules with less mean delay than other fourteen scheduling policies at all the throughput rate values. The improvement was most remarkable against Uniform release policy, where the mean delay reduction is approximately 81%. Moreover, SA outperformed Uniform release policy with respect to CVID times at higher throughput rate values. When compared to WR, SA produced schedules with approximately 50% less mean delay at the higher end of throughput range. It is important to note that the performance of all closed loop release policies was better than open loop release policy except for FRCP, PWR and EWIP. The objective of FRCP release policy was to minimize the work in process inventory cost, so under this release policy jobs get on hold at each step and therefore it increases the delay. 5

Proceedings of the 2015 International Symposium on Semiconductor Manufacturing Intelligence (ISMI2015) [7]

outperformed SIPT dispatching rule. The reason could be that SIPT dispatching rule give preference to the job which is about to leave the fab. Hence, it reduces the delay and increase the throughput. However, in case of EWIP release policy the release of jobs into the system is based on the arrival rate which is varied in accordance to the WIP at the bottleneck work station. The SIPT dispatching rule allow more jobs to go out. Thus in this way, it may reduce WIP at the bottleneck work station, which in turn brings more jobs into the system and consequently it increases the delay. Generally, it is concluded that SIPT was the best dispatching rule and SA the superior release policy.

[8]

[9]

[10]

[11]

VI. CONCLUSION In this paper, a set of simulation experiments is carried out using a Mini Fab model on Arena simulation platform to gain insights into the behaviour and impact of the scheduling policies in a wafer fabrication environment. The relative effect of fifteen release policies with three dispatching policies are observed and analysed subsequently. In this study, 45 scheduling policies are simulated by making all possible combinations of fifteen release policies that include Uniform, WR, CONWIP, SA, WIPLCtrl, Droll, DEC, TOTAL CT, CONLOAD, HPSRC, DRCP, FRCP, PWR, EWIP and (k, w) with three dispatching rules FIFO, LIFO and SIPT. The simulation results show that an appropriate choice of release policy can significantly improve the system performance with respect to mean delay and throughput rate. The improvements caused by the controlled or closed loop release policies are greater than the open loop release policies in most of the cases. Among the fifteen release policies, SA outperforms the others at all throughput rate values and SIPT was the best dispatching rule in almost all the scenarios. The important conclusion drawn from this study is that varying the dispatching rule for a fixed release policy did not show as much mean delay sensitivity as fixing the dispatching rule and varying the release policy. This conclusion is consistent with the argument given by [27, 7 and 10]. This conclusion motivates us to propose an efficient release policy for a wafer fabrication environment which will be more responsive and robust to the system variability’s and will be considered for future work.

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