Simulink Library Development and Implementation for VLSI Testing in ...

Simulink Library Development and Implementation for VLSI Testing in Matlab Gurinder Pal Singh and Balwinder Singh Acadamics and consultancy Services Division Centre for Development of Advanced Computing, Mohali, India [email protected], [email protected]

Abstract. In ATPG, faults in the VLSI circuits are detected with D-algorithm, SPODEM and FAN algorithms. This paper gives the emphasis on presenting first two algorithms in MATLAB. Implementation of these algorithms for complex VLSI circuits is very tedious job. So an environment in Simulink is presented here, which is further verified on some benchmark circuits. Simulink provides an environment for intellectual properties (IP) building block based circuit engineering design as well as project simulation environment. In PODEM the requirement is the exact values of Controllability and Observability. For effective and fast calculation of COM, Simulink based designed models are used. Keywords: ATPG (Automatic Test Pattern Generator), COM (Controllability and Observability Measures), CUT (Circuit Under Test), S-PODEM (Sequential-Path Oriented Decision Making), VLSI (Very Large Scale Integrated) Circuits, GUI (Graphic User Interface), CC (Controlled Controllability), CO (Controlled Observability).

1 Introduction Selection of proper test vector is essential, after discarding equivalent faults. The test vectors are generated manually or by special software tool which automates the process, that is Automatic Test pattern Generator (ATPG) [6]. The ATPG is fault oriented; it selects a fault from list of candidate faults, and attempts to create a test for fault. There are well-known three algorithms for the ATPG for digital circuits. Each algorithm require some information related to the DUT (Device under Test) i.e, information related to the circuit design, the fault list information, information of the individual components and their fault free behavior, the way through which fault effects are propagates to primary outputs and the fault equivalence list. Each algorithm operates with fault generator, to minimum collapsed fault list. ATPG algorithms are multi-purpose that means they are able to; generate circuit testpatterns, to find the redundant circuit logic, to match circuit implementation with another circuit. Those three algorithms are: D-Algorithm, PODEM (Path Oriented Decision Making) Algorithm and Fan algorithm. A. Mantri et al. (Eds.): HPAGC 2011, CCIS 169, pp. 233–240, 2011. © Springer-Verlag Berlin Heidelberg 2011

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The functioning of D-Algorithm is mainly based on the Roth’s five valued logic shown in table1 [10], Developed by Roth in 1960s. This algorithm uses a logical value for representation of “good” and “faulty” circuits. The method is based on the intersection of the D-cubes. The supported 5 values are D,D, 1, 0, X. PODEM algorithm applied of combinational circuits is also based on this algebra but the difference is that the through which the values of the primary input for the objective defect is decided that is the backtracing applied in PODEM is totally based on the COM [14, 15]. Controllability is VLSI circuit is the difficulty of setting a particular logic signal to 1 or 0. Observability is the difficulty of observing the state of a logic signal [17]. For DUT, includes the sequential elements that are flip flops, this 5-valued logic algebra is not able to detect the fault. For that the algorithm used is sequential PODEM (S-PODEM). This approach uses the concept of time compression and synthesizes in one time frame a single test vector representing the compressed form of multiple time frames. The single vector is then expanded into a test sequence [21]. For sequential circuit testing, when a test pattern is applied for the fault propagation, then each signal line can be static or pulsating. So for these pulsating lines a ‘P- model’ value is used to reflect the behavior of the pulsating line model is used for CUT. So for the S-PODEM a ’11-value’ logic model is used to reflect the behavior of each and every gate and flip flop in the CUT. These Values of 11-value logic that are: D, D, 0, 1, X, P, P0, P1, 1P, 0P and PP. Where D: denotes logic value 1 in the good circuit and 0 in faulty circuit. D: indicates logic value 0 in the good circuit and 1 in faulty circuit. P: value used for any pulsating signal. P0 and P1: indicates a pulsating signal in the good circuit and static value 0(1) in the faulty circuit respectively. 0P and 1P: indicates 0 in the good circuit and P in the faulty circuit respectively. PP: represents a signal pulsating in the good machine with another signal pulsating in the faulty machine [21]. In sequential circuits the primary inputs remain at some static values during test generation for a particular fault. Only a few primary inputs exhibit pulsating behavior. Some common and important terms in S-PODEM are explained below: Static Lines: A line which remains at a static value for both faulty and faulty free circuits, during the entire test operation is regarded as a static line, and is designated by SLS. Pulsating Lines: If line faces a change in its logic value in any one of faulty or faulty free circuits during the test experiment, then that line is known as pulsating line. In section 2 includes the related work. Section 3 explains the way to model Dalgorithm and PODEM in MATLAB/Simulink and shows the modified library of Simulink representation. Designing of SPODEM is represented on benchmark circuit S27 and Serial Multiplier is shown in section 4. At the last in section 5, paper is concluded by presenting all results of designed circuit for purposed environment in tabular form, followed by future work.

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2 Related Work Tommo Inoue et. al suggest the fast detection of the faults in ATPG by following 5valued algebra instead of following 16-valued logic[2]. Jozesf Sziary et. al presents two algorithm that are D-algorithm and composite justification are analyzed on the basis of computational complexity, for calculating fault detection for digital circuits. From analyzing these two it is concluded that composite justification requires less computational steps [3]. Bushnell M. et. al in his book tells about ATPG algorithms that are POPDEM and D algorithm described. Benefits of using PODEM over D algorithm are defined by considering the speed of testing as the main factor [10]. Wen-Ben Jone ,et. al gives idea on Testing of sequential element that is flip flop. A method for sequential element testing is suggested which is based a new PODEM technique which depends on 11- value logic [21]. Mohamed Lamoussi et. al presents all the basic formulas for the calculation of controllability and observability based on Rutman’s system model are used, which are further based on Reduced Ordered binary Decision Diagram (ROBDD) [23]. Noatake Kamuira et. al introduces the use of COM to guide D algorithm for multi valued logic, and used for determining the execution of the D-drive at the fan out[17].

3 Simulink Based Implementation for Testing for Stuck-at Faults Using D-Algorithm and PODEM 3.1 Testing for Combinational Circuits D-cubes are the collapsed truth table that can be used to characterize an arbitrary logic block. D-cubes are utilized to describe both the faulty and normal functions simultaneously. Conceptual purpose of the D-cubes is the path sensitization. Notation D represents logic value “1” in the good circuit or fault free and “0” in the faulty circuit. Compliment of D represents “0” in the fault free circuit and “1” in the faulty circuit, shown in table1. So In D-Cubes main parameters are D, D and X. But these are not understandable to Simulink. To interpret these to Simulink some notations are used that are; For interpretation of ‘D’ it is replaced with the numeric value 2, similarly ‘D’ is replaced with 3 and parameter unknown (‘X’) is replaced with 4 illustrated in table 1. Table 1. Interpretation values for the D-Logic 0

1

2

3

4

0

1

D

D

X

Now based on these values the behavior of all logic gates is defined in Simulink so that it is understandable to user and Simulink both. D-cube is generated for fault

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propagation. For any fault to be detected, condition is that its effect should be propagated to the output [9]. By keeping this in view logic gates are designed by transporting the translated values of D-cubes into 2-D lookup tables of Simulink library. Its rows act as first primary input and column as second primary input. All logic gates are designed and properly masked and added to Simulink library (as shown in figure 1) permanently by modifying “slblocks.m”, to have user friendly environment.

Fig. 1. Updated Simulink library with D-cube based user designed logic gates

By using this newly designed logic gate library, 74181-4-bit ALU is designed in Simulink as shown in figure 2. To make it utilized for testing purpose some random faults are forced in the circuit shown in testing model, which are also mentioned in table 2 and this table also includes their respective test patterns. Randomly forced fault and their respective patterns for fast adder 74823 is given in table 3

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Fig. 2. D-algorithm based testing model for 74181 4bit ALU using library shown in figure 3.1 Table 2. Test vector based on D-algorithm for forced SA-0,1 for ALU- 74181 4-bit

S.NO.

Nodes SA-0, SA-1

Simulated test vectors for SA-0

Simulated test vectors for SA-1

1.

1c10a

01011011011101111

11001110111110110

2.

ce32j

11100110111101101

01111001101101111

3.

Bd6j

11011001111010111

00100110011010001

4.

45fg

11110110001101111

11011001110010010

5.

789l

11110111101111111

11010001010011000

6.

kmnpqrs

11010011110111101

00111001110011100

Table 3. Test vector based on D-algorithm for forced SA-0,1 for fast adder 74283 S.NO.

Nodes forced

Simulated test

Nodes forced for

Simulated test vectors for

for SA-0

vectors for SA-0

SA-1

SA-1

1.

aceg

11101011111111

dfhi

11010011000111

2.

klmp

11000110101101

ronq

01110110011101

3.

suvy

11011100110110

twxz

11011001111000

4.

b145

11101001101101

236

10010110011101

3.2 Testing for Sequential Circuits As mentioned in [20] testing of sequential circuits is depends on 11 valued logic called sequential PODEM, discussed earlier. As for 5-valued D-logic these 11-valued

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logic is also interpreted in to numeric form to make it understandable by the Simulink environment. This is represented in table 4. Table 4. Interpretation values for the D&P-Logic

0 0

1 1

2 D

3 D

4 P

5 0P

6 1P

7 P

8 P0

9 P1

10 PP

By using these values, a noble Simulink library model is developed for sequential testing, as done in pervious section 3.1. But in sequential based PODEM testing techniques COM calculations are essential [13]. Need of these depend upon the complexity of any circuit, because at certain levels in a CUT to propagate faults to PO it is not clear which input node is set for fault propagation. In that case controllability and observability measures are helpful. Here these are also calculated by using COM user Library model for Simulink and presented in table 6. To present sequential testing CUT taken is S27. Primary input values taken are;CC0a, CC1a=1 for sequential_NOR_Gate_Sys, sequential_Not_Gate_Sys,sequential_OR_Gate. CC0b, CC0b, CC1b=1 for sequential_NOR_Gate_Sys3.

Fig. 3. S27 testing for SA faults with SPODEM

To test this circuit for stuck-at0-1, faults are forced randomly as shown in figure 5. Table 5. COM Values for S27 Gates sequential_OR_Gate sequential_OR_Gate1 sequential_Not_Gate_Sys1 sequential_NAND_Gate D flip-flop1 D flip-flop2 D Flip-flop3

CC0Z 2 2 2 6

CC1Z 1 2 10 2

CC0Q x x x x 4 4 4

CC1Q x x x x 6 14 7

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Table 6. Test vectors for S27 S.NO.

1. 2. 3. 4. 5.

Nodes forced for SA0,SA-1

Simulated test vectors for SA-0

Simulated test vectors for SA-1

abf oec knf ghj ilm

010x 01x0 1101 011x 1100

11x0 1001 0010 100x 0011

4 Conclusion In this paper a new approach for VLSI testing in MATLAB is proposed and implemented. In this technique we have designed a user library for Simulink by using 2-D logic array block, for D-algorithm and SPODEM. By using that libraries benchmark circuits are implemented for random testing. Results are presented in tabular form. Controllability and Observability measures required in PODEM are calculated by using Simulink model for CUT. This environment is useful for VLSI testing to make understand the concept of testing to students and can be used as teaching tool.

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