Simultaneous Redundant Via Insertion and Line ... - Semantic Scholar

Simultaneous Redundant Via Insertion and Line End Extension for Yield Optimization Shing-Tung Lin1, Kuang-Yao Lee2, Ting-Chi Wang1, Cheng-Kok Koh3, and Kai-Yuan Chao4 1Department

of Computer Science, National Tsing Hua University, Taiwan 2Taiwan Semiconductor Manufacturing Company, Taiwan 3Electrical and Computer Engineering, Purdue University, USA 4Intel Corporation, USA

Outline y Introduction y Preliminaries and Problem Definition y Conflict Graph Construction y ILP Approach y Experimental Results y Conclusion

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Introduction y One popular topic of DFM is to minimize the

chip failure rate caused by via defects. y Reducing via defects and improving IC yield can be done by techniques such as redundant via insertion and line end extension.

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Redundant Via Insertion

layer 2 via cut layer 1

lateral view

aerial view Redundant via

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Line End Extension E E

E E (a) without line end extension

α>1

E αE

αE

E Line End Extended Via (LEEV) 5

(b) with line end extension

[ICCAD ‘06] K.-Y. Lee, T.-C. Wang, and K.-Y. Chao, “Post-routing redundant via insertion and line end extension with via density consideration,” in Proceedings of International Conference on Computer-Aided Design, 2006

Line End Extension (Cont’d) y Eight types

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LEH

LEV

LEB

NLEB

LEU

NLEU

LED

NLED

layer 2 via cut layer 1

Motivating Example y Four single vias (v1, v2, v3, v4) and four

obstacles (o1, o2, o3, o4). y Failure probabilities Single via

Redundant via LEB

LEH/LEV

0.005

0.0001

0.0006

layer 1 via cut layer 2

0.0003

o3

o1 v2 v1

v3 v4

7

o2

o4

Motivating Example – Case A ([ICCAD ‘06]) y Two redundant vias. y One line end extension (LEH). y Via yield = (1-0.005)×(1-0.0001)2×(1-0.0006) = 0.9942 layer 1 via cut layer 2

v5 o1

o3

v2 v1

v6

v3

v4 8

o2

o4

Motivating Example – Case B y One redundant via. y Three line end extensions (LEH). y Via yield = (1-0.0001)×(1-0.0006)3 = 0.9981 layer 1 via cut layer 2

v5 o1

o3

v2 v1

v3 v4

9

o2

o4

Motivating Example – Case C (using our algorithm) One redundant via y Three line end extensions (one LEB via and two LEH vias) y Via yield = (1-0.0001)×(1-0.0003)×(1-0.0006)2 = 0.9984 y

layer 1 via cut layer 2

v5 o1

o3

two LEH’s

v2 v1

v3 v4

10

o2

o4

one LEB

Our Contributions y Considering eight types of line end extensions. y Formulating a via yield optimization problem

by simultaneous Redundant Via Insertion and Line End Extension (RVI/LEE). y Proposing a zero-one Integer Linear Program (0-1 ILP) based approach to solve the RVI/LEE problem optimally. y Using two speedup techniques to reduce runtime. y Providing extensive experimental results to support our apporach. 11

Outline y Introduction y Preliminaries and Problem Definition y Conflict Graph Construction y ILP Approach y Experimental Results y Conclusion

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Double Via (DV) y Four types

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DVU

DVR

DVD

DVL

y Feasible Double Via (fDV) y No violation of any design rule

Line End Extended Via (LEEV) y Eight types (LEH, LEV, LEB, NLEB, LEU,

NLEU, LED, and NLED) y Feasible Line End Extended Via (fLEEV) y

No violation of any design rule

y Special cases

αE αE

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αE

Via (Treated as a LEEV)

αE

Failure Probabilities y Thirteen types of vias y DVU, DVR, DVD, DVL y LEH, LEV, LEB, NLEB, LEU, NLEU, LED, NLED y Single Via type (SV) y Each type of via has an independent failure

probability. y Via yield is computed by the product of nonfailure probabilities of all vias.

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Problem Definition y RVI/LEE problem y Given a routed design, maximizing the via yield of the design by Redundant Via Insertion and Line End Extension. y Via yield model

AV: the set of all single vias in the original layout. y vt(i): the resultant via type of i after redundant via insertion and line end extension. y

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Outline y Introduction y Preliminaries and Problem Definition y Conflict Graph Construction y ILP Approach y Experimental Results y Conclusion

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Conflict Graph (CG) y CG(V, E = EI∪EX) y Vertex set V y At most thirteen vertices (four fDV vertices, eight fLEEV vertices, one SV vertex) for each single via. y Edge set E y An edge exists if two end vertices cannot be chosen simultaneously. y Internal edge set EI: each edge connects two vertices from the same single via. y External edge set EX: each edge connects two vertices from different single vias. 18

Construction of CG O1

layer 1 via cut layer 2

r3 r2

v1 r1

V1

r4

v2

r5

confliction

Internal edge External edge

X axis r1

LEH

r2 LEV

LEU 19

design rule violation

NLED

r4 r3

V2 SV

NLEU NLEB

LED

LEB

r5

Outline y Introduction y Preliminaries and Problem Definition y Conflict Graph Construction y ILP Approach y Experimental Results y Conclusion

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0-1 ILP Formulation

Vi: the set of vertices that originate from single via i. t(vi,j): via type of vertex vi,j . ri,j: binary variable (1: vi,j is chosen; 0: vi,j is not chosen) 21

0-1 ILP Formulation (cont’d)

Subject to:

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V1

V2 SV

DV2

Internal edge External edge

LEH DV1

SV

AV = {V1, V2} V1 = {v1,SV , v1,LEH} V2 = {v2,DV1 , v2,DV2 , v2,SV} max r1,SV × log(1-Prob(t(v1,SV )))+ r1,LEH × log(1-Prob(t(v1,LEH))) + r2,DV1 × log(1-Prob(t(v2,DV1)))+ r2,DV2 × log(1-Prob(t(v2,DV2))) + r2,SV × log(1-Prob(t(v2,SV)))

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subject to: r1,SV ={0,1} r1,LEH ={0,1} r2,DV2 ={0,1} r2,DV3 ={0,1} r2,SV ={0,1} r1,SV + r1,LEH = 1 r2,DV1 + r2,DV2 + r2,SV = 1 r1,LEH + r2,DV1 ≤ 1

Speedup Methods (Pre-selection) y Pre-selection y Reducing CG size. y A vertex can be pre-selected if its failure probability is the lowest almost all vertices originating from the same single via and it is not connected by any external edges. Pre-selected vertices 0.0006

0.0001 V2

V6

V1 V4

V3

0.0003

Internal edge External edge 0.0001

V5

0.0006

0.0003

Pre-select v6 first , then pre-select v1. 24

Speedup Methods (Connected Components) y Connected components y Each is separately solved by a 0-1 ILP. Vertex group External edge

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Two connected components.

Speedup Methods (Cont’d) y Overall approach y First reducing the size of the conflict graph by preselecting vertices. y Then dividing the remaining graph into connected components, and using the 0-1 ILP approach for every connected component. y At the end, collecting all the individual solutions of connected components and the pre-selected vertices to produce the final solution.

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Extension y

RVI/LEH problem [ICCAD ‘06] y Objectives: to first insert as many redundant vias as possible

and to then replace as many remaining single vias by LEH vias as possible. y

Modifications y CG: keeping vertices of double vias, LEH’s, and SV’s as well

as their associated edges. y Objective function of 0-1 ILP:

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Outline y Introduction y Preliminaries and Problem Definition y Conflict Graph Construction y ILP Approach y Experimental Results y Conclusion

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Experiment Platform and Test Cases y CPU: 2.4GHz y RAM: 8GB y ILP solver: lp_solve

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Failure Probabilities Prob(SV)

Prob(DV)

Prob(LEB)

Prob(NLEB)

5E-6

(5E-6)/40

(5E-6)/11

(5E-6)/10

Prob(LEH)/Prob(LEV) Prob(LEU)/Prob(LED) (5E-6)/8

Prob(NLEU)/Prob(NLED) (5E-6)/5

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(5E-6)/6

Yield Comparison (Original vs. Ours)

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1

1.91

Yield Comparison (RVI vs. Ours)

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1.71

1.91

CG Information (RVI vs. Ours)

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Runtime Comparison (RVI vs. Ours)

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RVI/LEH Results ([ICCAD ‘06] vs. Ours)

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Outline y Introduction y Preliminaries and Problem Definition y Conflict Graph Construction y ILP Approach y Experimental Results y Conclusion

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Conclusion y We have formulated a problem of

simultaneous redundant via insertion and line end extension. More than one type of line end extension is considered. y The objective function to be optimized directly accounts for via yield. y

y We have presented a 0-1 ILP based approach. y Equipped with two speedup techniques. y Extensive experimental results have been

shown to support our approach. 37