Single chip frame buffer and graphics accelerator

USO0RE37944E

(19) United States (12) Reissued Patent

(10) Patent Number: US RE37,944 E (45) Date of Reissued Patent: Dec. 31, 2002

Fielder et al. (54)

SINGLE CHIP FRAME BUFFER AND

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GRAPHICS ACCELERATOR

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(75) Inventors: Dennis A. Fielder, Herts (GB); James -

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Related U-S. Patent Documents

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5,712,664 A * 1/1998 Reddy ...................... .. 345/519 FOREIGN PATENT DOCUMENTS

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Randy Torrance >Ot::;aa(CA)~’ Cormac M. O’Connell, Kanata (CA)

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5,572,655 A * 11/1996 Tuljapurkar et al. ...... .. 707/526

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Filed:

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(21) Appl. No.: 09/434,331 (22)

Foss et al.

3/1989

OTHER PUBLICATIONS

,

“The integrated display controller (IDC) for VLSI design

(51)

7 Int. Cl. .............................................. .. G06F 15/76

Workstation”b Jur en Stark, Com uter & ra hics vol. 11, N 2 1853/19; 1987 * P g P

(52)

US. Cl. ..................... .. 345/519; 345/546; 345/559;

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100 MpIxel/sec single chip integrated graphics controller

(IGC)” by D. Mansharamani et al, IEEE 1991 custom

(58) Fleld of seagcrssiis/ 546, 545, 559; 365/189.07, 203, 276, 230.06, ’

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integrated circuits conf,

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56 ( )

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May

1991, PP.

(List continued on next page.) Prim/1ry Examiner—Kee M. Tun g

(74) Attorney, Agent, or Firm—Shapiro Cohen (57) ABSTRACT

U.S. PATENT DOCUMENTS 4,646,151 A

12—15

16.5.1—16.5.4.*

Welles, II et al.

........ .. 348/513

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4,691,295 A

9/1987 Erwin et al. .............. .. 345/188

A slngle ChIP dlsplay Processor comprlsed Of a dynamlc random access memory (DRAM) for storing at least one of

4,740,782 A

4/1988 Aoki et a1, ,,,,, ,,

345/205

4,918,526 A *

4/1990 Lewis et al. ....... ..

348/580

graphics and video pixel data, a pixel data unit (PDU) for

5,027,212 A

6/1991 Marlton et al

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processing the pixel data, integrated in the same integrated

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1/1992

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circuit (IC) Chip as the DR AM, the 1C Chip further Com_

prising a massively parallel bus for transferring blocks of

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2/1994 Gillingham .......... .. 365/189.07

5,305,283 A

4/1994 Shimokura et a1.

5,392,391 A *

2/1995 Caulk, Jr. et al. ......... .. 395/503

Subsequent dlsplay of Processed Plxel dam

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pixel data at the same time from the DRAM to the PDU, Whereby the PDU can process the'blocks of pixel data for 26 Claims, 19 Drawing Sheets

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US RE37,944 E Page 2

OTHER PUBLICATIONS NEC Research and Development, vol. 33, No. 4, Oct. 1992

Tokyo, JP, pp. 585—594 “Integrated Mernory Array Processor”.

IEEE Journal of So1id—State Circuits, vol. 25, No. 1, Feb. 1990 N.Y.

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