Special Issue On Asynchronous Circuits And Systems - IEEE Xplore

Scanning the Issue Special Issue on Asynchronous Circuits and Systems I. INTRODUCTION Welcome to this Special Issue on asynchronous circuits and systems. Most modern digital systems are built using synchronous circuits, which operate under control of a global clock. Asynchronous circuits, in contrast, are those which do not use a global clock. While research in asynchronous design goes back to the mid 1950’s and has received varied levels of attention over the years, there is now a major and ongoing resurgence of interest. In the last decade, projects in industry (Intel, Philips, Sun Microsystems, Sharp Corporation) and academia have demonstrated that it is possible to design asynchronous circuits which exhibit significant benefits on nontrivial realworld examples. In fact, in 1998, entirely asynchronous integrated circuits (IC’s) have appeared in the commercial market: a family of baseband IC’s for pagers developed by Philips Semiconductors, based on an 80C51 microcontroller. In addition to fabricated chip designs, there have been significant advances of several critical enabling technologies: mature computer-aided design (CAD) tools; testability and design-for-testability techniques; and practical algorithms for timing analysis and formal verification. Asynchronous designs promise a number of advantages over synchronous designs. These include: high performance, low power, improved noise and electromagnetic compatibility (EMC), and ease of interfacing to heterogeneous systems. However, an asynchronous methodology also brings many challenges and is not a cure all: it is easy to demonstrate many examples where the above advantages are not realized. Therefore, an important theme of this Special Issue is to indicate where the opportunities for asynchronous design appear, and how and when these advantages can be obtained. This Special Issue is basically a “snapshot” of the stateof-the-art of current asynchronous research. The idea for this issue came about in early 1997, at around the time of the IEEE Async’97 Symposium (also known as the Third IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems). The majority of the articles in this issue first appeared in preliminary form in this symposium but have since been revised, expanded, and re-refereed for publication here. However, in addition, Publisher Item Identifier S 0018-9219(99)00877-4.

several other interesting articles were solicited in order to achieve a more balanced coverage of the field. We should also add a caveat: the bias of this issue is somewhat toward fabricated chips, both applicationspecific integrated circuits (ASIC’s) and processors, which demonstrate real benefits against comparable synchronous designs. However, we also include several representative articles on other topics: CAD tools, analysis techniques, and testability. In the remainder of this introduction, we quickly scan and summarize the contents of the issue: the two introductory articles and the ten invited articles. II. THE ARTICLES: A QUICK SCAN In “Scanning the Technology: Applications of Asynchronous Circuits,” we give an introduction to the “opportunities” for asynchronous design in the current world of technology. We focus on four potential advantages over synchronous design: 1) high performance; 2) low power; 3) improved noise and EMC; and 4) ease of interfacing in heterogeneous systems. For each of these topics, we illustrate the advantages with a number of recent asynchronous case studies. Our emphasis is especially on real-world examples whenever possible, i.e., industrial designs and fabricated chips. We also highlight throughout the challenges and difficulties faced by asynchronous design methods. Finally, we briefly survey some recent asynchronous CAD tools and testability techniques. Both CAD tools and testability are critical technologies which enable the commercial development of asynchronous design. The first regular article in the issue, “Modeling and Design of Asynchronous Circuits,” also written by us, is a different type of introduction to the field: a technical tutorial, introducing some of the key design styles. The article proceeds, bottom up, from simple gates to networks of gates, all the way up to hardware description languages and system synthesis methodologies. Along the way, the article introduces basic issues (hazards) and circuit models (fundamental-mode and speed-independent) and then presents some common approaches to designing asynchronous control circuits (speed-independent versus burstmode) and data-path circuits (bundled data versus delayinsensitive codes). Finally, it presents a systems architecture that supports high-level language-based synthesis tools.

0018–9219/99$10.00  1999 IEEE PROCEEDINGS OF THE IEEE, VOL. 87, NO. 2, FEBRUARY 1999

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The next article, “AMULET2e: An Asynchronous Embedded Controller” by Furber et al., describes a complete fabricated implementation of an asynchronous embeddedsystem chip. The processor core is 32-bit ARM-compatible with a 4-kbyte pipelined cache, and it also includes a flexible memory interface with dynamic bus sizing. The chip demonstrates performance and power-efficiency which are competitive with synchronous designs. The chip also has some uniquely asynchronous advantages: 1) low electromagnetic emissions and 2) the ability to restart from a complete halt (standby mode) to full operation with essentially no delay. The design also includes some novel architectural features which fit well with its asynchronous operation. Kessels and Marston’s article, “Designing Asynchronous Standby Circuits for a Low-Power Pager,” describes a very different asynchronous circuit for low power: a small standby circuit for use in a pager IC. The authors identify that a significant fraction of overall power consumption in commercial pagers is due solely to this one small subcomponent. The authors, working at Philips Electronics, develop an asynchronous standby circuit which consumes four times less power than a comparable commercial synchronous circuit. In the context of the entire pager, the result is a 37% reduction in overall power, with essentially no additional area. Interestingly, this article illustrates how an asynchronous subcomponent can successfully be incorporated into a larger synchronous design. It also indicates how 100% testability can be obtained for a particular class of asynchronous circuits. Nielsen and Sparsø’s article, “Designing Asynchronous Circuits for Low Power: An IFIR Filter Bank for a Digital Hearing Aid,” describes a novel asynchronous application: an asynchronous filter bank for a digital hearing aid. Their approach is to develop asynchronous architectures and circuits which can exploit the particular characteristics of the operating environment. For example, since typical data samples involve small numbers, they developed adders which are highly optimized for small numbers. Working in cooperation with a commercial manufacturer (Oticon, Inc.), they design and fabricate a chip that has five times less power consumption than a comparable commercial synchronous design. The next article, “DDMP’s: Self-Timed Super-Pipelined Data-Driven Multimedia Processors” by Terada et al., describes an impressive asynchronous data-driven multimedia processor developed in Japan, in stages, since the mid 1980’s. This work, conducted jointly between Osaka University, Kochi University of Technology, and Sharp Corporation, demonstrates how a data-driven architecture can be coupled naturally with an asynchronous design style to realize a single chip multimedia processor which can execute tens of billions of operations per second, with power consumption as low as 2W. In terms of operations per watt, the design shows a 3–10 improvement over conventional sequential digital signal processors. Molnar et al. have contributed another impressive example of high-performance asynchronous design, in their 220

article “Two FIFO Ring Performance Experiments.” Their goal is to demonstrate that asynchronous first-in firstout (FIFO), or pipeline control, circuits can be designed which are just as fast as comparable synchronous circuits. Two alternative FIFO designs are introduced which were developed at Sun Laboratories. Measured throughputs in fabricated chips of 1.1 Giga data items/s and 1.7 Giga data items/s, respectively, are obtained. Interestingly, unlike synchronous designs, these FIFO’s also have the benefit of elasticity (see “Scanning the Technology”), and a natural ability to interface with heterogeneous interfaces. The authors have also run a variety of experiments on the chips to measure operation over a wide range of voltages, temperatures, and pipeline configurations (i.e., degrees of congestion). Ebergen and Berks’ article, “Response-Time Properties of Linear Asynchronous Pipelines,” tackles a different problem: analytical techniques to estimate the response time of an asynchronous pipeline. This work addresses a key challenge: since asynchronous pipelines operate in a decoupled manner, with varying rates depending on the environment and the operating speeds of the individual stages, how does one formally characterize the overall performance? The article presents elegant closed-form solutions to this problem, in terms of two subproblems: 1) worst-case response time and 2) average-case response time. These solutions incorporate a model where each stage may have a varying delay. Jacobson and Gopalakrishnan’s article “ApplicationSpecific Programmable Control for High-Performance Asynchronous Circuits” is not primarily a paper on chip design nor on analytical techniques. Rather, it introduces a new general architecture for asynchronous programmable control. Programmable control offers a number of advantages, such as fast design time, easy correction of late design errors, and ease in upgrading of product families. Their architecture includes enhancements such as static branch prediction and overlapped instruction fetching. It also includes several novel features which would be difficult to incorporate into a comparable synchronous structure. The architecture has been applied to the design a CD-player error corrector that is estimated three times faster than a comparable asynchronous design built using a design compiler. Chakraborty et al.’s article, “Min–Max Timing Analysis and an Application to Asynchronous Circuits,” is the first CAD-oriented paper in the issue. This work addresses a critical problem: efficient and accurate timing analysis for asynchronous systems. While some asynchronous methodologies produce circuits that are guaranteed correct regardless of timing assumptions, many do not. In particular, most modern asynchronous methodologies targeted to high performance rely on local timing assumptions, which cannot be easily verified using synchronous tools. This article makes two contributions. First, it introduces an efficient polynomial-time min–max timing simulation algorithm for timing analysis of asynchronous circuits with bounded delays. Second, as a case study, it applies the PROCEEDINGS OF THE IEEE, VOL. 87, NO. 2, FEBRUARY 1999

timing analyzer to a particular class of control circuits, called 3D, and reports results on a number of timing constraints (setup and hold times, feedback delay, and environmental response time). Although the method uses a conservative approximation, experiments indicate that it is fairly accurate and also very efficient. The next article, “Logic Decomposition of SpeedIndependent Circuits” by Kondratyev et al., is the sole CAD synthesis paper in this issue. The focus of this work is on a challenging problem: hazard-free logic decomposition. This work is focused on a robust class of control circuits, called speed-independent: circuits which are guaranteed to operate correctly, regardless of gate delays (and with minor assumptions on wire delays). While logic decomposition is a well-studied problem in synchronous logic synthesis, it poses particular difficulties in asynchronous design. The decomposition of a gate into smaller gates must preserve not only the functional correctness of a circuit, but also speed independence, i.e., hazard freedom under unbounded gate delays. This article presents a general solution to this problem and reports results on a number of benchmark circuits. Finally, last (and certainly not least) is the article by Roncken entitled “Defect-Oriented Testability for Asynchronous IC’s.” Testability is a major challenge for asynchronous design: without viable techniques for testability,

there is little opportunity to consider the migration of asynchronous design to commercial products. Thus, it is a critical underpinning to all of the design methods and examples presented earlier in the issue. While there have been a number of recent papers on asynchronous testability, testing. this article addresses one of the final hurdles: In this article, Roncken quantifies the impact of self-based test methods timing on the effectiveness of for bridging faults. She then proposes a low-cost Designfor-Test solution. The author (whose work was carried out at Philips Research Laboratories, and who is now at Intel Corporation) illustrates the approach on three asynchronous IC’s: an error corrector, an 80C51 microcontroller, and an ADPCM speech codec. STEVEN M. NOWICK, Guest Editor Columbia University New York, NY 10027 USA MARK B. JOSEPHS, Guest Editor South Bank University London SE1 0AA U.K. C. H. (KEES) VAN BERKEL, Guest Editor Philips Research Laboratories Eindhoven 5600 MB The Netherlands

Steven M. Nowick received the Ph.D. degree in computer science from Stanford University, Stanford, CA, in 1993 and the B.A. degree from Yale University, New Haven, CT. His dissertation introduced an automated synthesis method for locally clocked asynchronous state machines, and he formalized the asynchronous specification style called “burst mode.” He is an Associate Professor of Computer Science at Columbia University, New York, NY. His research interests include asynchronous circuits, computer-aided digital design, low-power and high-performance digital systems, logic synthesis, and formal verification of finite-state concurrent systems. Dr. Nowick received an NSF Faculty Early Career (CAREER) Award (1995), an Alfred P. Sloan Research Fellowship (1995), and an NSF Research Initiation Award (RIA) (1993). He received a Best Paper Award at the 1991 IEEE International Conference on Computer Design, and he was a Best Paper Finalist at the 1993 Hawaii International Conference on System Sciences and at the 1998 IEEE Async Symposium. He was Co-Founder and Program Committee Co-Chair of the First IEEE Async Symposium (1994), and he is Program Committee Co-Chair of the upcoming Fifth IEEE Async Symposium (1999). He is a member of several international program committees, including ICCAD, ICCD, IWLS, Async, and ARVLSI. PROCEEDINGS OF THE IEEE, VOL. 87, NO. 2, FEBRUARY 1999

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Mark B. Josephs received the B.Sc. (Hons.) degree in mathematics from University College, London, in 1983 and the M.Sc. and D.Phil. degrees in computation from the University of Oxford, U.K., in 1984 and 1986, respectively. He is currently Professor of Computing and Director of the Centre for Concurrent Systems and Very Large Scale Integration (CCSV), South Bank University, London, U.K. He held a research position at the Computing Laboratory, University of Oxford, and he was Lecturer in Computation at Trinity College, Oxford, before moving to London in 1993. In 1987, he was a Visiting Scientist at IBM, Yorktown Heights, NY, and in 1990, he was a Visiting Fellow at Eindhoven University of Technology, Eindhoven, The Netherlands. His research interests include mathematical models of computation, formal methods for specification and design, and CMOS circuit techniques. Prof. Josephs is Project Manager of the European (ESPRIT) Working Group on Asynchronous Circuit Design (ACiD-WG). He has chaired or served on the program committees of four international symposia, two working conferences, and eight workshops, all on asynchronous circuit design.

C. H. (Kees) van Berkel (Member, IEEE) received the M.Sc. (summa cum laude) degree in electrical engineering from Delft University of Technology, Delft, The Netherlands, in 1980 and a Ph.D. degree from Eindhoven University of Technology, Eindhoven, The Netherlands, in 1992. He is a Senior Scientist at the IC Design Center of Philips Research Laboratories, Eindhoven, The Netherlands, and a Visiting Professor in Computer Science at the Eindhoven University of Technology. His research interests include VLSI programming, VLSI architectures, mobile communication, compilers, asynchronous circuits, CMOS circuits, and low power. He has authored and coauthored 24 publications and holds five patents on the subject of asynchronous circuits and was involved in the design of a dozen asynchronous IC’s. He is also author of the book Handshake Circuits—An Asynchronous Architecture for VLSI Programming. Dr. van Berkel managed the ESPRIT project EXACT (EXploitation of Asynchronous Circuits Technologies) and co-chaired the Program Committee of Async’97.

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