will find the insights on technology coming from looking at the .... Stephen Kosonocky (M'90) received the B.S., M.S., and Ph.D. degrees from Rutgers University,.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 1, JANUARY 2008
Special Issue on Device Technologies and Circuit Techniques for Power Management
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HIS SPECIAL Issue is devoted to research and development (R&D) activities directed toward managing power and temperature on highly scaled and highly integrated CMOS IC chips and the impact on devices and process integration. At 90 nm and beyond, both the active- and leakage-power density of high-performance CMOS chips is reaching the air-cooling limit. Moreover, OFF-state leakage power, which increases exponentially with channel-length and threshold-voltage reduction, has now become approximately equal to active switching power, and gate leakage, which is present in both the ON- and OFF-state, is now so large that scaling conventional gate oxide has essentially stopped. These combined effects are limiting our ability to reap the historical benefits of continued scaling, as we are forced to tradeoff performance for reduced power consumption. Already, this has resulted in a reduced rate of frequency increase from generation to generation, and eventually, it could force us to reduce the rate of density increase or to further tradeoff frequency to limit the power density. Already, high-performance chips use variable-voltage islands, dynamic frequency scaling, and control circuits to turn off unused portions of the chip—these chips effectively have reached the point where they cannot simultaneously utilize all of their transistors at once. Moreover, all of these power constraints are magnified by orders of magnitude when designing chips for mobile applications as power consumption directly affects the mobile unit’s usability. Because the power issues in modern FETs are due to reaching fundamental physical limits at these dimensions, there is unlikely to be any single breakthrough at the device level, which will stem the exponential power increases associated with continued scaling. Hence, there is increased need for power and thermal management at the circuit- and chip-architecture level to mitigate the effects of the power increase. A very close interaction between device and circuit design engineers will be needed so that the FETs are designed with the optimal characteristics to enable effective power management at the circuit level. The objective of this Special Issue is to bring together a diversity of R&D activities and discoveries in both devices and circuits and to inspire more novel concepts and innovative thinking in the growing field of power and thermal management. Bringing together such a large variety of R&D activities and results that touch on both the device and circuit aspects of the problem is a somewhat different approach for a TED Special Issue, and the Guest Editor team hopes it will inspire even more interaction between these disciplines in going forward.
Digital Object Identifier 10.1109/TED.2007.912611
Moreover, in particular, we hope that the device and process engineers who make up the majority of the TED readership will find the insights on technology coming from looking at the combined device and circuit interaction valuable in their future research work. To that end, this Special Issue consists of 20 carefully selected papers, including 12 invited papers and 8 contributed papers on a fairly wide variety of topics, all dealing with managing power and variability in ultrascaled CMOS technologies. This Special Issue starts off with five papers looking specifically at how device structures can be optimized for improved power-performance applications. These include three papers on devices utilizing metal-electrode/high-k insulators (Lee et al.), enhanced channel materials (Takagi et al.), and advance silicon-on-insulator (SOI) for adaptive threshold voltages (Ohtou et al.), respectively, followed by two contributed papers on suspended-gate FETs (Akarvardar et al.) and independentgate FinFETs (Tawfik and Kursun) for low-power logic applications. The next three papers cover device and circuit cooptimization approaches for managing the power problem. The first of these is an invited paper looking at codesign for elements from devices through circuits for a broad array of applications in the power-limited scaling regime (Nikolic), followed by two more invited papers on low-power applications: one focused on transistor-circuit cooptimization (Diaz et al.) and one focused on innovative materials, devices, and circuits for mobile multimedia applications (Skotnicki et al.). The next three papers look at the effects of shrinking devices to the nanoscale, starting with two invited papers—one on the impact of variation on performance and leakage on CMOS in general (Saxena et al.) and the second on the even larger impact on low-power SRAMs (Zhang et al.)—followed by a contributed paper on device-design and optimization methodology for reducing these leakage and variability impacts (Mukhopadhyay et al.). The next two papers look at these impacts in the extreme case of subthreshold applications, including an invited paper on managing device variation for minimum-energy subthreshold circuits (Verma et al.) and a contributed paper on nanoscale devices for subthreshold logic and SRAM (Hanson et al.). The next series of papers starts with an invited paper, giving a broad perspective from the EDA tools’ point of view on managing power (Kawa). This is followed by three contributed papers looking at specific technology issues that come up in powermanagement designs, including reducing noise in power-gating structures (Kim et al.), dealing with leakage in low-voltage transient suppressors (Dai et al.), and developing appropriate power FET devices (Chen et al.).
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 1, JANUARY 2008
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Finally, the last three papers focus appropriately on a key issue arising from the increased power density: thermal management. The first is an invited paper on electron–phonon transport in nanoscale FETs (Rowlette and Goodson), followed by an invited paper on self-heating in SOI FETs specifically (Fiegna et al.), and concluding with a contributed paper on the opportunities for cooling CMOS chips (Lin et al.). The Guest Editor team would like to extend their sincere thanks to the authors for their work in submitting and revising their manuscripts. We also wish to express our deepest gratitude to our reviewers for their efforts and dedication. This issue would not have been possible without their expert advice across the broad spectrum of research areas that this issue comprises. Finally, the superb work from J. Marsh of the EDS Office was instrumental in completing this issue on schedule and with the highest possible quality.
STEPHEN KOSONOCKY, Guest Editor AMD Fort Collins, CO 80528 USA
JEFFREY J. WELSER, Guest Editor IBM Almaden Research Center San Jose, CA 95120 USA
TSU-JAE KING LIU, Guest Editor University of California at Berkeley Berkeley, CA 94720 USA TAKAYASU SAKURAI, Guest Editor University of Tokyo Tokyo 153-8505, Japan ROLAND THEWES, Guest Editor Qimonda AG D85579 Neubiberg, Germany BIN ZHAO, Guest Editor Freescale Semiconductor Irvine, CA 92618 USA
Jeffrey J. Welser (S’87–M’89) received the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 1995, where his work was focused on utilizing strained-Si and SiGe materials for FET devices. After graduating, he joined the IBM T.J. Watson Research Center, where he worked on a variety of novel devices, including nanocrystal and quantum-dot memories, vertical-FET DRAM, and Si-based optical detectors and, eventually, took over managing the Novel Silicon Device Group. He was also an Adjunct Professor with Columbia University, New York, NY, where he taught semiconductor device physics. He joined the Technology Group Headquarters in 2000 and then joined the Microelectronics Division in 2001 as a Project Manager for the HighPerformance CMOS Device Design Groups. He was the Director of High-Performance SOI and BEOL Technology Development in May 2003, in addition to his continuing work as the IBM Management Committee Member of the Sony, Toshiba, and AMD development alliances. He returned to the Research Division in late 2003 as the Director of Next Generation Technology Components. He worked on the Next Generation Computing Project, looking at technology, hardware, and software components for systems in the 2008-2012 timeframe. Since 2006, he has been on an assignment with the IBM Corporation to serve as the Director of the Nanoelectronics Research Initiative (NRI) and is currently based at the IBM Almaden Research Center, San Jose, CA. The NRI is a subsidiary of the Semiconductor Research Corporation (SRC) and supports university-based research on future nanoscale logic devices to replace the CMOS transistor in the 2020 timeframe.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 1, JANUARY 2008
Stephen Kosonocky (M’90) received the B.S., M.S., and Ph.D. degrees from Rutgers University, New Brunswick, NJ, in 1986, 1991, and 1994, respectively. From 1986 to 1992, he was a Research Scientist with Siemens Corporate Research, Princeton, NJ, where he worked on CMOS digital- and analog-circuit design. From 1992 to 1993, he was with Samsung Princeton Design Center, where he worked on mixed-signal BiCMOS video circuits. In 1994, he was with IBM T.J. Watson Research Center, Yorktown Heights, NY, where he has developed prototype embedded DRAM systems-on-chip applications and contributed to the circuit, logic, and microarchitecture design of Daisy and BOA VLIW processors. In 2000, he began leading a team on low-power circuits and technology for digital-communication engines for handheld applications, and since 2003, he has been focusing on low-power-circuit techniques for high-speed microprocessors for server applications, SIMD processing extensions, low-power and robust SRAM, and exploratory memory. He is currently the Power Lead for the next-generation IBM Power7 microprocessor core. He has authored or coauthored over 43 publications and is a coinventor on 23 issued U.S. patents with 13 pending. Dr. Kosonocky has been on the Technical Program Committee for the 2001–2006 Symposium on VLSI Circuits, on the Technical Program Committee for the 2002–2004 IEEE International Solid-State Circuit Conference, and on the Technical Program Committee for the 2001–2005 International Symposium on Low Power Electronics and Design. He was the IEEE Solid-State Circuit Society Membership Chair from 1998 to 2000, a member of the IEEE Electron Devices Society Membership Committee from 1997 to 2005, and the Chair of a 1999 IEEE Technical Activities Board Focus Committee on retaining young members.
Tsu-Jae King Liu received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1984, 1986, and 1994, respectively. She joined the Xerox Palo Alto Research Center as a member of Research Staff in 1992, where she researched on and developed polycrystalline-silicon thin-film transistor technologies for high-performance flat-panel display and imaging applications. In August 1996, she joined the faculty of the University of California, Berkeley (UC Berkeley), where she is currently a Professor of electrical engineering and computer sciences and the Faculty Director of the Microfabrication Laboratory, UC Berkeley. Her research interests include nanoscale integratedcircuit devices and technology, and thin-film materials and devices for integrated microsystems and large-area electronics. Dr. Liu has been a member of the Process, Integration, Devices, and Structures Working Group, International Technology Roadmap for Semiconductors, since 2004. She was a member of the IEEE EDS VLSI Technology and Circuits Technical Committee from 2000 to 2001. From 1999 to 2004, she was an Editor of the IEEE ELECTRON DEVICE LETTERS. She has served on several committees for many technical conferences, including the IEEE International Electron Devices Meeting (IEDM) and the Symposium on VLSI Technology.
Takayasu Sakurai (S’77–M’78–SM’01–F’03) received the Ph.D. degree in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1981. In 1981, he was with Toshiba Corporation, where he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has worked extensively on interconnect-delay and capacitance modeling known as Sakurai model and alpha power-law MOS model. From 1988 to 1990, he was a Visiting Researcher with the University of California, Berkeley, where he conducted research in the field of very large scale integration (VLSI) computer-aided design (CAD). Since 1996, he has been a Professor with the University of Tokyo, working on lowpower high-speed VLSI, memory design, interconnects, and wireless systems. He has published more than 400 technical papers, including 70 invited papers and several books, and has filed more than 100 patents. He is also a consultant to U.S. startup companies. Prof. Sakurai served as a Conference Chair for IEEE/JSAP Symposium on VLSI Circuits and IEEE ICICDT, a Vice Chair for Association for Computing Machinery (ACM)/IEEE Asia and South Pacific Design Automation Conference, and a program committee member for IEEE International Solid-State Circuits Conference, IEEE Custom Integrated Circuits Conference, ACM/IEEE Design Automation Conference, ACM/IEEE International Conference on CAD, ACM Field-Programmable Gate Array workshop, ACM/IEEE International Symposium on Low-Power Electronics and Design, ACM/IEEE International Workshop on Timing Issues, and other international conferences. He was a plenary speaker for the 2003 International Solid-State Circuits Conference. He is an elected AdCom member for the IEEE SolidState Circuits Society and a Distinguished Lecturer of the IEEE Circuits and Systems Society.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 1, JANUARY 2008
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Roland Thewes (M’99) was born in Marl, Germany, in 1962. He received the Dipl.-Ing. and Dr.-Ing. degrees in electrical engineering from the University of Dortmund, Dortmund, Germany, in 1990 and 1995, respectively. In 1994, he was with the Research Laboratories of Siemens AG and Infineon Technologies, where he was active in the design of nonvolatile memories and in the field of reliability and yield of analog CMOS circuits. From 1997 to 1999, he managed projects in the fields of design for manufacturability, reliability, analog-device performance, and analog-circuit design. From 2000 to 2005, he was responsible for the Laboratory on Mixed-Signal Circuits of Corporate Research of Infineon Technologies, focusing on CMOS-based biosensors and advanced analog CMOS circuit design. Since 2006, he has been heading a department developing DRAM core circuitry with Qimonda. He has authored or coauthored more than 120 publications including book chapters, tutorials, and invited papers, and he has given lectures and courses at academic institutions. Dr. Thewes was a member of the technical program committees of the International Reliability Physics Symposium and of the European Symposium on Reliability of Electron Devices, Failure Physics, and Analysis. He is a member of the technical program committees of the International Solid-State Circuits Conference, of the International Electron Devices Meeting, and of the European Solid State Device Research Conference, and serves as a member of the IEEE EDS VLSI Technology and Circuits Committee. Bin Zhao (S’90–M’94–SM’99–F’08) received the B.S.E.E. degree from Tsinghua University, Beijing, China, in 1985 and the M.S. and Ph.D. degrees from California Institute of Technology, Pasadena, in 1988 and 1993, respectively. He was with SEMATECH, Austin, TX, the Rockwell International Corporation, Newport Beach, CA, Conexant Systems, Newport Beach, and Skyworks Solutions, Irvine, CA. He is currently a Senior Engineering Manager with Freescale Semiconductor, Irvine, where he is responsible for analog/mixed-signal and power management IC design and product development for consumer and industrial applications. He is the author or coauthor of more than 200 journal publications and conference proceedings and three book chapters. He is the holder of more than 40 issued U.S. patents. His research interests include VLSI technologies and analog/mixedsignal/RF circuit designs for wireless communications and consumer electronics. Dr. Zhao is the Chair of the IEEE/EDS VLSI Technology and Circuits Committee and the IEEE R. B. Johnson Technology Award Committee. Since 2003, he has been a Cochair of the Technical Working Group of RF and Analog/Mixed-Signal IC Technologies for Wireless Communications, International Technology Roadmap for Semiconductors. He is a Guest Editor of the IEEE/TMS JOURNAL OF ELECTRONIC MATERIALS and the IEEE TRANSACTIONS ON ELECTRON DEVICES and an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I and II. He has served on a variety of IEEE conference committees, including the IEEE International Electron Devices Meeting (IEDM), Symposium on VLSI Technology, Symposium on VLSI Circuits, the International Conference on Solid-State and IC Technology (ICSICT), and the International Conference on ASIC (ASICON). He was the Chairman of the 2000 TMS Symposium on Advances in Interconnect and Packaging Materials, the Chair of the Subcommittee of Integrated Circuits and Manufacturing in IEDM 2001, a Cochair of Organizing Committee in the Sixth International Conference on Solid-State and Integrated-Circuit Technology (ICSICT 2001), ICSICT 2004, and ICSICT 2006, and a Cochair of Technical Program Committee in the Seventh International Conference on ASIC (ASICON 2007).
