same design are being diagnosed (as in an integrated circuit manufacturing process). However, a common problem associated with these techniques is that it is ...
STATIC, DYNAMIC AND INTEGRATED SOLUTIONS FOR FAULT DIAGNOSIS Vamsi Boppana, Ismed Hartanto, Srikanth Venkataraman Coordinated Science Laboratory University of Illinois Urbana, IL 61801
W. Kent Fuchs School of Electrical and Computer Eng. Purdue University West Lafayette, IN 47907-1285
Abstract Fault diagnosis techniques for digital integrated circuits have been classified into three categories: static (using pre-computed information), dynamic (using simulation at run-time) and integrated (using a combination of pre-computed information and simulation). This paper presents our research in all three areas. We first present our tree-based theoretical framework, which improves static fault diagnosis by providing significant reductions in fault dictionary storage. Dynamic diagnosis is improved by reducing run-time simulation with the help of critical path tracing. Finally, we present integrated solutions to diagnosis based on the selective storage of state information.
1 Introduction Fault diagnosis refers to the process of locating failures in faulty integrated circuits. This paper describes contributions to the three groups into which fault diagnosis techniques are classified [1]. The first group of techniques, called static fault diagnosis, uses pre-computed information in the form of fault dictionaries for locating failures based on faulty responses produced by defective circuits. In contrast, dynamic techniques diagnose the faulty behavior of the circuit while the test set is applied. Integrated diagnosis methods store small amounts of pre-computed information and couple this with efficient dynamic algorithms to perform fault location. The main advantage of static fault diagnosis techniques occurs when multiple copies of the same design are being diagnosed (as in an integrated circuit manufacturing process). However, a common problem associated with these techniques is that it is typically infeasible to store all the pre-computed information (typical full fault dictionaries can require several gigabytes of storage for even moderately large circuits (20,000 gates)). Hence, research in this direction has concentrated on developing compact fault dictionaries. The main motivation for dynamic diagnosis algorithms is that they do not require any pre-computed information storage. However, this results in large runtimes for diagnosing each single faulty unit, thus leading to research on reducing the runtimes for dynamic diagnosis. Integrated techniques have been developed to incorporate the advantages of both the static and dynamic techniques. The main advantage of these techniques is the flexibility provided in choosing the amount of pre-computed information. This, in turn, has an effect on the time required for performing diagnosis at run-time. This research was supported in part by the Semiconductor Research Corporation (SRC) under grant 95-DP-109 and by an equipment grant from Hewlett-Packard.
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2 Static Fault Diagnosis Fault dictionaries store output information, produced by the circuit under consideration, on application of the given set of test vectors and under the influence of the set of modeled faults. Since fault dictionaries are typically prohibitively large to store, fault dictionary compaction has been an important focus of research. Past work addressing the size problem has yielded solutions in two distinct directions. The first set of contributions provide fault dictionary compaction targeting high modeled fault resolution, while the second set offers alternative representations for storing the full fault dictionary. We have provided solutions in both of the above directions by formulating the problems in terms of efficient storage of diagnostic experiment trees [2, 3]. A summary of our research is described in this section.
2.1 Tree-Based Fault Dictionary Compaction and Representation We have shown that diagnostic experiment trees are powerful tools for modeling the information corresponding to a diagnostic experiment. Diagnostic experiment trees are labeled trees; hence, the dictionary storage problem can be reduced to a labeled tree encoding problem. The two labeled trees that we use to represent the diagnostic experiment are introduced as special instances of a general diagnostic experiment tree. Definition 1 (General Diagnostic Experiment Tree T (V; E )) A general diagnostic experiment tree consists of a set of vertices V (T ) and a set of directed edges E (T ), i.e., each edge e is of the form (u; v ); u; v 2 V (T ) with the direction of the edge being from u to v . Each vertex v 2 V (T ) of the tree is associated with a set of faults F (v ) that is a subset of the list of all modeled faults F , and each edge e 2 E (T ) is associated with a list of outputs O (e) that is a subset of all the primary outputs of the circuit. Definition 2 (Vector-based Diagnostic Experiment Tree TV (V; E )) A diagnostic experiment tree in which each level represents the application of a test vector, and each edge e 2 E (TV ) is associated with a list of outputs O (e) that is the set of all the primary outputs of the circuit, is called a vector-based diagnostic experiment tree. Definition 3 (Output-based Diagnostic Experiment Tree TO (V; E )) A diagnostic experiment tree in which each level represents a (test vector,output) pair rather than a test vector, and each edge e 2 E (TO ) is associated with a single primary output of the circuit, is called an output-based diagnostic experiment tree. Example : Figures 1 (b) and 1 (c) show the vector-based and output-based diagnostic experiment trees corresponding to the full fault dictionary shown in the matrix format in Figure 1 (a). The information embedded in the vector-based diagnostic experiment tree is fully exploited to identify output sequences that may be eliminated to produce highly compact dictionaries even while they retain high diagnostic resolution with respect to modeled faults. The compact storage structures developed for storing the information identified to be useful provide compaction of up to 2 orders of magnitude [2]. For full fault dictionary representation, it is shown that both of the labeled trees can be efficiently represented by disjointly storing the label information and the underlying unlabeled tree. The vector-based tree is encoded by the use of a compact binary code, while the regular structure of the output-based tree is exploited to provide a spectrum of eight alternative representations for the full fault dictionary. This is possible
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because there exist three orthogonal (not influencing each other) components determining the label information, namely the fault, vector and output information. It is worth noting that the currently known list and the matrix formats arise as special cases in our framework. The results produced by our schemes result in the best currently known storage requirements for full fault dictionary representation [3]. Faults
012345
Output 0
01234
Faults
faults 0 1 2 3 4 5
v1 00 00 01 00 01 10
(a)
v2 11 11 01 10 00 11
1
5 1
0
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0
012345
013
Outputs 00
01
0
013 11
01
24
10
01
3
2
5
24
10
5
00
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11
4
1
5
1
5
5
0
1
3 01
0
2
1
0
4
-
1
1
0
1
-
5
-
-
24
013
0
1
0
0
0
1
-
-
0
5
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1
0
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1
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0
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1
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(b) (c) Figure 1: (a) Matrix Dictionary, (b) Vector-based tree, (c) Output-based tree
3 Dynamic Diagnosis Dynamic diagnosis techniques analyze the output responses produced by the failed chip at diagnosis time with the help of diagnostic fault simulation to derive a set of failures that best explain the set of observed responses. The approach does not require the storage of any pre-computed information. Previous work on dynamic diagnosis, which has included the use of artificial intelligence, expert systems and symbolic information to deduce information about faults, is typically not feasible to apply to large integrated circuits. Efficient fault location algorithms for large combinational circuits are known. These techniques are either based on effect-cause analysis, which analyzes the faulty responses (effects) to obtain the location of the fault (cause), or on cause-effect analysis, which starts with possible sources of causes (faults) and then determines their corresponding effects (responses). The commonly used diagnosis strategies perform modeled fault simulation to obtain a set of candidate faults that is consistent with the observed responses. Since modeled fault simulation of large sequential circuits is computationally intensive, the runtimes required for dynamic diagnosis are unsatisfactory. We provide a solution to the problem by the use of critical path tracing to rapidly reduce the list of candidate faults [4]. Our approach combines the use of cause-effect and effect-cause analyses. Cause-effect analysis is performed by single stuck-at fault simulation followed by a matching algorithm. Effect-cause analysis is performed by an error propagation backtrace starting from the failing outputs. This combination of cause-effect and effect-cause strategies enables us to handle phenomena typical to sequential circuits, such as sequential reconvergence. The error propagation backtrace eliminates from consideration faults that could not have caused the failing symptoms, thus reducing the candidate fault list. This procedure is exact for defects behaving as single stuck-at faults. Experiments on benchmark circuits have shown the improvements in runtimes achievable with our diagnosis strategy [4].
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4 Integrated Fault Diagnosis The prohibitive size of fault dictionaries and the large runtimes required for dynamic diagnosis have led to the development of integrated fault diagnosis techniques, where the focus is on storing a limited amount of essential information and utilizing this information effectively along with analysis/simulation at run-time. Two of our contributions to integrated fault diagnosis are described below [5, 6]. State information-based diagnosis solves a crucial problem inherent to conventional diagnostic techniques [5]. Conventional techniques store only primary output-based information, offering only a black-box view of the circuit and thus little diagnostic flexibility. Our technique provides a solution by storing information corresponding to the internal nodes in the circuit, namely the state nodes. The selective storage of state information has been shown to significantly improve the time for diagnostic fault simulation. A method for reducing the amount of storage by storing only a subset of the state space has also been provided. Further, we have shown that the technique is ideally suited to sequential circuits with partial scan. The structural simplicity of partial scan circuits is exploited to perform rapid diagnosis. Experimental results on large circuits were presented to demonstrate the improvements in performance. The previous work provides an opportunity for reducing the amount of simulation time during diagnosis, but it does not explicitly target reduced simulation. We have developed an integrated diagnosis technique to overcome this limitation by specifically creating the pre-computed information to provide savings in the simulation costs at diagnosis time [6]. This is achieved by first formulating the diagnosis problem in terms of a set of computations, only a small number of which are identified to be essential for diagnosis. Our integrated diagnosis algorithm exploits the identification of unnecessary computations by storing this information in a pre-computed storage structure and using it at diagnosis time to avoid a large number of unnecessary computations. For example, in Figure 1 (b), if the class structure for level 1 is stored, then the simulation of only one of faults 0, 1 and 3 suffices to produce the output responses of all three faults. Experimental results on the ISCAS 85 and ISCAS 89 circuits have demonstrated the substantial savings achieved by this technique.
References [1] W. K. Fuchs, V. Boppana and I. Hartanto, “Fault diagnosis solutions: Storage, reuse and parallelism,” To Appear in Proceedings of International Workshop on Computer-Aided Design, Test, and Evaluation for Dependability , 1996. (SRC Publication: C96212) [2] V. Boppana and W. K. Fuchs, “Fault dictionary compaction by output sequence removal,” in Proceedings of International Conference on Computer-Aided Design, November 1994, pp. 576–579. (SRC Publication: C95017) [3] V. Boppana, I. Hartanto, and W. K. Fuchs, “Full fault dictionary storage based on labeled tree encoding,” in Proceedings of VLSI Test Symposium, April 1996, pp. 174–179. (SRC Publication: C96211) [4] S. Venkataraman, I. Hartanto, and W. K. Fuchs, “Dynamic diagnosis of sequential circuits,” in Proceedings of VLSI Test Symposium, April 1996, pp. 198–203. (SRC Publication: C95393) [5] V. Boppana, I. Hartanto, and W. K. Fuchs, “Fault diagnosis using state information,” To Appear in Proceedings of Fault Tolerant Computing Symposium, 1996. (SRC Publication: C96213) [6] V. Boppana and W. K. Fuchs, “Integrated fault diagnosis targeting reduced simulation,” To Appear in Proceedings of International Conference on Computer-Aided Design, 1996. (SRC Publication: C96226)
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