subthreshold synchronization

Extending Synchronization from Super-threshold to Sub-threshold Region Jun Zhou, Maryam Ashouei, David Kinniment*, Jos Huisken and Gordon Russell* IMEC Netherlands & *Newcastle University

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Sub-threshold Operation Synchronization in Multi-Low-VDD Systems on Chip Low Voltage Synchronizer Design Sub-threshold Synchronizer Design Results Implementation Conclusion

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Sub-threshold Operation Synchronization in Multi-Low-VDD Systems on Chip Low Voltage Synchronizer Design Sub-threshold Synchronizer Design Results Implementation Conclusion


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Sub-threshold Operation Minimum energy point VDD Low Performance Requirement

Energy per Cycle

Dynamic Leakage Total

0

VT

VDD

Minimum Energy VDD

Freq

• •

0

VT

VDD

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Sub-threshold Operation Synchronization in Multi-Low-VDD Systems on Chip Low Voltage Synchronizer Design Sub-threshold Synchronizer Design Results Implementation Conclusion


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Multi-Low-VDD Systems on Chip Synchronizers

VDD/Clock Domain A

S

Network on Chip

Norm VDD

S

VDD/Clock Domain B

S

Low VDD

VDD/Clock Domain C Sub-threshold VDD

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Sub-threshold Operation Synchronization in Multi-Low-VDD Systems on Chip Low Voltage Synchronizer Design Sub-threshold Synchronizer Design Results Implementation Conclusion


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Synchronizer Performance (MTBF) t s −Td

e τ MTBF = Tw f c f d

ts: Synchronization Time Td : Normal Propagation Delay τ : Metastability Time Constant Tw : Metastability Window fc : Clock Frequency fd : Incoming Data Frequency

In the Super-threshold Region: Td ∝ VDD, VDD ↓→ Td ↑→ MTBF ↓↓ C and g m ∝ I d ∝ VDD 2 , VDD ↓→ τ ↑→ MTBF ↓↓
τ ∝ gm


In the Sub-threshold Region: VDD
Td ∝ VDD , VDD ↓→ Td ↑↑→ MTBF ↓↓↓ e C and g m ∝ I d ∝ eVDD , VDD ↓→ τ ↑↑→ MTBF ↓↓↓
τ ∝ gm


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Jamb Latch

1.00E-06 4.0E-07 1.2E-07 1.00E-07

3.4E-08 9.5E-09

T au (s)

1.00E-08 2.8E-09 9.0E-10 1.00E-09 3.2E-10

τ

1.3E-10 6.0E-11

1.00E-10

3.2E-11

1.00E-11 0.2

0.4

0.6

0.8 VDD (v)

Schematic

τ

vs VDD

1

1.2


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Improved Latch 1.00E-06 4.0E-07 1.2E-07 1.00E-07

Jamb Latch

3.4E-08 9.5E-09

Tau (s)

1.00E-08 2.8E-09 9.0E-10 1.00E-09 3.2E-10 1.3E-10 6.0E-11

1.00E-10

3.2E-11

1.00E-11 0.2

0.4

0.6

0.8

1

1.2

VDD (v) 1.00E-06

1.00E-07

9.2E-08

Tau (s)

1.00E-08

8.4E-09

1.00E-09

Improved Latch 9.8E-10 1.9E-10

1.00E-10

6.6E-11 3.4E-11

Schematic 1.00E-11

2.1E-11 1.5E-11

1.2E-11 9.6E-12

1.00E-12 0.2

0.4

0.6

0.8

τ

VDD (v)

vs VDD

1

1.2

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Normal Propagation Delay Td


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Sub-threshold MTBF t s −Td

e τ MTBF = Tw f c f d At 0.3 V, Tw = 30 ～ 50 ns. Assuming that fc = fd = 300 KHz:

τ

Td

MTBF

Jamb Latch

400 ns

0.7 us

0.17 s

Improved latch

92 ns

1.5 us

2 days

Two factors are not taken into account in the calculation: 1.

System MTBF = Single MTBF / Num of Synchronizers

2.

Large Process Variation in the Sub-Threshold Region

Unacceptable !


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Process Variation t s −Td

e τ MTBF = Tw f c f d

80

Number of Occurance

70 60 Mean: 440 ns Std: 230 ns

50 40 30 20 10 0 0

150

300

450

600

750

900

1050

1200

Tau (ns)

Variation of Tau for Jamb Latch at 0.3 V

1350

1500

1650

1800

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Sub-threshold Operation Synchronization in Multi-Low-VDD Systems on Chip Low Voltage Synchronizer Design Sub-threshold Synchronizer Design Results Implementation Conclusion


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Increasing Transistor Size? 3.00E-11

2.80E-11

Tau (s)

2.60E-11

2.40E-11

2.20E-11

τ∝

2.00E-11

1.80E-11 0.00E+00

2.00E-06

4.00E-06

6.00E-06

8.00E-06

Transistor Size (m)

1.00E-05

1.20E-05

C↑ gm ↑


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Applying Forward Body Bias (FBB)

Advantages: 1.

Increase gm without increasing C. So tau is reduced.

2. Propagation delay is reduced like other logic circuits. 3. Process variation is improved. Super-threshold: g m = µ n ⋅ C ox Sub-threshold:

gm =

W ⋅ (V gs − VT ) L

Id , I d ∝ e −V T n ⋅ν th

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Sub-threshold Operation Synchronization in Multi-Low-VDD Systems on Chip Low Voltage Synchronizer Design Sub-threshold Synchronizer Design Results Implementation Conclusion


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Tau vs FBB

VDD=1.2

VDD=1.1

VDD=1.0

VDD=0.5

VDD=0.4

VDD=0.3

1.00E-06

VDD=0.9

VDD=0.8

VDD=0.7

VDD=0.6

VDD=1.1

VDD=1.0

VDD=0.5

VDD=0.4

VDD=0.3

VDD=0.9

VDD=0.8

VDD=0.7

VDD=0.6

1.00E-06

8 times reduction

3.96E-07

VDD=1.2

7 times reduction 9.16E-08

1.00E-07

1.00E-07 4.88E-08

1.30E-08

1.00E-08 Tau (s)

Decreasing VDD

Tau (s)

1.00E-08

1.00E-09

1.00E-09 1.00E-10

1.00E-10 1.00E-11

1.00E-11

1.00E-12

0

0.1

0.2

0.3

0.4

0.5

0.6

Body-Bias (v)

Jamb Latch with FBB

0.7

0.8

0

0.1

0.2

0.3

0.4

0.5

0.6

Body-Bias (v)

Improved Latch with FBB

0.7

0.8


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Propagation Delay vs FBB

VDD=1.1

VDD=1.0

VDD=0.9

VDD=0.6

VDD=0.5

VDD=0.4

VDD=0.3

VDD=0.8

VDD=0.7

5 times reduction

7.06E-07

VDD=1.1

VDD=1.0

VDD=0.9

VDD=0.6

VDD=0.5

VDD=0.4

VDD=0.3

VDD=0.8

VDD=0.7

4 times reduction 1.454E-06

1.43E-07

1.00E-07

VDD=1.2

1.00E-05

Norm al P ropagation Delay (s)

Norm al P ropagation Delay (s)

1.00E-06

VDD=1.2

1.00E-08

1.00E-09

1.00E-10

1.00E-11

1.00E-06 3.150E-07 1.00E-07

1.00E-08

1.00E-09

1.00E-10

0

0.1

0.2

0.3

0.4

0.5

Body-Bias (v)

Jamb Latch with FBB

0.6

0.7

0.8

0

0.1

0.2

0.3

0.4

0.5

0.6

Body-Bias (v)

Improved Latch with FBB

0.7

0.8


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Process Variation

90

80

80 70

60

N u m b er of O ccu ra nce

Number of Occurance

70

Mean: 440 440 ns Mean: ns Std:230 230ns ns Std:

50 40 30

50

Std: 10 times reduction

40 30

20

20

10

10

0

Mean: ns Mean: 5454ns Std:ns 25 ns Std: 25

60

0

0

150

300

450

600

750

900

1050

Tau (ns)

Without FBB at 0.3 V

1200

1350

1500

1650

1800

0

25

44

63

82

101

120

Tau (ns)

With FBB at 0.3 V

139

158

177

196


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Sub-threshold MTBF t s −Td

e τ MTBF = Tw f c f d At 0.3 V, Tw = 7 ～ 15 ns, assuming that fc = fd = 300 KHz:

τ

Td

MTBF

Jamb Latch

400 ns

0.7 us

0.17 s

Improved latch

92 ns

1.5 us

2 days

Jamb Latch with 0.3V FBB

49 ns

0.14 us

1.35x1017 years

Improved Latch with 0.3V FBB

13 ns

0.32 us

4.88x1089 years

3σ

4.7 months

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Sub-threshold Operation Synchronization in Multi-Low-VDD Systems on Chip Low Voltage Synchronizer Design Sub-threshold Synchronizer Design Results Implementation Conclusion


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Full-VDD Biased Synchronizer

Advantage: 1.

Full-VDD bias gives large performance improvement.

2.

No on-chip voltage generation circuit needed (Min Power and Area Overhead).

3.

The Bias can be disabled when VDD is higher than the PN junction conducting voltage (0.7 V) to avoid performance degradation.

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Sub-threshold Operation Synchronization in Multi-Low-VDD Systems on Chip Low Voltage Synchronizer Design Sub-threshold Synchronizer Design Results Implementation Conclusion

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Conclusions 1. For the first time, synchronizer performance is investigated in the near-threshold and sub-threshold region. 2. The investigated synchronizers shows unacceptable MTBF especially when taking into account the process variation. 3. Applying Forward Body Bias significantly improves Td and Tau. It also greatly reduce the impact of process variation on synchronizer performance. As a result, MTBF is significantly improved. 4. A full-VDD biased synchronizer scheme is proposed to improve synchronizer performance in the near-threshold and sub-threshold region with minimal area and power overhead.


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