Switch-Level Test Generation of Competing

Switch-Level Test Generation of Competing Bridging Faults in the Presence of Feedback Technical Report 00-02 Kristian Wiklund, Tomas Magnusson and Peter Dahlgren Department of Computer Engineering, Chalmers University of Technology S-412 96 Gothenburg, Sweden

ABSTRACT This paper presents an efficient scheme to improve the test generation of voltage testing under the competing bridge fault model. A procedure is presented that extracts test generation objectives from switch-level networks, which will maximize the likelihood of detecting a bridging fault that is undetectable by a stuck-at test set. The effects of both active feedback and variations in transistor parameters are taken into account. The experimental results show that the proposed method generates a significant increase in fault coverage at a relatively low computational cost. 1 Introduction To improve the testability of deep sub-micron VLSI circuits, the need for incorporating more accurate defect models in traditional test generation schemes has become accentuated. Shorts between normally unconnected signal lines are known to be representative of a sizeable class of physical failures occurring in CMOS circuits [3][4]. Although, Iddq testing [7] has been successfully used for detecting shorts for a long time, the efficiency of Iddq testing in complex deep sub-micron circuits has recently become questionable. Consequently, a significant part of the testing must rely on other testing methods such as voltage testing and delay testing. In order to model the effects of shorts accurately, electrical-level effects, such as intermediate voltage levels and active feedback, must be considered. For instance, several studies have reported that a great proportion of realistic bridging faults causes feedback loops, [1][2][5][12]. Active feedback in combinational circuits may cause oscillatory behavior if the feedback loop consists of an odd number of inversions. Oscillation may cause the fault to be undetected and, consequently, to reduce the overall defect coverage. This paper presents a new method to generate robust test sets for competing bridging faults that maximizes the probability of detection. The inputs to the circuit is generated in a way such that the driving strength is maximized for one of the shorted drivers and minimized for the other, similar to the approach in [18]. A search algorithm is proposed that will find the necessary input assignments to any transistor network that will maximize or minimize the driving strength and thereby generating bridge voltages that will fall outside the region of logically unresolvable intermediate values. A procedure for generating objectives for undetected faults was added to the fault simulator described in [12]. This fault simulator takes into account the driving strength ratio between the shorted drivers and situations of active feedback. Furthermore, to allow for fluctuation in process parameters during manufacturing the simulator classifies each competing fault case as logically resolvable or unresolvable. Some efficient methods based on modeling the driving strength have recently been developed for handling conflicts that occur when the outputs of two gates are shorted and for predicting

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the logic state at subsequent gates [5]-[9][13]. Methods based on mixed-mode simulation [9], precomputed tables containing data derived from analogue simulations [5]-[6][11][13] or extended switch-level models [7][10] can successfully handle a subset of bridging fault cases. Unfortunately, none of these approaches is applicable to situations of global feedback involving several logic gates that may result in asynchronous behavior or circuit oscillation. 2 Overview of test generation scheme The proposed bridging test generation scheme consists of the following four steps: (1)

Starting with the transistor-level circuit description, a gate-level description is extracted and a stuck-at test set is generated.

(2)

Bridging fault simulation is conducted for the stuck-at test set.

(3)

Test generation objectives are generated for each fault that was undetected in (2)

(4)

The set of objectives associated with the undetected faults are applied to a modified stuck-at test pattern generator.

(5)

A second bridging fault simulation is conducted for the remaining fault set under the new test set generated in (4).

The main contribution of this work is the procedure for generating objectives that will expose the bridging faults and the modification of a basic test generation procedure to handle multiple objectives for fault activation as described in Section 5. Most previous approaches for test generation under the competing bridge fault model, such as [17][18], are aimed at designs based on standard cells or gate-level descriptions and require precomputed strength tables obtained from extensive analogue simulation of each gate type. Our approach requires only the switch-level network description and is applicable to any static CMOS circuit design. Furthermore, conditions on the inputs are generated that will maximize the probability of detecting the fault and avoiding active feedback. In [19], a general method was proposed to propagate fault values within a gate, which is applicable to local faults within gates. However, this approach is not suitable for handling situations of global feedback, which frequently arise when realistic layout based fault sets are considered. 3 Fault modeling and definition of fault cases If the two shorted drivers are driven to opposite logic values, there may be several reasons why a bridging fault is not detected: (i) The resultant intermediate value may fall within the region of logically unresolvable values as discussed in Section 3.1; or (ii) the fault may cause active feedback that may cause the circuit to oscillate (see Section 3.2). 3.1 Region of logic uncertainty To predict the fault behavior with a high degree of confidence, we must allow a range of fluctuations in threshold values rather than study the response at a specific point of the operational space. The reason for this is that normal variations in the process parameters during manufacturing cause the logic threshold voltage to vary significantly between various samples of manufactured chips. In [14][15], it was reported that the variation in transistor gain factor can be as high as 20%. Figure 1 shows the variation of the transfer characteristics of an inverter, obtained from Spice simulations, when the gain factor of the transistors is increased and decreased by 10% of its nominal value. Thus, even if it were possible to predict a voltage at the bridge that falls within the U region of Figure 1 with electrical-level accuracy, there is a great uncertainty whether we would predict the correct behavior of a sample out of a set of manufactured circuits.

2

Vout (V) 5.0 Inverter: nmos gain factor +10% pmos gain factor -10% 4.0 Inverter: nominal gain factors 3.0

2.0

Inverter: nmos gain factor - 10% pmos gain factor + 10%

1.0

0 0

3.0

2.0

U

Vin (V)

Y Figure 1 Change in transfer characteristics caused by variations in transistor gain factors.

In addition, Byzantine fault behavior means that an intermediate value within a certain interval may be interpreted as different logic values by different gates owing to the variation in threshold voltage between different gate types [2][5][6][12][13]. Furthermore, as we use an extended switch-level model, [10], with limited accuracy in comparison with electrical-level analysis, to locally estimate the driving strength ratio between the two shorted nodes, we must assign a wider region. The U region of Figure 1 is therefore expanded to the Y region. Fault cases resulting in voltages predicted outside the Y region are considered to be correctly logically interpreted regardless of parameter variations and Byzantine fault behavior. Electrical-level simulation for a sample of faults and input vectors can be used to tune the width of the Y region so that the results produced by the switch-level model will match those of electrical-level simulations at an acceptable degree of accuracy. Choosing a wide Y interval will result in a pessimistic detection capability, whereas a narrow interval may cause errors in the classification of a fault as detected. In the simulation results reported in Section 6, the Y interval was set to the interval [ 1.9, 3.1 ] V for V DD = 5 V . .

3.2 Conditions for global bridging faults to cause active feedback Global bridging faults are shorts between the outputs of different gates or between internal nodes that belong to different gates. These faults are most likely to cause active feedback, as they can create combinational paths between gates located at different topological levels through the bridge. Only bridges between the ouput of gates are considered in this paper. Consider a bridge between the outputs of two gates, G1 and G2, as shown in Figure 2. Gate G2 dominates over gate G1 if the driving strength of G2 in combination with the bridge resistance is strong enough to produce a voltage at node n1 that falls outside the Y region of Figure 1 and is interpreted as the opposite logic value of n1 in the fault-free case. The dominance condition may be satisfied dynamically for some input vectors and not satisfied for others. Feedback may arise if there is a combinational path between n1 and n2 in Figure 2. Depending on the input state, , the feedback may be dynamically sensitized or non-sensitized. Active feedback is said to occur if the gate located at the higher topological level, G2, dominates over the gate at the lower level, G1, given that the path between n1 and n2 is sensitized. Furthermore,

3

G1

>1

Bridge

n1 a

1 b

& &



Feedback (FB) type

Behavior

00

No FB

Intermediate voltage level

&

01

FB: odd no. of inversions

Oscillation possible if n >1

G2

10

FB: even no. of inversions

Asynchronous behavior

11

FB: Both even and odd no.

Cancellation

n2

Figure 2 Example of a bridging fault causing various types of feedback.

the number of inversions of the loop must be an odd number. A special case of feedback that usually results in a very strong nonlinear behavior is the case when the number of inversions is one. This situation corresponds to a short between one of the input nodes of a gate and its output node. Although the path is inverting, this situation does not result in oscillation [1] since the effective propagation delay is shorter than the rise and fall times for a single gate. In stead, the circuit will settle into a stable state with some nodes assigned intermediate values. On the other hand, if there is an even number of inversions in the feedback loop, an originally combinational or synchronous circuit is likely to become a circuit with asynchronous “memory” behavior. Such fault cases may under certain conditions be detectable by a two pattern test sequence. As any global bridging fault dynamically can cause active feedback with varying number of inversion depending on the input state, as illustrated in Figure 2, feedback analysis is necessary for each fault case during the fault simulation. The goal of the test generation is to expose the fault without causing active feedback. This can be achieved by either breaking the feedback (generate = 00 in the example of Figure 2) or forcing the gate at the lower level G1 to dominate over the gate at the upper level by assigning appropriate values on the inputs of gates G1 and G2. 4 Fault simulator The core of the test generation system is the mixed mode fault simulator [12] that evaluates the existence of dominance in driving strength and classifies each fault case as a logically resolvable or unresolvable fault case and detects any situation of active feedback. This fault simulator uses levelized logic simulation for propagation of stuck-at fault values and feedback checking, and an extended switch-level model, [10], to evaluate intermediate values.

5 Test generation scheme Figure 3 shows a bridge between the outputs of two simple gates and the corresponding bridge voltage obtained from Spice simulations for various assignments on the inputs ABCDE. The pMOS transistors were assigned a width 2.7 times greater than the nMOS transistors to compensate for the difference in mobility between holes and electrons. It can be seen that most bridge voltages fall within the Y region of Figure 1, i.e. they are interpreted as logically unresolvable. Cases 3, 4 and 7 would most likely detect the fault by stuck-at propagation through g. The driving strength ratio between the p and n networks is maximized by the input conditions: AB = LL and CDE = HHL, resulting in the voltage 4.4 V at the bridge. Next section presents a

4

general procedure for generating the conditions that will optimize the driving strength ratio.

VDD

A

f

B A

E

Bridge

B C

Gnd

D

g

C E D

(a)

Case

ABCDE

Bridge voltage (V)

1. 2. 3. 4. 5. 6. 7. 8.

HHLHL HHLLL HLHHL LLHHL HLLLH LLLLH HLHHH LLHHH

2.48 3.08 3.80 4.40 2.50 3.64 1.83 3.07

(b)

Figure 3 (a) Example of bridging fault in a CMOS circuit. (b) Bridge voltage for various input assignments.

5.1 Path distance in channel graphs To determine the assignments necessary to generate the weakest possible driving strength, we first introduce the concept of path distance. The path distance of a node is defined as the maximum number of transistors that can be included in an acyclic path from the node through the channel graph formed by the p or n network to the signal source (VDD or Gnd). The path distance can be determined by tracing the channel graph in direction from the source to the output node. For each element passed, the distance is increased by one, and the element is labeled the same value. The procedure for computing the path distance of each node in either the p or n network consists of the following three steps: (1)

Each element connected directly to a signal source is given path distance 1.

(2)

Nodes with only one unlabeled element connected to themselves are processed first. Any node satisfying this condition is assigned the maximum path distance D Pmax , of the elements connected to the node. Next, the unlabeled element is labeled D Pmax + 1 .

(3)

If no nodes satisfy the criterion in (2), the element so far labeled the highest distance, D Pmax , is selected, and the unprocessed node, N F , connected by this element is assigned D Pmax . Next, all unlabeled elements connected to N F are labeled D Pmax + 1 .

Steps (2) and (3) are repeated until the output node is reached. Step (3) has lower priority than (2), which means that (3) is only performed when there are no nodes that satisfy (2). In case of transistors of different sizes, the procedure is modified in a way such that the path distance is increased by the width/length ratio relative to the nominal size in stead of one. As an example, consider the n network of a CMOS circuit given in Figure 4, assuming all transistors are of equal size. Figure 4a shows the state after some of the operations have been performed. For example, there are two elements that merge at node N A , labeled distances 1 and 2, 5

Pull-up network

Pull-up network



NO a

a

NC

b c

b 1

M2

NB

d

3

b

M1

NA

h 3 M1

2 e

ND g

NB



d

1

k

1

1

M3

4

M2 h

e

b 4

c

M3

NA

NO

5

1 2

k 1

ND g

1

1

Gnd

Gnd

node = path distance

(b)

(a)

Figure 4 Example of determining the path distance in an n network.

respectively. The condition in (2) is satisfied, and N A is therefore assigned path distance , after which M1 is labeled 3 as shown in Figure 4a. Next, no nodes satisfy (2) so Step (3) selects N B as the target node. N B will be assigned distance and elements M2 and M3 will be labeled 4. Figure 4b shows the final result of this procedure.

5.2 Generation of objectives for fault activation Given the path distance of each node, the minimization of the driving strength at the output of a gate is obtained by forming a single series transistor path from the output to the source that includes the maximum number of transistors. This path is obtained by tracing the network in descending order of the path distance. At each instance, selecting an element labeled the same value as the current node distance guarantees that the longest path (with greatest resistance) will be found. The objectives for the test generator are then obtained by forcing all transistors included in this path to be conducting and all others to be off. In the example of Figure 4, the objectives generated would be: ; ; ; ; ; ; and . If the necessary conditions are not possible to satisfy owing to a logic conflict, a heuristic method was developed to relax some of the conditions and try other non-optimal paths. On the other hand, the maximization of the driving strength at the output of a CMOS network is performed by generating objectives that will force a sufficient number of transistors in either the p or n network to be conducting such that the driver will dominate over the driver whose driving strength was minimized. Next, there are four possible ways of activating the fault. We must determine the network for which the driving strength should be maximized, and to which fault value the bridge should be driven. Referring to Figure 2 as a general bridging fault, we use the following criteria for this

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selection: (1)

In case of active feedback, G1 (at the lower level) is maximized and G2 is minimized. Next, the one of the p and n networks of G2 that has the greatest path distance determines the logic value that will be activated by G1. If the path with the maximum path distance is through the p(n) network, the driving strength of the n(p) network of G1 is maximized.

(2)

In case of no active feedback, the gate that has the maximum path distance through any of the p and n network is selected and the driving strength through that network is minimized. The driving strength of the other gate is maximized to the opposite logic state.

5.3 Test generation procedure To generate test vectors that satisfy the objectives for fault activation, a multiple objective PODEM stuck-at fault test generator was developed. This is possible since many of the requirements for a stuck-at test pattern generator are also requirements for the bridging fault test generator. The problem of satisfying the set of line justifications required to activate the bridging fault can be transformed into a problem similar to the activation of a multiple stuck-at fault. The test generator assumes that the fault is equivalent to a stuck-at fault at the dominated node. The backtrace limit was set to twice the number of primary inputs by default. This limit has experimentally shown to be a good trade-off between test generation efficiency and resource usage.

6 Experimental results Although the proposed test generation method is applicable to resistive shorts, only hard shorts between gate outputs were considered in the experiments. Other test methods such as delay testing or low voltage testing are usually much more efficient than voltage testing in detecting shorts with a resistance greater than the on resistance of a transistor. Table 1 shows some characteristics of the circuits investigated together with fault coverage for node stuck-at faults. Test sets of high stuck-at coverage were generated with the ATPG included in SIS [16]. Static CMOS implementations of the ISCAS 85 circuits and bridging fault sets were obtained in two ways. In the first implementation, the net list based implementation, each logic operation from the net list was converted to a corresponding CMOS gate. No information concerning the physical layout of the circuits was available for this implementation, but only the switch-level representations. The fault set was extracted based on the idea that nodes that are located close to one another in the transistor schematics are more likely to be adjacent in the physical layout. This fault set was obtained by selecting all shorts between neighboring gates of a maximum distance of six, where the distance between two gates is defined as the minimum number of gates that can be included in any path between the two gates. The second implementation, the layout based implementation, consists of the MCNC standardcell implementations, which use both simple gates and complex gates such as AOIs and OAIs. The fault sets for this version were obtained from the fault extraction tool Carafe [20], which generates realistic fault sets on the basis of layout information. The results of the bridging fault simulations and test generations are shown in Table 2. The original fault coverage refers to the coverage obtained for the stuck-at test sets alone. All fault simulations were conducted both with active feedback taken into account and with feedback effects ignored, which is indicated in the table by “FB” and “no FB”, respectively. Ignoring the feedback effects simply means that the fault is handled as a non-feedback fault and considered detected if the intermediate value predicted at the bridge is logically resolvable and the fault 7

value is propagated to a primary output. It can be seen that there is a significant increase in fault coverage for both implementations when the vectors generated by the proposed method were added. The coverage increases with up to 5% for the net list based implementations and up to 1.5% for the MCNC implementations. The reason why some of the circuits, particularly the C432 for the net list based implementation, show a poor original coverage is that these circuits are made up of a lot of 2-input Nand gates. Bridges between the outputs of these gates are undetectable because the intermediate values will fall within the interval of logically unresolvable values (See Section 3.1) regardless of gate input assignments when all transistors are set to the minimum size, which was the case for all implementations investigated here. On the other hand, if the Y interval of Figure 1 is reduced, a significant increase in coverage numbers would be reported for most circuits, both as original coverage and improved coverage by the bridging test generator. However, due to the effects discussed in Section 3.1, such as variation in process parameters, the confidence in those number would be low. By comparing the columns denoted “no FB” and “FB”, it can be seen that active feedback significantly reduces the overall coverage for most circuits. The reason why the coverage for the net list based implementations are more sensitive to active feedback than the MCNC implementations is that the fault sets generated for these implementations include more bridges between nodes that are logically dependent on one another. Table 3 shows the number of bridging faults processed by the test generator, i.e. the number of undetected faults by the initial stuck-at test set, together with the number of test vectors generated. The execution times are shown for the test generation and fault simulation and are given in CPU seconds on a Sun Sparcstation 5 at 110 MHz. The times for the fault simulation include the times for generating fault activation objectives.

Table 1 General information about the circuits investigated and node stuck-at coverage. Circuit characteristics Name

# of PIs/ POs

Stuck-at faults

Transistor count

Gate count

# of test vectors

# of SA faults

Coverage (%)

C432

36/7

794

182

58

422

94.1

C880

60/26

1,802

555

86

1,178

100.0

C1908

33/25

3,444

1,105

148

2,226

99.9

C3540

50/22

7,498

2,482

253

5,020

97.8

C6288

32/32

10,112

2,672

32

5,344

99.7

8

Table 2 Bridging fault coverage. Net list based implementation and fault sets Circuit

Layout-based (MCNC) implementations and fault sets

Coverage (%) Original # of proposed method coverage faults (%) FB no FB

# of faults

Coverage (%) Original proposed method coverage (%) FB no FB

C432

1,488

55.7

60.6

68.7

912

89.7

91.1

92.2

C880

2,004

80.6

83.4

85.6

1,282

90.1

91.1

91.7

C1908

5,451

68.8

69.2

70.8

2,947

88.6

89.1

89.6

C3540

10,666

77.8

78.2

82.3

11,396

92.3

93.5

93.8

C6288

14,812

99.4

99.5

99.5

16,612

86.4

86.7

87.8

Table 3 Test generation and execution times for the net list based implementations.

No. of remaining faults processed

Execution time (CPU seconds) No. of additional test Test Fault vectors generated generation simulation

C432

659

417

4

2

C880

388

209

2

6

C1908

1,288

433

21

47

C3540

2,359

953

90

407

C6288

90

2

2

27

7 Conclusions An efficient test generation system for bridging faults was presented. The effects of both active feedback and intermediate vales are taken into account when the test sets are generated. The concept of path distance in switch-level channel graphs is used to generate fault activation objectives that will minimize the driving strength of a general CMOS complex gate in order to create a dominance in driving strength between the two shorted drivers. By extracting appropriate objectives, the test generator tries to activate the fault without causing active feedback by either breaking the feedback or forcing the gate at the lower topological level to dominate over the gate at the upper level. The experimental results show that the coverage is significantly improved at a reasonable computational cost by adding the proposed test generation procedure. The increase in coverage varies between 1%-5% for most of the ISCAS85 circuits under realistic fault sets.

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