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Switching Device Dead Time Optimization of Resonant Double-Sided LCC Wireless Charging System for Electric Vehicles Xi Zhang 1, * 1

2

*

ID

, Ziyang Lai 1 , Rui Xiong 2, *

ID

, Zhe Li 1 , Zhimin Zhang 1 and Liang Song 1

School of Mechanical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China; [email protected] (Z.L.); [email protected] (Z.L.); [email protected] (Z.Z.); [email protected] (L.S.) National Engineering Laboratory for Electric Vehicles, School of Mechanical Engineering, Beijing Institute of Technology, Beijing 100081, China Correspondence: [email protected] (X.Z.); [email protected] (R.X.); Tel.: +86-139-1891-3376 (X.Z.); +86-10-68-914-070 (R.X.); Fax: +86-10-68-914-070 (R.X.)

Received: 19 September 2017; Accepted: 30 October 2017; Published: 3 November 2017

Abstract: Aiming at the reduction of the influence of the dead time setting on power level and efficiency of the inverter of double-sided LCC resonant wireless power transfer (WPT) system, a dead time soft switching optimization method for metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed. At first, the mathematic description of double-sided LCC resonant wireless charging system is established, and the operating mode is analyzed as well, deducing the quantitative characteristic that the secondary side compensation capacitor C2 can be adjusted to ensure that the circuit is inductive. A dead time optimization design method is proposed, contributing to achieving zero-voltage switching (ZVS) of the inverter, which is closely related to the performance of the WPT system. In the end, a prototype is built. The experimental results verify that dead time calculated by this optimized method can ensure the soft switching of the inverter MOSFET and promote the power and efficiency of the WPT. Keywords: inverter; dead time; soft switching; resonant wireless charging; electric vehicles

1. Introduction Electric vehicles (EVs) have gained popularity in recent years, for their inherent environmental benefits of reduced gas emissions [1,2]. Battery systems and charging techniques are the most critical technology supporting EV market penetration [3]. As a new wireless power transfer technology, the resonant wireless power transfer (WPT) technology, which is based on magnetic field coupling between the transmitting and receiving coils, has been seen development in recent years [4]. Compared with the traditional charging method (e.g., plug-in), the WPT technology eases drivers from the problem of cable-exposure, tripping hazards, and risks on the snowy or rainy days [5]. In addition, with the characteristics of flexible application, safety, and reliability, WPT technology has been applied to various applications, such as medical implantation equipment, underwater robots, and electric vehicle (EV) charging [6,7]. A typical EV WPT system consists of AC/DC (PFC and BUCK circuit), DC/AC (inverter circuit), resonant compensation network, transmitting coil and receiving coil, rectifier, and battery [8]. The inverter circuit is used to transfer DC power into high frequency square wave voltage, which is key for the compensation network to achieve resonance. This paper adopts a full-bridge inverter circuit to meet high power EV charging conditions. In the inverter, if the upper and lower leg of the MOSFET are switched on at the same time, it will lead to short circuit, once the input voltage is too

Energies 2017, 10, 1772; doi:10.3390/en10111772

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on until are completely switched which means therebeshould be high, the another MOSFETpair will of be MOSFETs damaged. Therefore, it is required thatoff, a pair of the MOSFETs switched dead-time between drive signals. on until another pairthe of MOSFETs are completely switched off, which means there should be dead-time Therefore, to signals. improve the efficiency of the WPT system, it is necessary to adopt an optimal between the drive dead-time. Mosttoprevious on the dead-time focused on it theis buck or boost circuitan[9], all of Therefore, improvework the efficiency of the WPT system, necessary to adopt optimal which are required to samplework the load current or voltage, increasing complexity control. dead-time. Most previous on the dead-time focused on the the buck or boost of circuit [9],Other all of work [10] has analyzed the relation between the optimal dead-time and turn-off related switching which are required to sample the load current or voltage, increasing the complexity of control. Other parameter, butanalyzed it did notthe focus on thebetween resonantthe compensation network. In [8], the double-sided LCC work [10] has relation optimal dead-time and turn-off related switching resonant compensation network and its tuning method was proposed, which realizes unity power parameter, but it did not focus on the resonant compensation network. In [8], the double-sided LCC factor at both the input and output. Moreover, thewas secondary series capacitor C2 provides the resonant compensation network and its tuningtuning method proposed, which realizes unity power zero-voltage condition for the tuning MOSFET the inverter, however, theCpaper did not factor at bothswitching the input (ZVS) and output. Moreover, theofsecondary series capacitor provides the 2 propose a specific dead-time design method. Therefore, in this paper, a dead-time design method is zero-voltage switching (ZVS) condition for the MOSFET of the inverter, however, the paper did not proposed, by tuning the secondary capacitor C2 to in ensure the circuit is inductive. Considering propose a specific dead-time designseries method. Therefore, this paper, a dead-time design method is the parasitic ofsecondary the MOSFET, it capacitor is crucial Cto2 to adopt thethe optimal to improve the proposed, bycapacitor tuning the series ensure circuitdead-time is inductive. Considering power and efficiency of the WPT system. An inappropriate dead-time will lead to damage of the parasitic capacitor of the MOSFET, it is crucial to adopt the optimal dead-time to improve the power MOSFETs. and efficiency of the WPT system. An inappropriate dead-time will lead to damage of MOSFETs. In In this this paper, paper, the the dead-time dead-time optimization optimization method method of of ZVS ZVS is is studied studied in in the the double-sided double-sided LCC LCC resonant resonant compensation compensation network. network. The The mathematical mathematical equivalent equivalent model model of of the the double-sided double-sided LCC LCC resonant resonant compensation compensation network network is is established, established, and and the the relation relation between between the the equivalent equivalent impedance impedance phase of the primary side and the incremental capacitance of the secondary side capacitor phase of the primary side and the incremental capacitance of the secondary side capacitor C C22 is is obtained in Section Section2.2.Section Section 3 analyzes the process of charge and discharge of the capacitor parasitic obtained in 3 analyzes the process of charge and discharge of the parasitic capacitor of theinMOSFET in aperiod, switching period, then of thethe influence of on thethe dead-time on the of the MOSFET a switching then the influence dead-time soft-switching is soft-switching is discussed. In the case of fixed secondary series compensation capacitor C2, the discussed. In the case of fixed secondary series compensation capacitor C2 , the optimization method optimization method of the in dead-time proposed inresults Section 4. Experimental verify the of the dead-time is proposed Section 4.isExperimental verify the feasibility results and correctness of feasibility and correctness of the proposed method in Section 5. Finally, Section 6 concludes this paper. the proposed method in Section 5. Finally, Section 6 concludes this paper. 2. Analysis Analysis of of Double-Sided Double-Sided LCC LCC Resonant Resonant Compensation Compensation Network Network Equivalent Characteristic 2. The configuration configurationofofthe thedouble-sided double-sided LCC resonant WPT system is shown in Figure The LCC resonant WPT system is shown in Figure 1. The1. The inverter consists of four MOSFETs(S(S ) andparasitic parasiticcapacitors capacitors (C (Cs1s1~C ~Cs4s4 parasiticantiparallel antiparallel inverter consists of four MOSFETs 1~S 4) 4and ), ),parasitic 1 ~S diodes (D the self-inductances of the transmitting and receiving respectively. diodes (D11~D ~D44). LL11and andL2 Lare 2 are the self-inductances of the transmitting and coils, receiving coils, Lp , Cp , and CL1p,are side compensation inductor and capacitors. Ls, Cs, and C2 are respectively. Cp, the andprimary C1 are the primary side compensation inductor and capacitors. Ls, Cs, andthe C2 secondary side compensation components, the secondary side is symmetrical to the primary M is are the secondary side compensation components, the secondary side is symmetrical to theside. primary the coefficient the two main coils. rectifier of fast consists recoveryof diodes (D5 ~D8 ), side. M is the inductance coefficient of inductance of the twoThe main coils.consists The rectifier fast recovery a filtering capacitor Co , and a filtering Lo . diodes (D5~D 8), a filtering capacitor Co,inductor and a filtering inductor Lo.

L0

S1

A

iLp Lp

D1 Cs1 S3 D3 Cs3

C1

Cp B D2 Cs2 S4

iLs Ls

D7

a

Uin

S2

M

C2

D5

L1 i1

D4 Cs4

C0

Cs

L2

Battery

Uo b

i2 D6

D8

Figure 1. Schematic of double-sided LCC resonant compensation network. Figure 1. Schematic of double-sided LCC resonant compensation network.

For the convenience of analysis, the parasitic resistance of the capacitors, inductors, and coils For the convenience analysis, the parasitic of theequivalent capacitors,network inductors, and coils are ignored. The primary of and secondary resonant resistance compensation is shown in are ignored. The primary and secondary resonant compensation equivalent network is shown in 2 2 Figure 2 [11]. Where U  U . Where RL represents the equivalent impedance of the battery e



o

and rectifier. According to [8], the receiving terminal can realize the unity power factor, thus, the

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√

Figure 2 [11]. Where Ue = 2 π 2 Uo . Where RL represents the equivalent impedance of the battery and 2U o 2 , equivalent rectifier. According to [8], terminal the unity power equivalent impedance canthe bereceiving represented as a can purerealize resistance, defined asfactor, Pout is the RL thus, the 2 2 out impedance can be represented as a pure resistance, defined as R L = π8PUouto , Pout is the8 P output power of output power of the WPT system. the WPT system.

Zin Zs C1

Lp

L2

L1 Uin

Cp

LS

C2

M

CS

RL

Ue

Figure 2. Equivalent schematic of double-sided LCC resonant compensation network. Figure 2. Equivalent schematic of double-sided LCC resonant compensation network.

The equivalent impedance of the secondary side circuit is The equivalent impedance of the secondary side circuit is 1 ( RL  j0 Ls )  1 1 ( R L + jω0 Ls ) ·jjω010CCss Z  +j  (1)(1) s 0L 2L2 + Zs = jω 0 j0jω C20 C2 RRL + jω Ls + jω110 Cs 0L j  L 0 s j0 Cs where ω0 is the resonant frequency. whereThe is the resonant frequency. 0equivalent impedance of secondary side Zr was reflected to the primary side by the mutual The equivalent impedance of secondary side Zr was reflected to the primary side by the mutual inductance M of the coils, Zr is defined as inductance M of the coils, Zr is defined as ω0 2 M 2 Zr =  2 M 2 (2) Z r  0 Zs (2)

Z

s Therefore, the equivalent impedance of the primary side is defined as

Therefore, the equivalent impedance of the1 primary side is defined as ( jω0 L1 + jω0 C1 + Zr ) · jω01Cp + jω0 L p (3) Zin = 1 1 ( jω j00 L11 + jω10 C1 +  ZZrr) +  jω01C p j0 C1 j0 C p Z in   j0 L p (3) 1 1 resonant According to [5], the parameters of double-sided LCC compensation network are j L   Zr  designed by the following equations 0 1 j0 C1 j0 C p  1 1 According to [5], the parameters double-sided compensation network are , Ls · CLCC  L p · Cof p = s = ωresonant 2 , ω02 0 (4) designed by the following equations  L1 − L p = 21 , L2 − Ls = 21 ◦ ω C ω C 0

1

0

2

1 1  , Ls  Cs  2 , p  C (3), p  the 2 equivalent  Land Substitute (2) and (4) into (1) impedance of the equivalent double-sided 0 0  LCC compensation network is given by (4)   L L  1 , L L  1 p 2 s  1  02C1 ω0 2 L2p L2s  02C2  Zin =

(5) M2 R L Substitute (2) and (4) into (1) and (3), the equivalent impedance of the equivalent double-sided It is a pure resistant load. In this LCC compensation network is given bycase, the inverter output voltage is in phase with the output current, and unity power factor achieves, but it is not a suitable condition for MOSFETs to achieve 2 0 2 L2p Lcapacitor ZVS. According to [8], by tuning the secondary series C2 , making the circuit be inductive s Z in  (5) 2 and thus providing conditions for the MOSFET to M achieve ZVS. R L

It is a pure resistant load. In this case, the inverter output voltage is in phase with the output current, and unity power factor achieves, but it is not a suitable condition for MOSFETs to achieve

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Energies 2017, 10, 1772 4 of 10 ZVS. According to [8], by tuning the secondary series capacitor C2, making the circuit be inductive and thus providing conditions for the MOSFET to achieve ZVS. After Aftertuning tuningthe theCC2, ,the theequivalent equivalentimpedance impedanceof ofthe theprimary primaryside sidecircuit circuitisis 2

' Zin  R+jX (6) 0 Zin = R + jX (6) L2p 0 2 L2p L2S C2 X L2p R ω0 2 L2p2L2S  2 ∆C2 , X = .C ) C here ∆C2 is the incremental value, R = MM · 2R R 20 M(C2 +(C ∆C22 )C ω0 M 2 . 2 2 L L , where ΔC2 is the incremental value, As is known, the ZVS condition mainly depends on the variation of load resistance and mutual As is known, the ZVS condition mainly depends on the variation of load resistance and mutual inductance, in this paper, by using the equivalent resistance Zin , which relates to the load resistance inductance, in this paper, by using the equivalent resistance Zin, which relates to the load resistance RL and mutual inductance M, as (5) and (6) shown above. It is a simple method to integrate various RL and mutual inductance M, as (5) and (6) shown above. It is a simple method to integrate various conditions into one variable. conditions into one variable.

3. Time Domain Analysis of the Double-Sided LCC Compensation Network 3. Time Domain Analysis of the Double-Sided LCC Compensation Network 3.1. Time Domain Analysis of Switching Mode 3.1. Time Domain Analysis of Switching Mode To facilitate the analysis, the following assumptions are made [12]: To facilitate the analysis, the following assumptions are made [12]: 1. All the MOSFETs and diodes are ideal; 1.2. All diodes are Allthe theMOSFETs capacitors,and inductors andideal; coils are ideal; 2. All the capacitors, inductors and coils are ideal; 3. Cs1 = Cs2 = Cs3 = Cs4 = Coss , where Coss is the output capacitor of the MOSFET; 3. Cs1 = Cs2= Cs3 = Cs4 = Coss, where Coss is the output capacitor of the MOSFET; Considering the dead-time, the main operating waveform is shown in Figure 3. Considering the dead-time, the main operating waveform is shown in Figure 3.

UGS S1&S4

S2&S3

S1&S4

iLp

t

UAB Uin

t

-Uin t0

t1 t2

t3 t4

Figure 3. Operation waveform of the inverter. Figure 3. Operation waveform of the inverter.

A switching cycle can be divided into four stages. The first half switching cycle is analyzed. A switching canthe be Sdivided stages. Theinverter first half switching cycle Mode 1 (t0, t1):cycle before 1 and S4into are four turned on, the output current iLp is analyzed. freewheeling Mode (t0 , D t14):, C before andbeen S4 are turned on,tothe inverter output current iLp istfreewheeling through D1 1and s1 andthe Cs4S1has discharged zero voltage. At the moment 1, S1, and S4 throughzero D1 and D4 , turn-on. Cs1 and C discharged to zero voltage. At the moment t1 , S1 , and S4 achieve voltage Us4 AB has = Uinbeen at this time. achieve zero turn-on. UAB U1inand at this Mode 2 voltage (t1, t2): at t1, both the= S S4 time. are turned off, the inverter output current iLp (the Mode 2 (t at t1 , MOSFET both theturned S1 andoffS4is are turned off,current) the inverter output iLp instantaneous current called cut-off is charging thecurrent capacitor 1 , t2 ): when instantaneous current whencapacitors MOSFET C turned called cut-off current) is charging the capacitor C(the s1 and Cs4 to voltage Uin, while s2 and off Cs3 is are discharged to zero voltage. Cs1 and Uin , while capacitors Cs2 and Cs3mode are discharged to zero The C mode 3 and mode 4 are similar to mode 1 and 2, respectively. Byvoltage. tuning the capacitor s4 to voltage The mode 3 and mode 4 are the similar to mode 1 andcan mode respectively. tuningthe theMOSFET capacitor C2 and dead-time optimization, turn-off current be 2, minimized andBy reduce C2 and loss. dead-time optimization, the turn-off current can be minimized and reduce the MOSFET turn-off turn-off loss. 3.2. The Influence of Dead-Time on Soft-Switching 3.2. The Influence of Dead-Time on Soft-Switching From the above analysis, the inverter output current charges and discharges the parasitic Fromofthe analysis, output charges discharges the parasitic capacitors theabove MOSFET duringthe theinverter dead-time. If thecurrent dead-time is setand inappropriately, it will lead capacitors of the MOSFET the dead-time. If the is set inappropriately, it will to a lower transmitting powerduring and efficiency. Therefore, the dead-time dead-time setting is crucial for MOSFET lead to a lower to achieve ZVS. transmitting power and efficiency. Therefore, the dead-time setting is crucial for MOSFET to achieve ZVS.

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Take the left arm of the inverter as an example, if the dead-time is set too short, the S1 will be turned on before the parasitic capacitor completely discharged, at the moment S1 is turned on, the parasitic capacitor short-circuits and produces an impulse current on the MOSFET, if the impulse current is larger than the pulsed drain current of the MOSFET, the MOSFET will break down. If the dead-time is set too long, when the parasitic capacitor C1 has been discharged completely, while the S1 do not be turned on, C1 is involved in the circuit resonant, and to be charged again, making S1 fail to achieve ZVS. It is found that there is a positive current on the S1 before the S1 is switched on, which will also produce an impulse current on the S1 . 4. Optimization Method of Dead-Time of Inverter MOSFET According to the above analysis, to ensure MOSFETs achieve ZVS and reduce the switching loss, on the one hand, the dead-time should be large enough to charge or discharge both the MOSFET’s and PCB’s parasitic capacitor, on the other hand, it is required that the inverter current be close to zero at the switching point, which means the dead-time should smaller than the diode freewheeling time. Therefore, the dead-time is required to meet with the expression tc + to f f < t DT < td where tc is the time of charging and discharging the parasitic capacitors, toff is the turn-off time of MOSFET, and td is the diode freewheeling time. 4.1. Calculation of Parasitic Capacitor Charging Time Since the time for charging and discharging the parasitic capacitor is relatively short compared to a switching period, the turn-off current Ioff can be approximately regarded as constant. According to [13], the time of parasitic capacitor charging and discharging is defined as tc = (2Coss + Cstray )

Uin Io f f

(7)

where Cstray is the parasitic capacitor of PCB. Considering the high order harmonics of the square voltage [14], the inverter first order output current is defined as √ 2U ILp_1st = 0 in sin(ωt + θ1st ) (8) Zin where θ 1st is the phase angle of the first order input impedance. At the moment MOSFET is turned off, t = π, the first order turn-off current is Io f f _1st =

√

2Uin

X R2 + X 2

(9)

Similarly, the high order turn-off current is given by

√ Io f f _(2k+1)th ≈

2Uin_(2k+1)th X(2k+1)th

R2(2k+1)th + X(22k+1)th

(10)

Therefore, the total turn-off current can be given by Io f f

=

∞

Io f f _1st + ∑ Io f f _(2k+1)th √

=

2Uin X R2 + X 2

k =1 √ ∞

X(2k+1)th 2Uin 2k +1 R2 + X(22k+1)th (2k+1)th k =1

+ ∑

(11)

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4.2. Calculation of Diode Freewheeling Time the above aboveanalysis, analysis,atatthe theend endofofthe the diode freewheeling, another pair MOSFETs should From the diode freewheeling, another pair MOSFETs should be be turned on, which means when the equivalent inductor of the circuit was completely discharged, turned on, which means when the equivalent inductor of the circuit was completely discharged, the the inverter current should be zero [15]. fact, using MATLAB,according accordingtoto(7), (7),all allthe thehigh high order order inverter current should be zero [15]. In In fact, byby using MATLAB, voltage UAB byby about 90◦90°. . Figure 4 shows the effect of theofhigh current lags lags behind behindthe theinverter inverteroutput output voltage UAB about Figure 4 shows the effect the order harmonic current on the inverter current. high order harmonic current on the inverter current.

iLp_1st

iLp_3rd

iLp_5th

t

iLp=iLp_1st+∑ iLp_mth

UAB Uin -Uin

t

Figure Figure 4. 4. Effect Effect of of high order inverter current.

From Figure 4, it is found that the zero-crossing point of the inverter current is mainly decided From Figure 4, it is found that the zero-crossing point of the inverter current is mainly decided by by the third harmonic current. Thus, the dead-time roughly meets with the following expression the third harmonic current. Thus, the dead-time roughly meets with the following expression

I

√ 2I rms _3rd sin(30td  3rd )

Lp _3rd ILp_3rd =

2Irms_3rd sin(3ω0 td + θ3rd )

So the diode freewheeling time is given by So the diode freewheeling time is given by

(12) (12)

 1 td  θ3rd 1 (13) 3rd 3 f 360 td = (13) 360 3 f where f is the inverter switching frequency and θ3rd is the phase angle of the third order input where f is the inverter switching frequency and θ 3rd is the phase angle of the third order input impedance. impedance. 5. Experiment Results 5. Experiment Results In order to validate the optimization method of dead time of switching devices in double-sided order to validate thea optimization method of the dead time of switching devices in double-sided LCC In resonant WPT system, prototype is established, experimental platform is shown in Figure 5. LCC The resonant WPT system, a prototype is established, the experimental platform is shown Figure 5. input voltage Uin = 100 V, output voltage Uo = 48 V, resonant frequency f = 95inkHz, the The input voltage U = 100 V, output voltage U = 48 V, resonant frequency f = 95 kHz, the transfer o transfer gap h = 150 mm.inThe parameter of the double-sided LCC resonant WPT system are listed in gap h = 150 mm. The parameter of the double-sided LCC resonant WPT system are listed in Table 1. Table 1.

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Cs

Rectifier

C2

L2

L1

C1

Inverter

Cp

Figure 5. Experiment platform. Figure 5. Experiment platform. Table 1. Double-sided LCC resonant WPT system parameter Table 1. Double-sided LCC resonant WPT system parameter.

Parameter Transmitting (receiving) Parametercoil L1(L2)/uH Compensation inductor Transmitting (receiving) coilLpL,1L(Ls/uH 2 )/uH Mutual inductor M/uH Compensation inductor Lp , Ls /uH Mutual inductorCM/uH Parallel capacitor p, Cs/nF Parallel capacitor C , CsC /nF p Primary series capacitor 1/nF Primary series capacitor C1 /nF Secondary series capacitor C 2/nF Secondary series capacitor C2 /nF Output equivalent resistance /Ω Output equivalent resistance RRLL/Ω

Value 260 Value 66 260 67.6 66 67.6 42.3 42.3 14.4 14.4 15.4 15.4 25.8 25.8

By increasing the capacity of C2, the WPT system circuit is inductive, the specific capacity of C2 By increasing the capacity of C2 , the WPT system circuit is inductive, the specific capacity of C2 can be set according to practical application, for convenience, in this paper we set ΔC2 = 1 nF. can be set according to practical application, for convenience, in this paper we set ∆C2 = 1 nF. In this work, Infineon IPW60R070C6 CoolMOS MOSFET is chosen as the inverter switches, its In this work, Infineon IPW60R070C6 CoolMOS MOSFET is chosen as the inverter switches, turn-off time is 88 ns, output capacitor Coss = 215 pF. From the above analysis and parameters, it can its turn-off time is 88 ns, output capacitor Coss = 215 pF. From the above analysis and parameters, it can be calculated that the dead-time should meet with the expression: be calculated that the dead-time should meet with the expression: 325ns  tDT  875ns (14) 325 ns < t DT < 875 ns (14) Considering the increase of MOSFET temperature, which may lead to the increase of MOSFET turn-on and turn-off the optimal dead-time is set 500 ns. may lead to the increase of MOSFET Considering thetime, increase of MOSFET temperature, which Figure shows the voltage and current of MOSFET when turn-on and6turn-off time, the optimal dead-time is set 500 ns. tDT = 500 ns, tDT = 1.2 us, respectively. Figure 6 shows the voltage and current of MOSFET when tDT = 500 ns, tDT = 1.2 us, respectively.

UDS

UDS

ID

ID (a)

(b)

Figure 6. Voltage and current of MOSFET (a) tDT = 500 ns; (b) tDT = 1.2 us.

be calculated that the dead-time should meet with the expression: 325ns  tDT  875ns

(14)

Considering the increase of MOSFET temperature, which may lead to the increase of MOSFET 8 of 10 time, the optimal dead-time is set 500 ns. Figure 6 shows the voltage and current of MOSFET when tDT = 500 ns, tDT = 1.2 us, respectively.

Energies 2017, 1772 turn-on and10,turn-off

UDS

UDS

ID

ID (a)

(b)

Figure 6. Voltage and current of MOSFET (a) tDT = 500 ns; (b) tDT = 1.2 us. Figure 6. Voltage and current of MOSFET (a) tDT = 500 ns; (b) tDT = 1.2 us. Energies 2017, 10, 1772

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From Figure 6a, before MOSFET turned on, there is negative current on the MOSFET because of From Figure 6a, before MOSFET turned on,Uthere is negative current on the MOSFET because of the diode freewheeling, when the drive voltage GS go rise to 90%, the MOSFET has forward current the freewheeling, when zero the drive voltage UGS goFrom rise to 90%, 6b, the because MOSFETofhas current (ID )diode and the MOSFET achieve voltage switch on. Figure theforward long dead-time, (I D) and the MOSFET achieve zero voltage switch on. From Figure 6b, because of the long dead-time, before the MOSFET is turned on, there is positive current on the MOSFET, even after the MOSFET is before is turned on, there is positive turnedthe off,MOSFET the voltage of the switch drops sharplycurrent to zero.on the MOSFET, even after the MOSFET is turned off, the voltage the switch to zero. Figure 7 shows theofvoltage and drops currentsharply of inverter when tDT = 500 ns, tDT = 1.2 us, respectively. Figure 7 shows the voltage and current of inverter when tDT = 500 ns, tDT = 1.2 us, respectively.

ILp

ILp

UAB

UAB (a)

(b)

Figure 7. Voltage and current of inverter (a) tDT = 500 ns; (b) tDT = 1.2 us. Figure 7. Voltage and current of inverter (a) tDT = 500 ns; (b) tDT = 1.2 us.

From Figure 7b, if the dead-time is too large, there is high frequency oscillation of the inverter. Figure 7b, if results, the dead-time is toosetting large, there high frequency oscillation ofto the inverter. FromFrom the experimental a dead-time that isistoo short or too long will lead distortion From the experimental results, a dead-time setting that is too short or too long will lead to distortion output voltage and current of the inverter, causing a lower efficiency and transmitting power of the output voltage and current of the inverter, causing a lower efficiency and transmitting power of the WPT system. WPTItsystem. is known that the longer the dead time, the less effective value of the inverter voltage. When It is known the longer theindead time, the conduction less effectiveloss value thethe inverter voltage. When the the input powerthat is about 100 W, Figure 8, the of of both dead-time situations is input power is about 100 W, in Figure 8, the conduction loss of both the dead-time situations is about about 0.02 W, much less than the switching loss. It also shows that the turning on/off loss is much 0.02 W, much thandead the switching loss. It also shows that turningdead on/off lossthe is much smaller if smaller if the less proper time is chosen. By selecting thethe optimal time, MOSFETs can the proper is chosen. Byand selecting thedistortion, optimal dead time, the MOSFETsefficiency. can achieve ZVS achieve ZVSdead and time eliminate voltage current promoting transmitting and eliminate voltage and current distortion, promoting transmitting efficiency.

Loss(W) Switching Loss Comparison 4 3 2 1 0 MOSFET

MOSFET

dead time=500ns

dead time=1.2us

WPT system. It is known that the longer the dead time, the less effective value of the inverter voltage. When the input power is about 100 W, in Figure 8, the conduction loss of both the dead-time situations is about 0.02 W, much less than the switching loss. It also shows that the turning on/off loss is much Energies 2017, 10, 1772 10 smaller if the proper dead time is chosen. By selecting the optimal dead time, the MOSFETs9 of can achieve ZVS and eliminate voltage and current distortion, promoting transmitting efficiency.

Loss(W) Switching Loss Comparison 4 3 2 1 0 MOSFET

MOSFET

dead time=500ns

dead time=1.2us

Conduction loss

Turn on/off loss

dead time loss

Figure 8. Switching loss comparison. Figure 8. Switching loss comparison.

6. Conclusions 6. Conclusions In this paper, the problem of soft-switching of the MOSFET in the double-sided LCC resonant this paper, the problem of soft-switching in the double-sided LCC resonant WPTInsystem is studied and analyzed. Based of onthe theMOSFET theoretical calculation of the equivalent WPT system is studied and analyzed. Based on the theoretical calculation of the equivalent impedance, impedance, the condition of MOSFET to achieve ZVS is verified. By analyzing the time-domain the condition of MOSFET to achieve ZVS is of verified. By analyzing the is time-domain model an of model of a switching period, the influence dead-time on MOSFET studied. Finally, a switching period, the influence of dead-time on MOSFET is studied. Finally, an optimization optimization of switching device dead-time of double-sided LCC WPT system is proposed. The of switching device dead-time of double-sided LCC WPT system is proposed. The feasibility of this feasibility of this method is verified by experiment results. method is verified by experiment results. Acknowledgments: This work was supported in part by the National Natural Science Foundation of China under Grant No. 51677118, the Joint Funds of the National Natural Science Foundation of China under Grant No. U1564206, the Science and Technology Commission of Shanghai Municipality under Grant 16510711500 and 16PJD030, Beijing Municipal Science and Technology Project under Grant No. Z171100000917013, the National Science and Technology Support Program under Grant No. 2015BAG04B00, and International Science & Technology Cooperation Program of China under contract No. 2016YFE0102200. Author Contributions: Xi Zhang proposed the original idea and built the mathematical model. Ziyang Lai developed all the hardware. Rui Xiong helped improve the parameter analysis. Zhe Li did some simulation work. Zhiming Zhang designed the primary and secondary coils. Liang Song completed the software. All authors carried out the data analysis, discussed the results and contributed to writing the paper. Conflicts of Interest: The authors declare no conflict of interest.

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